Driver to drive?

[Nico Coesel]

John Larkin <jjlarkin@highNOTlandTHIStechnologyPART.com> wrote:

On Wed, 26 Nov 2008 10:05:06 -0800 (PST), palvarez
pabloalvarezsanchez@gmail.com> wrote:

Hi,

For several reasons a need very low jitter on some of my outputs. I
was thinking of using LVDS for my I/Os and of course I do not consider
using a clock manager. Do you have an idea of the order of magnitude
of jitter one can get? What fpga would you recomend for a low cost
small design?

Cheers

Pablo


Here's a signal that has made three independent non-trivial in/out
passes through a Spartan3, plus passed through six external SSI CMOS
chips. Total jitter of that whole chain is below 20 ps RMS.

ftp://jjlarkin.lmi.net/Jitter3.jpg

I presume this is without routing the clock through the DCM

--
Failure does not prove something is impossible, failure simply
indicates you are not using the right tools...
"If it doesn't fit, use a bigger hammer!"
--------------------------------------------------------------

 

[John Larkin]

On Thu, 26 Mar 2009 23:02:35 GMT, nico@puntnl.niks (Nico Coesel)
wrote:

John Larkin <jjlarkin@highNOTlandTHIStechnologyPART.com> wrote:

On Wed, 26 Nov 2008 10:05:06 -0800 (PST), palvarez
pabloalvarezsanchez@gmail.com> wrote:

Hi,

For several reasons a need very low jitter on some of my outputs. I
was thinking of using LVDS for my I/Os and of course I do not consider
using a clock manager. Do you have an idea of the order of magnitude
of jitter one can get? What fpga would you recomend for a low cost
small design?

Cheers

Pablo


Here's a signal that has made three independent non-trivial in/out
passes through a Spartan3, plus passed through six external SSI CMOS
chips. Total jitter of that whole chain is below 20 ps RMS.

ftp://jjlarkin.lmi.net/Jitter3.jpg

I presume this is without routing the clock through the DCM

Yes! One of the three FPGA inputs is in fact a global clock, but it's
not multiplied or anything.

In another mode, we do double a 40 MHz clock to 80 in a DCM. That adds
about 80 ps p-p jitter, because it wiggles alternate 80 MHz clock
edges.

John

 

[Joerg]

John Larkin wrote:

On Thu, 26 Mar 2009 19:34:22 -0000, "Andrew Holme" <ah@nospam.co.uk
wrote:

"John Larkin" <jjlarkin@highNOTlandTHIStechnologyPART.com> wrote in message
news:nhfns4lrd245pvu2lt4pnn03lio466j5ti@4ax.com...
On Wed, 26 Nov 2008 10:05:06 -0800 (PST), palvarez
pabloalvarezsanchez@gmail.com> wrote:

Hi,

For several reasons a need very low jitter on some of my outputs. I
was thinking of using LVDS for my I/Os and of course I do not consider
using a clock manager. Do you have an idea of the order of magnitude
of jitter one can get? What fpga would you recomend for a low cost
small design?

Cheers

Pablo

Here's a signal that has made three independent non-trivial in/out
passes through a Spartan3, plus passed through six external SSI CMOS
chips. Total jitter of that whole chain is below 20 ps RMS.

ftp://jjlarkin.lmi.net/Jitter3.jpg


We were fairly impressed. Spartans are like having a few thousand 10KH
ECL gates on a $20 chip.

John

I've just built a fractional-N synthesizer using a Spartan 3. The reference
frequency comes from an LVDS-output crystal oscillator. The VCO frequency
is fed into the opposite side of the FPGA using an LVDS-output comparator
and the (AD9901 style) PFD output from the FPGA to the loop filter is also
LVDS on a third physical side.

Inside the FPGA, the VCO divider and reference divider are on local clocks
confined to small regions around the pads where they enter. BUFGCE
primitives are used to gate the clocks so I only send edges over the global
clock network when a divider resets. The AD9901 PFD ensures that the VCO
and reference divider outputs are 180 degrees out of phase.

Some years ago, I built a cruder fractional-N synth using a 5V Altera PLCC84
CPLD. It worked quite well, but there was some interation between the VCO
and reference frequencies which caused integer-N boundary spurs. I see no
trace of these spurs on my new Spartan 3 design, and the phase noise is much
lower. I'm seeing around -95 dBc/Hz at 100 Hz offsets at the moment; and I
haven't finished tweaking things yet.


They say don't attempt analogue functions in FPGAs; but it seems to work
remarkably well in the Spartan 3, which is fully static when I'm not
clocking it.



The Spartan LVDS inputs are pretty good r-r comparators. And you can
make lots of good, cheap delta-sigma dacs from an FPGA.

You can do cool analog things with FPGAs. ...

Can you tell us more about that? Sounds very interesting. As long as it
doesn't rely on really undocumented parameters like leakage currents, or
goes away when the family gets discontinued (one reason I don't like
FPGA much).

... You can also get into a heap of trouble.

Probably of the exothermic kind where the smoke alarms kick in and the
sprinkler system comes on

--
Regards, Joerg

http://www.analogconsultants.com/

"gmail" domain blocked because of excessive spam.
Use another domain or send PM.

 

[John Larkin]

On Sat, 28 Mar 2009 13:35:04 -0700, Joerg
<notthisjoergsch@removethispacbell.net> wrote:

John Larkin wrote:
On Thu, 26 Mar 2009 19:34:22 -0000, "Andrew Holme" <ah@nospam.co.uk
wrote:

"John Larkin" <jjlarkin@highNOTlandTHIStechnologyPART.com> wrote in message
news:nhfns4lrd245pvu2lt4pnn03lio466j5ti@4ax.com...
On Wed, 26 Nov 2008 10:05:06 -0800 (PST), palvarez
pabloalvarezsanchez@gmail.com> wrote:

Hi,

For several reasons a need very low jitter on some of my outputs. I
was thinking of using LVDS for my I/Os and of course I do not consider
using a clock manager. Do you have an idea of the order of magnitude
of jitter one can get? What fpga would you recomend for a low cost
small design?

Cheers

Pablo

Here's a signal that has made three independent non-trivial in/out
passes through a Spartan3, plus passed through six external SSI CMOS
chips. Total jitter of that whole chain is below 20 ps RMS.

ftp://jjlarkin.lmi.net/Jitter3.jpg


We were fairly impressed. Spartans are like having a few thousand 10KH
ECL gates on a $20 chip.

John

I've just built a fractional-N synthesizer using a Spartan 3. The reference
frequency comes from an LVDS-output crystal oscillator. The VCO frequency
is fed into the opposite side of the FPGA using an LVDS-output comparator
and the (AD9901 style) PFD output from the FPGA to the loop filter is also
LVDS on a third physical side.

Inside the FPGA, the VCO divider and reference divider are on local clocks
confined to small regions around the pads where they enter. BUFGCE
primitives are used to gate the clocks so I only send edges over the global
clock network when a divider resets. The AD9901 PFD ensures that the VCO
and reference divider outputs are 180 degrees out of phase.

Some years ago, I built a cruder fractional-N synth using a 5V Altera PLCC84
CPLD. It worked quite well, but there was some interation between the VCO
and reference frequencies which caused integer-N boundary spurs. I see no
trace of these spurs on my new Spartan 3 design, and the phase noise is much
lower. I'm seeing around -95 dBc/Hz at 100 Hz offsets at the moment; and I
haven't finished tweaking things yet.


They say don't attempt analogue functions in FPGAs; but it seems to work
remarkably well in the Spartan 3, which is fully static when I'm not
clocking it.



The Spartan LVDS inputs are pretty good r-r comparators. And you can
make lots of good, cheap delta-sigma dacs from an FPGA.

You can do cool analog things with FPGAs. ...


Can you tell us more about that? Sounds very interesting. As long as it
doesn't rely on really undocumented parameters like leakage currents, or
goes away when the family gets discontinued (one reason I don't like
FPGA much).

How are you going to get an edge on your competition unless you use
stuff that they don't know?

John

 

[krw]

On Thu, 26 Mar 2009 13:39:47 -0700, John Larkin
<jjlarkin@highNOTlandTHIStechnologyPART.com> wrote:

On Thu, 26 Mar 2009 19:34:22 -0000, "Andrew Holme" <ah@nospam.co.uk
wrote:


"John Larkin" <jjlarkin@highNOTlandTHIStechnologyPART.com> wrote in message
news:nhfns4lrd245pvu2lt4pnn03lio466j5ti@4ax.com...
On Wed, 26 Nov 2008 10:05:06 -0800 (PST), palvarez
pabloalvarezsanchez@gmail.com> wrote:

Hi,

For several reasons a need very low jitter on some of my outputs. I
was thinking of using LVDS for my I/Os and of course I do not consider
using a clock manager. Do you have an idea of the order of magnitude
of jitter one can get? What fpga would you recomend for a low cost
small design?

Cheers

Pablo


Here's a signal that has made three independent non-trivial in/out
passes through a Spartan3, plus passed through six external SSI CMOS
chips. Total jitter of that whole chain is below 20 ps RMS.

ftp://jjlarkin.lmi.net/Jitter3.jpg


We were fairly impressed. Spartans are like having a few thousand 10KH
ECL gates on a $20 chip.

John


I've just built a fractional-N synthesizer using a Spartan 3. The reference
frequency comes from an LVDS-output crystal oscillator. The VCO frequency
is fed into the opposite side of the FPGA using an LVDS-output comparator
and the (AD9901 style) PFD output from the FPGA to the loop filter is also
LVDS on a third physical side.

Inside the FPGA, the VCO divider and reference divider are on local clocks
confined to small regions around the pads where they enter. BUFGCE
primitives are used to gate the clocks so I only send edges over the global
clock network when a divider resets. The AD9901 PFD ensures that the VCO
and reference divider outputs are 180 degrees out of phase.

Some years ago, I built a cruder fractional-N synth using a 5V Altera PLCC84
CPLD. It worked quite well, but there was some interation between the VCO
and reference frequencies which caused integer-N boundary spurs. I see no
trace of these spurs on my new Spartan 3 design, and the phase noise is much
lower. I'm seeing around -95 dBc/Hz at 100 Hz offsets at the moment; and I
haven't finished tweaking things yet.


They say don't attempt analogue functions in FPGAs; but it seems to work
remarkably well in the Spartan 3, which is fully static when I'm not
clocking it.



The Spartan LVDS inputs are pretty good r-r comparators. And you can
make lots of good, cheap delta-sigma dacs from an FPGA.

I asked the Altera rep (actually from Arrow) to check on that for me.
It seemed like a possibility. I have a bunch of ideas if this is
really a possibility (noise and such).

You can do cool analog things with FPGAs. You can also get into a heap
of trouble.

I may try? So far the other engineers don't think it can be done.
We'll see. ;-)

 

[John Larkin]

On Sat, 28 Mar 2009 16:09:45 -0700 (PDT), rickman <gnuarm@gmail.com>
wrote:

On Mar 28, 6:52 pm, John Larkin
jjlar...@highNOTlandTHIStechnologyPART.com> wrote:
On Sat, 28 Mar 2009 13:35:04 -0700, Joerg



notthisjoerg...@removethispacbell.net> wrote:
John Larkin wrote:
On Thu, 26 Mar 2009 19:34:22 -0000, "Andrew Holme" <a...@nospam.co.uk
wrote:

"John Larkin" <jjlar...@highNOTlandTHIStechnologyPART.com> wrote in message
news:nhfns4lrd245pvu2lt4pnn03lio466j5ti@4ax.com...
On Wed, 26 Nov 2008 10:05:06 -0800 (PST), palvarez
pabloalvarezsanc...@gmail.com> wrote:

Hi,

For several reasons a need very low jitter on some of my outputs. I
was thinking of using LVDS for my I/Os and of course I do not consider
using a clock manager. Do you have an idea of the order of magnitude
of jitter one can get? What fpga would you recomend for a low cost
small design?

Cheers

Pablo

Here's a signal that has made three independent non-trivial in/out
passes through a Spartan3, plus passed through six external SSI CMOS
chips. Total jitter of that whole chain is below 20 ps RMS.

ftp://jjlarkin.lmi.net/Jitter3.jpg

We were fairly impressed. Spartans are like having a few thousand 10KH
ECL gates on a $20 chip.

John

I've just built a fractional-N synthesizer using a Spartan 3.  The reference
frequency comes from an LVDS-output crystal oscillator.  The VCO frequency
is fed into the opposite side of the FPGA using an LVDS-output comparator
and the (AD9901 style) PFD output from the FPGA to the loop filter is also
LVDS on a third physical side.

Inside the FPGA, the VCO divider and reference divider are on local clocks
confined to small regions around the pads where they enter.  BUFGCE
primitives are used to gate the clocks so I only send edges over the global
clock network when a divider resets.  The AD9901 PFD ensures that the VCO
and reference divider outputs are 180 degrees out of phase.

Some years ago, I built a cruder fractional-N synth using a 5V Altera PLCC84
CPLD.  It worked quite well, but there was some interation between the VCO
and reference frequencies which caused integer-N boundary spurs.  I see no
trace of these spurs on my new Spartan 3 design, and the phase noise is much
lower.  I'm seeing around -95 dBc/Hz at 100 Hz offsets at the moment; and I
haven't finished tweaking things yet.

They say don't attempt analogue functions in FPGAs; but it seems to work
remarkably well in the Spartan 3, which is fully static when I'm not
clocking it.

The Spartan LVDS inputs are pretty good r-r comparators. And you can
make lots of good, cheap delta-sigma dacs from an FPGA.

You can do cool analog things with FPGAs. ...

Can you tell us more about that? Sounds very interesting. As long as it
doesn't rely on really undocumented parameters like leakage currents, or
goes away when the family gets discontinued (one reason I don't like
FPGA much).

How are you going to get an edge on your competition unless you use
stuff that they don't know?

John

You mean the stuff that can change without warning? One place where I
worked had a design that was using FET transistors to control the
current to control the current to an LED backlight, V in and I out.
Heck, they publish a curve for that right? That would be a *typical*
curve. After using this part for some years, the circuit stopped
working right with a dim backlight. The FET maker had "improved"
their process and changed the threshold voltage just a bit, still
within spec, but not the same curve. So now the ROM values for the
DAC didn't let enough current pass.

Using a fet open-loop as a linear current controller is more risk that
I'm willing to take... especially when it's easy to do it right.

It's not likely that the LVDS circuit would be changed at any point in
the future... I guess that is where the "trouble" part comes in.

Rick

It's a matter of calculated risk. If a part behaves in some useful but
undocumented way, and the process is likely stable, the performance
may be worth the risk. I think I've been burned more times by
semiconductors being discontinued than by their behavior changing.

On a thing we're doing now, we're using some SOT-89 power phemts as
switches. These are RF parts, and are barely specified for DC
behavior; hell, lots of RF fets are totally unspecified for DC
behavior. So we're including a place to install a trimpot in case the
transfer curves don't stay put.

John

 

[John Larkin]

On Thu, 26 Mar 2009 19:34:22 -0000, "Andrew Holme" <ah@nospam.co.uk>
wrote:

"John Larkin" <jjlarkin@highNOTlandTHIStechnologyPART.com> wrote in message
news:nhfns4lrd245pvu2lt4pnn03lio466j5ti@4ax.com...
On Wed, 26 Nov 2008 10:05:06 -0800 (PST), palvarez
pabloalvarezsanchez@gmail.com> wrote:

Hi,

For several reasons a need very low jitter on some of my outputs. I
was thinking of using LVDS for my I/Os and of course I do not consider
using a clock manager. Do you have an idea of the order of magnitude
of jitter one can get? What fpga would you recomend for a low cost
small design?

Cheers

Pablo


Here's a signal that has made three independent non-trivial in/out
passes through a Spartan3, plus passed through six external SSI CMOS
chips. Total jitter of that whole chain is below 20 ps RMS.

ftp://jjlarkin.lmi.net/Jitter3.jpg


We were fairly impressed. Spartans are like having a few thousand 10KH
ECL gates on a $20 chip.

John


I've just built a fractional-N synthesizer using a Spartan 3. The reference
frequency comes from an LVDS-output crystal oscillator. The VCO frequency
is fed into the opposite side of the FPGA using an LVDS-output comparator
and the (AD9901 style) PFD output from the FPGA to the loop filter is also
LVDS on a third physical side.

Inside the FPGA, the VCO divider and reference divider are on local clocks
confined to small regions around the pads where they enter. BUFGCE
primitives are used to gate the clocks so I only send edges over the global
clock network when a divider resets. The AD9901 PFD ensures that the VCO
and reference divider outputs are 180 degrees out of phase.

Some years ago, I built a cruder fractional-N synth using a 5V Altera PLCC84
CPLD. It worked quite well, but there was some interation between the VCO
and reference frequencies which caused integer-N boundary spurs. I see no
trace of these spurs on my new Spartan 3 design, and the phase noise is much
lower. I'm seeing around -95 dBc/Hz at 100 Hz offsets at the moment; and I
haven't finished tweaking things yet.


They say don't attempt analogue functions in FPGAs; but it seems to work
remarkably well in the Spartan 3, which is fully static when I'm not
clocking it.

We did some playing with FPGA-based PLLs. The classic charge-pump PDs
didn't work very well. This works...


fpga_up------ak----R-----+-------opamp
|
|
|
fpga_dn------ka----R-----+


where AK and KA are schottky diodes feeding an opamp integrator (P+I
control) thing, and the up/down things pulse in the obvious
polarities. The fpga outputs are hard and fast, not tri-state, and
overlap a good bit. No deadband, fast as all getout, low phase noise.

John

 

[rickman]

On Mar 28, 6:52 pm, John Larkin
<jjlar...@highNOTlandTHIStechnologyPART.com> wrote:

On Sat, 28 Mar 2009 13:35:04 -0700, Joerg



notthisjoerg...@removethispacbell.net> wrote:
John Larkin wrote:
On Thu, 26 Mar 2009 19:34:22 -0000, "Andrew Holme" <a...@nospam.co.uk
wrote:

"John Larkin" <jjlar...@highNOTlandTHIStechnologyPART.com> wrote in message
news:nhfns4lrd245pvu2lt4pnn03lio466j5ti@4ax.com...
On Wed, 26 Nov 2008 10:05:06 -0800 (PST), palvarez
pabloalvarezsanc...@gmail.com> wrote:

Hi,

For several reasons a need very low jitter on some of my outputs. I
was thinking of using LVDS for my I/Os and of course I do not consider
using a clock manager. Do you have an idea of the order of magnitude
of jitter one can get? What fpga would you recomend for a low cost
small design?

Cheers

Pablo

Here's a signal that has made three independent non-trivial in/out
passes through a Spartan3, plus passed through six external SSI CMOS
chips. Total jitter of that whole chain is below 20 ps RMS.

ftp://jjlarkin.lmi.net/Jitter3.jpg

We were fairly impressed. Spartans are like having a few thousand 10KH
ECL gates on a $20 chip.

John

I've just built a fractional-N synthesizer using a Spartan 3.  The reference
frequency comes from an LVDS-output crystal oscillator.  The VCO frequency
is fed into the opposite side of the FPGA using an LVDS-output comparator
and the (AD9901 style) PFD output from the FPGA to the loop filter is also
LVDS on a third physical side.

Inside the FPGA, the VCO divider and reference divider are on local clocks
confined to small regions around the pads where they enter.  BUFGCE
primitives are used to gate the clocks so I only send edges over the global
clock network when a divider resets.  The AD9901 PFD ensures that the VCO
and reference divider outputs are 180 degrees out of phase.

Some years ago, I built a cruder fractional-N synth using a 5V Altera PLCC84
CPLD.  It worked quite well, but there was some interation between the VCO
and reference frequencies which caused integer-N boundary spurs.  I see no
trace of these spurs on my new Spartan 3 design, and the phase noise is much
lower.  I'm seeing around -95 dBc/Hz at 100 Hz offsets at the moment; and I
haven't finished tweaking things yet.

They say don't attempt analogue functions in FPGAs; but it seems to work
remarkably well in the Spartan 3, which is fully static when I'm not
clocking it.

The Spartan LVDS inputs are pretty good r-r comparators. And you can
make lots of good, cheap delta-sigma dacs from an FPGA.

You can do cool analog things with FPGAs. ...

Can you tell us more about that? Sounds very interesting. As long as it
doesn't rely on really undocumented parameters like leakage currents, or
goes away when the family gets discontinued (one reason I don't like
FPGA much).

How are you going to get an edge on your competition unless you use
stuff that they don't know?

John

You mean the stuff that can change without warning? One place where I
worked had a design that was using FET transistors to control the
current to control the current to an LED backlight, V in and I out.
Heck, they publish a curve for that right? That would be a *typical*
curve. After using this part for some years, the circuit stopped
working right with a dim backlight. The FET maker had "improved"
their process and changed the threshold voltage just a bit, still
within spec, but not the same curve. So now the ROM values for the
DAC didn't let enough current pass.

It's not likely that the LVDS circuit would be changed at any point in
the future... I guess that is where the "trouble" part comes in.

Rick

 

[Joerg]

John Larkin wrote:

On Sat, 28 Mar 2009 13:35:04 -0700, Joerg
notthisjoergsch@removethispacbell.net> wrote:

John Larkin wrote:
On Thu, 26 Mar 2009 19:34:22 -0000, "Andrew Holme" <ah@nospam.co.uk
wrote:

"John Larkin" <jjlarkin@highNOTlandTHIStechnologyPART.com> wrote in message
news:nhfns4lrd245pvu2lt4pnn03lio466j5ti@4ax.com...
On Wed, 26 Nov 2008 10:05:06 -0800 (PST), palvarez
pabloalvarezsanchez@gmail.com> wrote:

Hi,

For several reasons a need very low jitter on some of my outputs. I
was thinking of using LVDS for my I/Os and of course I do not consider
using a clock manager. Do you have an idea of the order of magnitude
of jitter one can get? What fpga would you recomend for a low cost
small design?

Cheers

Pablo
Here's a signal that has made three independent non-trivial in/out
passes through a Spartan3, plus passed through six external SSI CMOS
chips. Total jitter of that whole chain is below 20 ps RMS.

ftp://jjlarkin.lmi.net/Jitter3.jpg


We were fairly impressed. Spartans are like having a few thousand 10KH
ECL gates on a $20 chip.

John

I've just built a fractional-N synthesizer using a Spartan 3. The reference
frequency comes from an LVDS-output crystal oscillator. The VCO frequency
is fed into the opposite side of the FPGA using an LVDS-output comparator
and the (AD9901 style) PFD output from the FPGA to the loop filter is also
LVDS on a third physical side.

Inside the FPGA, the VCO divider and reference divider are on local clocks
confined to small regions around the pads where they enter. BUFGCE
primitives are used to gate the clocks so I only send edges over the global
clock network when a divider resets. The AD9901 PFD ensures that the VCO
and reference divider outputs are 180 degrees out of phase.

Some years ago, I built a cruder fractional-N synth using a 5V Altera PLCC84
CPLD. It worked quite well, but there was some interation between the VCO
and reference frequencies which caused integer-N boundary spurs. I see no
trace of these spurs on my new Spartan 3 design, and the phase noise is much
lower. I'm seeing around -95 dBc/Hz at 100 Hz offsets at the moment; and I
haven't finished tweaking things yet.


They say don't attempt analogue functions in FPGAs; but it seems to work
remarkably well in the Spartan 3, which is fully static when I'm not
clocking it.


The Spartan LVDS inputs are pretty good r-r comparators. And you can
make lots of good, cheap delta-sigma dacs from an FPGA.

You can do cool analog things with FPGAs. ...

Can you tell us more about that? Sounds very interesting. As long as it
doesn't rely on really undocumented parameters like leakage currents, or
goes away when the family gets discontinued (one reason I don't like
FPGA much).

How are you going to get an edge on your competition unless you use
stuff that they don't know?

Oh, I do a lot of unorthodox stuff. Using 74HCU or CD4000 in analog
circuits, switcher FETs in servos, RF parts for digital functions and so
on. I am just curious what can be done with an FPGA in that respect.

A long time ago I was looking into using the old Intel CPLD series that
way because of they microamp capabilities. Boy was I glad I didn't,
shortly after they ditched the whole line. Thing is, most of my designs
are targeted for more than a decade in production. And no trimpots or
calibration allowed unless that can be automated.

--
Regards, Joerg

http://www.analogconsultants.com/

"gmail" domain blocked because of excessive spam.
Use another domain or send PM.

 

[john]

On Sat 28-Mar-2009 00:14, John Weston
<invalid@earlsway.invalid> wrote:

In article <2OydndXBso-NpVDUnZ2dnUVZ8oKWnZ2d@bt.com>,
"Kráftéé" wrote:

Think you may have just jumped the gun a little there.

The OP stated that they are on a Virgin Media Landline, which
probably means cable, which means no DSL signal on telephone.

The only problem that they may have then is if the RJ11 cable
is not compatable pin to pin..

So I did... - providing it is cable and not a LLU (C&W or the
old Bulldog network)

Thanks for the info. No worries! My ADSL adapters were just spare
in a drawer.

-------------

Better to get some new adaptors ...

(a) ...to connect an RJ11 plug to an BT-style wall socket.
(b) ...to connect an RTJ9/4P4C plug to the BT wall socket.

These RJ plugs attach to a little device which permits recording of
phone conversation. I presume I wouldn't want to use those adaptors
advertised as a "crosswired". Is this correct?

--------------

I'm sure I once saw some good web pages about variations in how
particular telephone wires are allocated to connectors. Maybe
someone has a link to an article about the wiring of:

(1) telephone line cords
(2) handset curly cords.

 

[glen herrmannsfeldt]

In comp.arch.fpga Joerg <notthisjoergsch@removethispacbell.net> wrote:

Oh, I do a lot of unorthodox stuff. Using 74HCU or CD4000 in analog
circuits, switcher FETs in servos, RF parts for digital functions and so
on. I am just curious what can be done with an FPGA in that respect.

I once knew someone who built an FM radio transmitter
using a 74S04 as the output stage. I suppose
cheaper than RF transistors at the time.

-- glen

 

[John Weston]

In article <Xns9BDD2DAEDA7DA451E7A@69.16.185.247>, "john" wrote:

Thanks for the info. No worries! My ADSL adapters were just spare
in a drawer.

-------------

Better to get some new adaptors ...

(a) ...to connect an RJ11 plug to an BT-style wall socket.

I've had no problems using an old ADSL filter as a simple RJ11 to BT
converter, since that part is straight through. I don't think I've had
to use one on a Virgin cable connection, if that's what you have. I
suppose the filter on the phone output could develop a fault but I've
not seen one. If necessary, you can cut the wires to the filter inside
the housing, since a cheap ADSL filter will usually be cheaper than the
straight converter, see
http://www.maplin.co.uk/Module.aspx?ModuleNo=12494

(b) ...to connect an RTJ9/4P4C plug to the BT wall socket.

I've not met the RTJ9 A 4P4C, sometimes incorrectly called an RJ9
is a phone handset/headset connector and a handset shouldn't normally be
connected directly to a BT socket. I've got one on a call recorder
adapter, that goes between phone and headset but it is incompatible with
direct connection to a phone line.

These RJ plugs attach to a little device which permits recording of
phone conversation. I presume I wouldn't want to use those adaptors
advertised as a "crosswired". Is this correct?

The two types of RJ11 are connects to the two inner connectors (2&3) or
to the two outer (1&4). The more ususal one, for the first phone line,
is the first. The line 1 converter connects the RJ11 pins 2&3 to 2&5 on
the BT plug. The line 2 converter is 1&4 on the RJ11 to 2&5 on BT. The
polarity doesn't normally matter, so cross-wiring them shouldn't stop it
working.

--------------

I'm sure I once saw some good web pages about variations in how
particular telephone wires are allocated to connectors. Maybe
someone has a link to an article about the wiring of:

(1) telephone line cords
(2) handset curly cords.

Try here: http://telephonesuk.co.uk/wiring_info.htm (The "Grey" should

be "Slate" since G = Green)

--
John W
To mail me replace the obvious with co.uk twice

 

[Jan Panteltje]

On a sunny day (Sat, 28 Mar 2009 17:38:50 -0700) it happened Joerg
<notthisjoergsch@removethispacbell.net> wrote in
<Dqzzl.27297$ZP4.3376@nlpi067.nbdc.sbc.com>:

How are you going to get an edge on your competition unless you use
stuff that they don't know?


Oh, I do a lot of unorthodox stuff. Using 74HCU or CD4000 in analog
circuits, switcher FETs in servos, RF parts for digital functions and so
on. I am just curious what can be done with an FPGA in that respect.

Although I am by no means an FPGA expert, I have done some funny things
with my Spartan 2 FPGA board.
For example did video out with a simple R2R network connected to some
output pins (8 bits), video conversion from 50Hz V and 15625Hz H to
50Hz V and 31250Hz H, for display on a VGA monitor, (with an ADC for input),
and similar stuff.
Of course using a real DAC (I have now) is much better.
Simple pulse things, like John does in that example to charge an integrator, work,
but analog is not the field for FPGAs, the 'right' way is to digitise,
process digitally, and then convert to analog again.
Like for filters, for example a nice lowpass in Verilog for video is only a
few lines of code, etc.
It seems Altera has a _lot_ of real nice video stuff, compete codecs, etc.
For sure I would go Altera if I needed something like that for video again.
Also Xilinx stuff is either not there, and cannot be bought from their online shop
(at least it was that way a while ago).

A long time ago I was looking into using the old Intel CPLD series that
way because of they microamp capabilities. Boy was I glad I didn't,
shortly after they ditched the whole line. Thing is, most of my designs
are targeted for more than a decade in production. And no trimpots or
calibration allowed unless that can be automated.

That is the nice thing about digital processing, no trimmers, no tolerances,
no monte carlos.
You may want an FPGA with onboard flash..
Just make sure you can actually get the chips from several sources, watch
the price too.
The Altera soft runs in MS windows and in Linux in Wine.
The Xilinx stuff has a Linux version that also works, and the tools have a command line
interface that can be used from a script,

Packages are small, you need a development (or more then one) board for each
FPGA.
And learning a HDL, Verilog or VHDL, or both, will take a lot of your time.
That needs to be calculated in too.

 

[john]

On Sun 29-Mar-2009 11:28, John Weston
<invalid@earlsway.invalid> wrote:

In article <Xns9BDD2DAEDA7DA451E7A@69.16.185.247>, "john"
wrote:

Thanks for the info. No worries! My ADSL adapters were just
spare in a drawer.

Better to get some new adaptors ...

(a) ...to connect an RJ11 plug to an BT-style wall socket.

I've had no problems using an old ADSL filter as a simple RJ11
to BT converter, since that part is straight through. I don't
think I've had to use one on a Virgin cable connection, if
that's what you have. I suppose the filter on the phone output
could develop a fault but I've not seen one. If necessary,
you can cut the wires to the filter inside the housing, since
a cheap ADSL filter will usually be cheaper than the straight
converter, see
http://www.maplin.co.uk/Module.aspx?ModuleNo=12494

(b) ...to connect an RTJ9/4P4C plug to the BT wall socket.

I've not met the RTJ9 A 4P4C, sometimes incorrectly
called an RJ9 is a phone handset/headset connector

Hello John W. For non-UK crossposted groups I should say I'm in the
UK. Anyway, as an aside ....

I didn't know if the convention was to refer to 4P4C or to the
modular plug used as a handset jack. The Wiki tells me that the RJ
references (RJ9, RJ10, RJ22) for a 4P4C are technically incorrect
but have gained widespread usage. I figured I wouldn't try to
fight convention even if it is incorrect!

and a handset shouldn't normally be connected directly to a BT
socket. I've got one on a call recorder adapter, that goes
between phone and headset but it is incompatible with direct
connection to a phone line.

What you describe is also my situation. At the moment I use a
Retell 156 in the curly lead and it's fine. Is that what you use?

I need another adapter for a different phone and decided to try
some different ones: one by Commtel adapter and another by Uket.

http://cpc.farnell.com/commtel/41529740/telephone-recording-
adaptor/dp/TE05106

http://www.uket.co.uk/digital-voice-
recorders/accessories/telephone-recording-adapters/prod_130.html

The Uket supplier says he can attach it either to the handset curly
(as it says on the web page) or to the line cord. The line cord is
a bit surprising but I won't really know until I have tried. A
friend of mine had an adapter which looked identical in appearance
to the Uket one and it actually did work well when plugged into a
wall socket with his own cord.

That's why I asked about variations in wiring line cords and curly
handset cords (below). I figured maybe some combination of a
telephone's non-standard wiring has permitted the adapter to work
in the line cord. In fact, I very vaguely(???) recall there is
poor standardisation for one or both of these:

(A) the pinout on the line cord's connector to the phone base.

(B) the pinout on either end of handset's curly lead.

These RJ plugs attach to a little device which permits
recording of phone conversation. I presume I wouldn't want to
use those adaptors advertised as a "crosswired". Is this
correct?

The two types of RJ11 are connects to the two inner connectors
(2&3) or to the two outer (1&4). The more ususal one, for the
first phone line, is the first. The line 1 converter connects
the RJ11 pins 2&3 to 2&5 on the BT plug. The line 2 converter
is 1&4 on the RJ11 to 2&5 on BT. The polarity doesn't
normally matter, so cross-wiring them shouldn't stop it
working.

I'm sure I once saw some good web pages about variations in
how particular telephone wires are allocated to connectors.
Maybe someone has a link to an article about the wiring of:

(1) telephone line cords
(2) handset curly cords.

Try here: http://telephonesuk.co.uk/wiring_info.htm (The
"Grey" should be "Slate" since G = Green)

Thanks for the link. It helped me find the following UK page which
mentions non-standard line cord setup at the end.

http://www.wppltd.demon.co.uk/WPP/Wiring/UK_telephone/uk_telephone.
html

As for the curly cord, a couple of articles in the Wiki don't agree
about this.

http://en.wikipedia.org/wiki/Telephone_plug says: "(the handset
cable) has a de facto standard of a 4P4C connector with straight
through cable".

http://en.wikipedia.org/wiki/4P4C says: "When used for connecting
handsets to the telephone base, the following pinout and wiring
diagram is used. [See original page.] Because the microphone and
speaker continue to function normally in the presence of reversed
polarity, the cable itself can be wired as a simple crossover cable
or as a straight through cable. Most telephone handset cords are
manufactured as crossover cables.

That second page references this:
www.gbpvr.com/pmwiki/pmwiki.php/Utility/DirecTVChannelControl
where it says: "Each end of a handset cord is wired opposite the
other".

Oh well. Perhaps a recording adapter doesn't care about this
because it will join together the pair of contacts for the earpiece
and the pair for the mic. I know this doesn't always work well
because Retell make their expensive model 650 for those flaky
occassions:

Retell 650 features
http://www.retellrecorders.co.uk/recording/machine/650.htm

Retell 650 video
http://www.retellrecorders.co.uk/support/productvideos/650video.htm

Retell 650 audio samples
http://www.retellrecorders.co.uk/help/connectors.htm

Luckily my phone with the cheaper Retell 156 gives equal volume
audio from both parties and this doesn't squelch either party.


Any comments from anyone on any of this are welcome.

 

[Joerg]

glen herrmannsfeldt wrote:

In comp.arch.fpga Joerg <notthisjoergsch@removethispacbell.net> wrote:

Oh, I do a lot of unorthodox stuff. Using 74HCU or CD4000 in analog
circuits, switcher FETs in servos, RF parts for digital functions and so
on. I am just curious what can be done with an FPGA in that respect.

I once knew someone who built an FM radio transmitter
using a 74S04 as the output stage. I suppose
cheaper than RF transistors at the time.

If this was 20 or more years ago, yes, RF power transistors that could
be used above 50MHz were painfully expensive. So I just used tubes.

--
Regards, Joerg

http://www.analogconsultants.com/

"gmail" domain blocked because of excessive spam.
Use another domain or send PM.

 

[Joerg]

Jan Panteltje wrote:

[...]

That is the nice thing about digital processing, no trimmers, no tolerances,
no monte carlos.

Don't need Monte Carlo, there's an Indian gambling place down the road
but I don't gamble anyhow.

Oh, wait ...

You may want an FPGA with onboard flash..

Flash? That's frowned upon as morally indecent in the more conservative
regions out here

Just make sure you can actually get the chips from several sources, watch
the price too. ...

That's the two main problems. FPGA are usually all single-sourced
(having several distributors doesn't count) and expensive. Seen too many
purchasing nightmares there.

[...]

--
Regards, Joerg

http://www.analogconsultants.com/

"gmail" domain blocked because of excessive spam.
Use another domain or send PM.

 

[krw]

On Sun, 29 Mar 2009 14:38:26 -0700, Joerg
<notthisjoergsch@removethispacbell.net> wrote:

Jan Panteltje wrote:

[...]

That is the nice thing about digital processing, no trimmers, no tolerances,
no monte carlos.


Don't need Monte Carlo, there's an Indian gambling place down the road
but I don't gamble anyhow.

Oh, wait ...


You may want an FPGA with onboard flash..


Flash? That's frowned upon as morally indecent in the more conservative
regions out here


Just make sure you can actually get the chips from several sources, watch
the price too. ...


That's the two main problems. FPGA are usually all single-sourced
(having several distributors doesn't count) and expensive. Seen too many
purchasing nightmares there.

Technically single-sourced, yes. As long as you stay away from the
quirks (LVDS performance can be considered a "quirk" , unique
features, and IP cores, they're pretty easy to substitute. The costs
have come *way* down, as well. $5-$20 buys a lot of logic these days.

 

[Joerg]

krw wrote:

On Sun, 29 Mar 2009 14:38:26 -0700, Joerg
notthisjoergsch@removethispacbell.net> wrote:

Jan Panteltje wrote:

[...]

That is the nice thing about digital processing, no trimmers, no tolerances,
no monte carlos.

Don't need Monte Carlo, there's an Indian gambling place down the road
but I don't gamble anyhow.

Oh, wait ...


You may want an FPGA with onboard flash..

Flash? That's frowned upon as morally indecent in the more conservative
regions out here


Just make sure you can actually get the chips from several sources, watch
the price too. ...

That's the two main problems. FPGA are usually all single-sourced
(having several distributors doesn't count) and expensive. Seen too many
purchasing nightmares there.

Technically single-sourced, yes. As long as you stay away from the
quirks (LVDS performance can be considered a "quirk" , unique
features, and IP cores, they're pretty easy to substitute. The costs
have come *way* down, as well. $5-$20 buys a lot of logic these days.

That's true, but a lot of times my whole design including board and
assembly can't cost nearly as much as that (in large quantities).

--
Regards, Joerg

http://www.analogconsultants.com/

"gmail" domain blocked because of excessive spam.
Use another domain or send PM.

 

[krw]

On Sun, 29 Mar 2009 17:02:47 -0700, Joerg
<notthisjoergsch@removethispacbell.net> wrote:

krw wrote:
On Sun, 29 Mar 2009 14:38:26 -0700, Joerg
notthisjoergsch@removethispacbell.net> wrote:

Jan Panteltje wrote:

[...]

That is the nice thing about digital processing, no trimmers, no tolerances,
no monte carlos.

Don't need Monte Carlo, there's an Indian gambling place down the road
but I don't gamble anyhow.

Oh, wait ...


You may want an FPGA with onboard flash..

Flash? That's frowned upon as morally indecent in the more conservative
regions out here


Just make sure you can actually get the chips from several sources, watch
the price too. ...

That's the two main problems. FPGA are usually all single-sourced
(having several distributors doesn't count) and expensive. Seen too many
purchasing nightmares there.

Technically single-sourced, yes. As long as you stay away from the
quirks (LVDS performance can be considered a "quirk" , unique
features, and IP cores, they're pretty easy to substitute. The costs
have come *way* down, as well. $5-$20 buys a lot of logic these days.


That's true, but a lot of times my whole design including board and
assembly can't cost nearly as much as that (in large quantities).

No, FPGAs aren't the right answer for every question but you're not
going to buy that function, or anything near it, for less. We have a
pile of crap logic that I'd *love* to sweep into a FPGA. It would
save a lot of money and grief. If I was convinced I could do a decent
delta sigma modulator I'd do even more.

 

[John Larkin]

On Sun, 29 Mar 2009 21:00:48 -0500, krw <krw@att.bizzzzzzzzzzz> wrote:

On Sun, 29 Mar 2009 17:02:47 -0700, Joerg
notthisjoergsch@removethispacbell.net> wrote:

krw wrote:
On Sun, 29 Mar 2009 14:38:26 -0700, Joerg
notthisjoergsch@removethispacbell.net> wrote:

Jan Panteltje wrote:

[...]

That is the nice thing about digital processing, no trimmers, no tolerances,
no monte carlos.

Don't need Monte Carlo, there's an Indian gambling place down the road
but I don't gamble anyhow.

Oh, wait ...


You may want an FPGA with onboard flash..

Flash? That's frowned upon as morally indecent in the more conservative
regions out here


Just make sure you can actually get the chips from several sources, watch
the price too. ...

That's the two main problems. FPGA are usually all single-sourced
(having several distributors doesn't count) and expensive. Seen too many
purchasing nightmares there.

Technically single-sourced, yes. As long as you stay away from the
quirks (LVDS performance can be considered a "quirk" , unique
features, and IP cores, they're pretty easy to substitute. The costs
have come *way* down, as well. $5-$20 buys a lot of logic these days.


That's true, but a lot of times my whole design including board and
assembly can't cost nearly as much as that (in large quantities).

No, FPGAs aren't the right answer for every question but you're not
going to buy that function, or anything near it, for less. We have a
pile of crap logic that I'd *love* to sweep into a FPGA. It would
save a lot of money and grief. If I was convinced I could do a decent
delta sigma modulator I'd do even more.

D-S dacs work just fine in FPGAs. They're especially handy for slow
trims, like dc offset, vcxo freq, stuff like that. One FPGA pin and
one external RC makes a pretty good dac.

John