K
Ken Smith
Guest
In article <AF57c.11433$rw6.217810@news.xtra.co.nz>,
Terry Given <the_domes@xtra.co.nz> wrote:
layout practice is to not put a via hole in a component pad but to instead
run a trace to the via. By time you include the length of the two traces
involved and plus the size of the body of the part, the total length is
longer than the 0.1" cap would have.
out of the calculation.
ones with the 0.1" spaced leads.
pad. This limit is imposed by the need to not wick all the heat away from
one part of the pad too quickly.
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Terry Given <the_domes@xtra.co.nz> wrote:
Its the trace that leads to the via, not the via its self. Standard"Ken Smith" <kensmith@violet.rahul.net> wrote in message
At 10.16, the document implies that surface mount decoupling capacitors
are better than through hole parts. In practice correctly installed
through hole capacitors with a 0.1" lead spacing can be better than
surface mount. The lead provides a very low impedance path from the
actual capacitance directly to the power and ground planes.
I presume this is due to the via somehow? many leaded caps are actually smt
caps with leads attached to the metallised end caps. please elaborate
layout practice is to not put a via hole in a component pad but to instead
run a trace to the via. By time you include the length of the two traces
involved and plus the size of the body of the part, the total length is
longer than the 0.1" cap would have.
I disagree with the 1.5mm number here. You left the length of the tracesthe biggest problem to overcome with leaded caps is their physical sixe.
trace the physical current loop....with an 0603 smt capacitor sitting 0.4mm
above the 0V plane (4-layer PCB) the physical loop can be no smaller than
(about) 1.5mm x 0.4mm.
out of the calculation.
Yes, don't use those they don't work well for bypassing. You want the= 2.5mm, the area WILL be bigger than that of an smt cap. Often leaded caps
have 0.1" leads bent out to 0.2" spacing,
ones with the 0.1" spaced leads.
If you are working with SMT you are limited as to trace size running to ait is clear from the above discussion that traces etc. only make the problem
worse. keep them wide, and use multiple parallel vias.
pad. This limit is imposed by the need to not wick all the heat away from
one part of the pad too quickly.
I can run faster than him. Not that I've had to yet.under its body. Some of the bypass capacitors should be on the back of
the PCB to make the impedance between the Vcc and DGND low.
if your production manager doesnt hit you with a stick.
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kensmith@rahul.net forging knowledge