Delaying signal assignment

[hssig]

How can I delay a signal in the following manner ?


signal clk : std_logic;
signal sig : std_logic;

process
begin
clk <= '1'; wait for 10 ns;
clk <= '0'; wait for 10 ns;
end process;

Now I want "sig" to be High for 50us, after that it should be assigned
the value of clk.

The following approach does not work:
sig <= '1', clk after 50 us;

Cheers, hssig

 

[Andy]

On Nov 19, 4:38 am, hssig <hs...@gmx.net> wrote:

How can I delay a signal in the following manner ?

signal clk : std_logic;
signal sig : std_logic;

process
begin
   clk <= '1'; wait for 10 ns;
   clk <= '0'; wait for 10 ns;
end process;

Now I want "sig" to be High for 50us, after that it should be assigned
the value of clk.

The following approach does not work:
sig <= '1', clk after 50 us;

Cheers, hssig

signal enable : boolean := false;
signal clk : std_logic := '0';
signal sig : std_logic := '1';

enable <= true after 50 us;

clk <= not clk after 10 ns;

sig <= clk when enable, else '1';

Andy

 

[rickman]

On Nov 19, 5:38 am, hssig <hs...@gmx.net> wrote:

How can I delay a signal in the following manner ?

signal clk : std_logic;
signal sig : std_logic;

process
begin
   clk <= '1'; wait for 10 ns;
   clk <= '0'; wait for 10 ns;
end process;

Now I want "sig" to be High for 50us, after that it should be assigned
the value of clk.

The following approach does not work:
sig <= '1', clk after 50 us;

Cheers, hssig

50us <= '1', '0' after 50 us;
sig <= clk or 50us;

Isn't that easy? Don't make things too hard by thinking about them
too much...

Rick

 

[Dave]

On 19 Nov, 10:38, hssig <hs...@gmx.net> wrote:

The following approach does not work:
sig <= '1', clk after 50 us;

Try:-

sig <= transport '1', clk after 50 us;

(this instructs the simulator to model sig as a transmission line)

 

[hssig]

Don't make things too hard by thinking about them
too much...

True point. Thank you for your suggestions.

Cheers, hssig