Delay without affecting pulse width

The clock doesn't need to be synchronized with anything. Free running
would be fine. The 'downside' is a 2 uSec window with a 500 KHz clock.
Use a bigger FIFO and faster clock for a smaller window. I got the
impression from earlier posts that the exact timing wasn't critical.
Think of it more like a crude 1 bit recorder/player.
GG

 

[Jamie]

Kitchen Man wrote:

On 10 Mar 2005 21:32:34 -0800 in sci.electronics.basics,
stratus46@yahoo.com wrote msg
1110519153.984390.183960@g14g2000cwa.googlegroups.com>:


Not what I had in mind, no. The OP wants a delay on both the leading
and trailing edge, I.E. maintain the original pulse width, just delay
it. Think of this as a 1 bit digitizer and the shift register is the
memory. If your clock is good, no temperature variations, very
predictable and pretty simple. Take the output from different bit
counts and/or vary the clock rate for different/multiple delays.


I guess I didn't explain myself clearly. I don't think there is a
system clock, so to use this approach, a system clock has to be
developed and synchronized to the release pulse.

i think what your looking for is a continous running clock that

inputs it's pulses to an AND gate. when the other input is on, the
pulse will appear on the output of the AND gate in sync because there
is no initial starting of an OSC/timer
etc.

is that what your looking for ?

 

[BR]

John Fields <jfields@austininstruments.com> wrote in
news:b0j931d9ehq67l4rtkb7uf21ubaijbn11l@4ax.com:

The easiest way, I think, would be to use something like an
HC123 or a 4538. Use the first section to generate the delay and
to trigger the second section after that delay. The output of
the second section will be the pulse you want and, if you use
this approach, will also be adjustable.

See "Delay without affecting pulse width" on
alt.binaries.schematics.electronic for a schematic and circuit
description.

I have some 4528 Thanks for the schematic.

Ben

--

 

Nope, even simpler than that. No gate required because no
synchronization is required. But you're right that the clock would need
to run continuously. The pulse to be delayed is applied to the input of
the shift register. I assume the logic families are compatible I.E.
you're not trying to connect ECL into TTL without the proper interface.
The delayed pulse(s) extracted some number of shift cycles later from
one or more 'taps'. This is nothing more than a digital equivalent of
the old analog CCD audio chips from the '70s.
GG

 

[BR]

"Chris" <cfoley1064@yahoo.com> wrote in
news:1110301780.420696.166330@z14g2000cwz.googlegroups.com:

BR wrote:
"Andrew Holme" <ajholme@hotmail.com> wrote in
news:1110282525.174548.111790@f14g2000cwb.googlegroups.com:


BR wrote:
John Fields <jfields@austininstruments.com> wrote in
news:kbdp211k5pm4367ap70l7jjcaah5ivinjk@4ax.com:

On Mon, 07 Mar 2005 12:15:30 -0600, BR
slackin@nonsense.comcast.net> wrote:

Hello,

Is there a circuit that can delay a pulse train without
affecting its width? The pulse width is about 1.5ms to
2ms, every 20ms (RC servo signals). The delay needed is
less than that, perhaps up to 1 ms. It would be convenient
if it were variable.

---
Can you provide a timing diagram to show what you mean or
verbally explain what you mean by "delay"?


The best I can do is give a description of the apparatus. It
involves three RC servos mounted on a rotating ring used to
form a gripper system. Each gripper pad is located
equidistant about the outside rim of a small 5" dia.
hemispherical bowl containing water. The opening of the 5"
bowl must be in full view. The 5" bowl is floating in a
larger bowl filled with water. All three servos are
connected to one signal output of an EZ servo 1 chip (a pre-
programed controller). A problem occurs when the bowl is
released. The gripper releases the bowl as fast as it can
when the signal pulse width changes abruptly from 1725ľs to
1650ľs. However, the differences between servos always
causes the bowl to drift slowly away from the lagging
servo. This is determined by releasing the bowl while the
ring is stationary. Adjusting the servo mounting hw only
reduces the problem. So, I'm looking for a way to fine tune
the release and minimize linear motion of the bowl. If this
can't be done with delay lines I would appreciate any
suggestions.

Here's one way you might do it:

Trigger a monostable on both edges of the input pulse. Clock
the input into a D-type flip-flop on mono timeout.
Exclusive-OR the flip-flop output with the input to make a
trigger pulse for the mono. The flip-flop output is also
your delayed pulse.

It sounds like you're trying to compensate for small
differences in servo response time. It might require
constant fiddling and tweaking to counteract ageing or
changes in temperature.


Thanks for the suggestion. I'll try it with some old CMOS 4000.
I assume some variable adjustment is possible with the timing
resistor on the mono, but the max delay is less than the pulse
width, is that correct?

Ben

--

Hi, BR. You might want to try using a 74C14, a resistor and a
cap, like this (view in fixed font or M$ Notepad):


` 2/6 74C14
` Servo In 200K
` ___ ___ |\ |\ Servo Out
` o---|___|--o-|___|--o--|H>O--|H>O-----o
` 20K | A | |/ |/
` | | | about 1ms delay
` | | ---
` '---' ---
` .01uF|
` |
` ==` GND
created by Andy´s ASCII-Circuit v1.24.140803 Beta
www.tech-chat.de

The built-in hysteresis of the C14, along with the R and C, act
as a digital delay line. Your 0 to 1 logic transitions will be
delayed almost exactly as much as the 1-to-0 transistions.

This is because the hysteresis of the 74C14 (and the 74HC14) is
centered on 1/2 Vcc. This doesn't work for the 7414, 74LS14,
and other TTL versions of this chip for several reasons.

Once you know the right value for your application, just
substitute a fixed resistor for the pot, and you're good to go.

Good luck
Chris

I'll add some 74C14 to my Mouser order. Thanks.

Ben

--

 

[John Fields]

On Mon, 07 Mar 2005 19:44:21 -0600, BR <slackin@nonsense.comcast.net>
wrote:

John Fields <jfields@austininstruments.com> wrote in
news:kbdp211k5pm4367ap70l7jjcaah5ivinjk@4ax.com:

On Mon, 07 Mar 2005 12:15:30 -0600, BR
slackin@nonsense.comcast.net> wrote:

Hello,

Is there a circuit that can delay a pulse train without
affecting its width? The pulse width is about 1.5ms to 2ms,
every 20ms (RC servo signals). The delay needed is less than
that, perhaps up to 1 ms. It would be convenient if it were
variable.

---
Can you provide a timing diagram to show what you mean or
verbally explain what you mean by "delay"?


The best I can do is give a description of the apparatus. It
involves three RC servos mounted on a rotating ring used to form a
gripper system. Each gripper pad is located equidistant about the
outside rim of a small 5" dia. hemispherical bowl containing water.
The opening of the 5" bowl must be in full view. The 5" bowl is
floating in a larger bowl filled with water. All three servos are
connected to one signal output of an EZ servo 1 chip (a pre-
programed controller). A problem occurs when the bowl is released.
The gripper releases the bowl as fast as it can when the signal
pulse width changes abruptly from 1725ľs to 1650ľs. However, the
differences between servos always causes the bowl to drift slowly
away from the lagging servo. This is determined by releasing the
bowl while the ring is stationary. Adjusting the servo mounting hw
only reduces the problem. So, I'm looking for a way to fine tune
the release and minimize linear motion of the bowl. If this can't
be done with delay lines I would appreciate any suggestions.

---
The easiest way, I think, would be to use something like an HC123 or a
4538. Use the first section to generate the delay and to trigger the
second section after that delay. The output of the second section
will be the pulse you want and, if you use this approach, will also be
adjustable.

See "Delay without affecting pulse width" on
alt.binaries.schematics.electronic for a schematic and circuit
description.

--
John Fields

 

[John Fields]

On Tue, 08 Mar 2005 09:13:35 +0000, Terry Pinnell
<terrypinDELETE@THESEdial.pipex.com> wrote:

John Fields <jfields@austininstruments.com> wrote:

On Mon, 07 Mar 2005 12:15:30 -0600, BR <slackin@nonsense.comcast.net
wrote:

Hello,

Is there a circuit that can delay a pulse train without affecting its
width? The pulse width is about 1.5ms to 2ms, every 20ms (RC servo
signals). The delay needed is less than that, perhaps up to 1 ms. It
would be convenient if it were variable.

---
Can you provide a timing diagram to show what you mean or verbally
explain what you mean by "delay"?

I assumed he meant this:
http://www.terrypin.dial.pipex.com/Images/PulseTrainDelay.gif

---
Yes, I think you're right; thanks. I posted a solution to abse a
little while ago under the same subject as this thread, albeit with an
error... U1-8 is ground, not U1A-Q. :-(


--
John Fields