DDS questions...

[John Larkin]

To make a programmable-frequency clock, the usual DDS chip has

A frequency-set register, N=32 or 48 bits or something

which adds, every clock, to a phase accumulator

M most-significant bits of that goes into a sine lookup table

Which clocks D bits into a DAC

Which drives a lowpass filter and a comparator.

(Ignoring DAC quantization and zero-order hold, this is the tail end
of the Shannon sampling theorem.)

Why do the sine lookup? The ms D bits of the accumulator are a
triangle waveform. Why not DAC and filter that? The lowpass filter
wouldn\'t know... it would interpolate as usual.

Why not use some clever VHDL and make a trapezoid with faster rise
time, especially at low frequencies where time quantization and
comparator errors make a lot of period jitter and the filter doesn\'t
interpolate.

If one just takes the MSB of the phase accumulator, you have a
programmable-frequency clock without all that other junk. But its
period is quantized to the clock, which gets totally ugly at high
frequencies. I wonder if some clever math could make that output
always some perfect multiple of, say 1 Hz or 1 mHz.

Somebody left a bag of second-rate coffee in the freezer at the cabin,
otherwise I\'d figure all this out myself.


--

John Larkin Highland Technology, Inc trk

The cork popped merrily, and Lord Peter rose to his feet.
\"Bunter\", he said, \"I give you a toast. The triumph of Instinct over Reason\"

 

[Anthony William Sloman]

On Sunday, August 7, 2022 at 11:55:32 PM UTC+10, John Larkin wrote:

To make a programmable-frequency clock, the usual DDS chip has

A frequency-set register, N=32 or 48 bits or something

which adds, every clock, to a phase accumulator

M most-significant bits of that goes into a sine lookup table

Which clocks D bits into a DAC

Which drives a lowpass filter and a comparator.

(Ignoring DAC quantization and zero-order hold, this is the tail end
of the Shannon sampling theorem.)

Why do the sine lookup? The ms D bits of the accumulator are a
triangle waveform. Why not DAC and filter that? The lowpass filter
wouldn\'t know... it would interpolate as usual.

The triangle waveform has all the odd harmonics of the fundamental, reduced in proportion to the square of the harmonic number - a triangular wave is just the integral of a square wave. This is a lot more low-harmonic number frequency content than you get out of a sine look-up.

The low-pass filter \"wouldn\'t know\" but anybody with any sense looking at it\'s output would.

Why not use some clever VHDL and make a trapezoid with faster rise
time, especially at low frequencies where time quantization and
comparator errors make a lot of period jitter and the filter doesn\'t
interpolate.

Because the low order harmonic content is higher.

If one just takes the MSB of the phase accumulator, you have a
programmable-frequency clock without all that other junk. But its
period is quantized to the clock, which gets totally ugly at high
frequencies. I wonder if some clever math could make that output
always some perfect multiple of, say 1 Hz or 1 mHz.

Wonder away, but wander away while you are doing it. Doing it here doesn\'t do anything for the perceived quality of this forum..

> Somebody left a bag of second-rate coffee in the freezer at the cabin, otherwise I\'d figure all this out myself.

You may be flattering yourself.

--
Bill Sloman, Sydney

 

[whit3rd]

On Sunday, August 7, 2022 at 6:55:32 AM UTC-7, John Larkin wrote:

To make a programmable-frequency clock, the usual DDS chip has

A frequency-set register, N=32 or 48 bits or something

which adds, every clock, to a phase accumulator

M most-significant bits of that goes into a sine lookup table

Which clocks D bits into a DAC

Which drives a lowpass filter and a comparator.

(Ignoring DAC quantization and zero-order hold, this is the tail end
of the Shannon sampling theorem.)

Why do the sine lookup? The ms D bits of the accumulator are a
triangle waveform. Why not DAC and filter that? The lowpass filter
wouldn\'t know... it would interpolate as usual.

The sine lookup minimizes the difference function, which is the target of
the (analog) lowpass filter. That makes it a kind of digital filter doing the
bulk of the work. Starting with a square wave, integrating to a triangle wave,
double-integrating to a parabola wave... is another approach that kinda
works, but it\'s low-pass filtering of a sort, that just isn\'t as elegant. That\'s
how a phase-shift oscillator works, basically (those aren\'t known for
precision).

Other than synchronization possibilities, the triangle-wave basis hasn\'t an
advantage to speak of.

Why not use some clever VHDL and make a trapezoid with faster rise
time,...

Any polygon would have roughly the same harmonics as a triangle, to filter out.

Another approach, from yesteryear, would be to microstep a motor that
runs a flywheel and generator; you can get sine and cosine out, and
it\'s hard to beat a flywheel for parts cost of high quality filter components.
If you ever see a sine source that precesses when tilted, that\'s why.

 

[Ricky]

On Sunday, August 7, 2022 at 9:55:32 AM UTC-4, John Larkin wrote:

To make a programmable-frequency clock, the usual DDS chip has

A frequency-set register, N=32 or 48 bits or something

which adds, every clock, to a phase accumulator

M most-significant bits of that goes into a sine lookup table

Which clocks D bits into a DAC

Which drives a lowpass filter and a comparator.

(Ignoring DAC quantization and zero-order hold, this is the tail end
of the Shannon sampling theorem.)

Why do the sine lookup? The ms D bits of the accumulator are a
triangle waveform. Why not DAC and filter that? The lowpass filter
wouldn\'t know... it would interpolate as usual.

The lowpass filter it typically, not sentient. But filters provide some amount of attenuation. It seems silly to require a filter with more attenuation because you supply a signal with higher noise content to be filtered. If your spurious signal requirements are so low that you can use a filter driven by a triangle wave, you probably could use a simple sine generator, with no filter at all!

Why not use some clever VHDL and make a trapezoid with faster rise
time, especially at low frequencies where time quantization and
comparator errors make a lot of period jitter and the filter doesn\'t
interpolate.

\"Clever VHDL\" is an odd way to term it. HDLs simply express a logic design.. I assume you mean a clever logic design. That is easily done, but a DDS is already a very efficient means of generating a sine function. The table size can be minimized by using approximation methods such as sin (a + b) = sin a cos b + cos a sin b where a is msbs and b is lsbs, so that cos(b) is always close to 1 and cos(a) sin(b) can be a second, smaller table or found with a multiplication. Since cos(a) sin(b) is a small value, it does not require as much resolution as sin(a) and the inputs are just the msbs of a and b.

The CORDIC algorithm is another algorithm to produce a stepped sine function with high resolution.

In other words, it is not hard to get more resolution than the DAC can ever hope to spit out.

If one just takes the MSB of the phase accumulator, you have a
programmable-frequency clock without all that other junk. But its
period is quantized to the clock, which gets totally ugly at high
frequencies. I wonder if some clever math could make that output
always some perfect multiple of, say 1 Hz or 1 mHz.

Yes, you can make your output a perfect multiple of arbitrary time values, by changing the modulus of the phase accumulator. I once constructed a phase accumulator with three sections with different moduli. The middle section had a modulus that gave a setting of 1 Hz resolution. The upper two bits were binary to for use as the sign and slope msb to allow folding of the waveform and so reduction of the sine table size (a very common technique). The lsbs were binary to provide fractions of Hz resolution. The table was sized to fit the middle counter bits which means it did not fit in a binary sized memory. However, there are other ways of calculating a sine.

You can also construct a sine using the CORDIC algorithm, or various other approximations.

It is important to preserve as much phase resolution as you can. The impact of resolution in the output of the sine generator produces errors that mostly appear as harmonics which can be filtered without too much difficulty. Truncation errors in the phase word, produce spurious frequencies which include values close to the fundamental of interest. These are hard to filter.

Somebody left a bag of second-rate coffee in the freezer at the cabin,
otherwise I\'d figure all this out myself.

Incomplete thought. Does \"second-rate coffee\" in the freezer mean you are drinking too much coffee, or that you refuse to drink any and are suffering from withdrawal?

As much as I love coffee, I had to give it up because caffeine gives me an irregular heartbeat. Not good for the soul.

--

Rick C.

- Get 1,000 miles of free Supercharging
- Tesla referral code - https://ts.la/richard11209

 

[John Larkin]

On Sun, 7 Aug 2022 08:23:49 -0700 (PDT), whit3rd <whit3rd@gmail.com>
wrote:

On Sunday, August 7, 2022 at 6:55:32 AM UTC-7, John Larkin wrote:
To make a programmable-frequency clock, the usual DDS chip has

A frequency-set register, N=32 or 48 bits or something

which adds, every clock, to a phase accumulator

M most-significant bits of that goes into a sine lookup table

Which clocks D bits into a DAC

Which drives a lowpass filter and a comparator.

(Ignoring DAC quantization and zero-order hold, this is the tail end
of the Shannon sampling theorem.)

Why do the sine lookup? The ms D bits of the accumulator are a
triangle waveform. Why not DAC and filter that? The lowpass filter
wouldn\'t know... it would interpolate as usual.

The sine lookup minimizes the difference function, which is the target of
the (analog) lowpass filter. That makes it a kind of digital filter doing the
bulk of the work. Starting with a square wave, integrating to a triangle wave,
double-integrating to a parabola wave... is another approach that kinda
works, but it\'s low-pass filtering of a sort, that just isn\'t as elegant. That\'s
how a phase-shift oscillator works, basically (those aren\'t known for
precision).

The positive zero crossing of a sine wave and a triangle look a lot
alike, a straight line within the attention span of the lowpass
filter. It can\'t remember enough long-ago to tell the difference.

We don\'t push the Nyquist rate, which needs an ideal lowpass filter.
In fact, the sawtooth looks better to me... there is more linear
history before the zero cross than a sine.

Other than synchronization possibilities, the triangle-wave basis hasn\'t an
advantage to speak of.

No sine lookup table and no error contributions from that.

Why not use some clever VHDL and make a trapezoid with faster rise
time,...

Any polygon would have roughly the same harmonics as a triangle, to filter out.

It\'s a clock. We don\'t want to filter out harmonics. Who designs
digital clocks with low harmonic content?

Another approach, from yesteryear, would be to microstep a motor that
runs a flywheel and generator; you can get sine and cosine out, and
it\'s hard to beat a flywheel for parts cost of high quality filter components.
If you ever see a sine source that precesses when tilted, that\'s why.

There is a clever synchro digitizer that simulates a rotating mass
internally. It tracks a constant-velocity rotation with zero error.

--

John Larkin Highland Technology, Inc trk

The cork popped merrily, and Lord Peter rose to his feet.
\"Bunter\", he said, \"I give you a toast. The triumph of Instinct over Reason\"

 

[Joe Gwinn]

On Sun, 07 Aug 2022 09:08:02 -0700, John Larkin
<jjlarkin@highlandtechnology.com> wrote:

On Sun, 7 Aug 2022 08:23:49 -0700 (PDT), whit3rd <whit3rd@gmail.com
wrote:

On Sunday, August 7, 2022 at 6:55:32 AM UTC-7, John Larkin wrote:
To make a programmable-frequency clock, the usual DDS chip has

A frequency-set register, N=32 or 48 bits or something

which adds, every clock, to a phase accumulator

M most-significant bits of that goes into a sine lookup table

Which clocks D bits into a DAC

Which drives a lowpass filter and a comparator.

(Ignoring DAC quantization and zero-order hold, this is the tail end
of the Shannon sampling theorem.)

Why do the sine lookup? The ms D bits of the accumulator are a
triangle waveform. Why not DAC and filter that? The lowpass filter
wouldn\'t know... it would interpolate as usual.

The sine lookup minimizes the difference function, which is the target of
the (analog) lowpass filter. That makes it a kind of digital filter doing the
bulk of the work. Starting with a square wave, integrating to a triangle wave,
double-integrating to a parabola wave... is another approach that kinda
works, but it\'s low-pass filtering of a sort, that just isn\'t as elegant. That\'s
how a phase-shift oscillator works, basically (those aren\'t known for
precision).

The positive zero crossing of a sine wave and a triangle look a lot
alike, a straight line within the attention span of the lowpass
filter. It can\'t remember enough long-ago to tell the difference.

We don\'t push the Nyquist rate, which needs an ideal lowpass filter.
In fact, the sawtooth looks better to me... there is more linear
history before the zero cross than a sine.


Other than synchronization possibilities, the triangle-wave basis hasn\'t an
advantage to speak of.

No sine lookup table and no error contributions from that.


Why not use some clever VHDL and make a trapezoid with faster rise
time,...

Any polygon would have roughly the same harmonics as a triangle, to filter out.

It\'s a clock. We don\'t want to filter out harmonics. Who designs
digital clocks with low harmonic content?

Not applicable in your application, but in the time world, reference
clocks are always sent as low-distortion sine waves, because the
harmonics don\'t travel in real cable all at the same speed, or all
have the same temperature coefficient of electrical length (group
velocity).

This is the answer to the usual querulous question: Given that the
first thing done to an arriving reference is to square it up, why
bother with a sine wave at all?


Joe Gwinn

 

[Gerhard Hoffmann]

Am 07.08.22 um 15:55 schrieb John Larkin:

Why do the sine lookup? The ms D bits of the accumulator are a
triangle waveform. Why not DAC and filter that? The lowpass filter
wouldn\'t know... it would interpolate as usual.

Why not use some clever VHDL and make a trapezoid with faster rise
time, especially at low frequencies where time quantization and
comparator errors make a lot of period jitter and the filter doesn\'t
interpolate.

If one just takes the MSB of the phase accumulator, you have a
programmable-frequency clock without all that other junk. But its
period is quantized to the clock, which gets totally ugly at high
frequencies. I wonder if some clever math could make that output
always some perfect multiple of, say 1 Hz or 1 mHz.

There was a DDS from Stanford Telecom (Standard? T.) that was
BCD and that thusly could produce exact mHz from 10 MHz etc.

Just using the MSB would inherit awful phase modulation / noise.

I have published a sine table on opencores.org with a
DDS as test bed. It stores only one quarter of the circle and
mirrors the rest. Table size is generic and taken automagically
from the connected busses. 0 up to 10 pipeline registers may be
selected and are strategically inserted as food for the register
balancer.

Without any work it ran at 230 MHz on a Spartan6 eval board,
just by asking for 250 MHz. I needed only 200 MHz.
Sine and cosine are available at no extra table cost to feed
the multipliers of a complex mixer.

It is pure VHDL that does not lock you into a silicon vendor.

< https://opencores.org/projects/sincos >

Cordic was ruled out for me because of its delays.
It is hard to get a digital Costas loop stable when
it takes a year for the oscillator to follow and it\'s
staggering around in the mean time after a frequency change.

Cheers, Gerhard

 

[Ricky]

On Sunday, August 7, 2022 at 12:08:13 PM UTC-4, John Larkin wrote:

On Sun, 7 Aug 2022 08:23:49 -0700 (PDT), whit3rd <whi...@gmail.com
wrote:
On Sunday, August 7, 2022 at 6:55:32 AM UTC-7, John Larkin wrote:
To make a programmable-frequency clock, the usual DDS chip has

A frequency-set register, N=32 or 48 bits or something

which adds, every clock, to a phase accumulator

M most-significant bits of that goes into a sine lookup table

Which clocks D bits into a DAC

Which drives a lowpass filter and a comparator.

(Ignoring DAC quantization and zero-order hold, this is the tail end
of the Shannon sampling theorem.)

Why do the sine lookup? The ms D bits of the accumulator are a
triangle waveform. Why not DAC and filter that? The lowpass filter
wouldn\'t know... it would interpolate as usual.

The sine lookup minimizes the difference function, which is the target of
the (analog) lowpass filter. That makes it a kind of digital filter doing the
bulk of the work. Starting with a square wave, integrating to a triangle wave,
double-integrating to a parabola wave... is another approach that kinda
works, but it\'s low-pass filtering of a sort, that just isn\'t as elegant.. That\'s
how a phase-shift oscillator works, basically (those aren\'t known for
precision).
The positive zero crossing of a sine wave and a triangle look a lot
alike, a straight line within the attention span of the lowpass
filter. It can\'t remember enough long-ago to tell the difference.

We don\'t push the Nyquist rate, which needs an ideal lowpass filter.
In fact, the sawtooth looks better to me... there is more linear
history before the zero cross than a sine.

Other than synchronization possibilities, the triangle-wave basis hasn\'t an
advantage to speak of.
No sine lookup table and no error contributions from that.

Why not use some clever VHDL and make a trapezoid with faster rise
time,...

Any polygon would have roughly the same harmonics as a triangle, to filter out.
It\'s a clock. We don\'t want to filter out harmonics. Who designs
digital clocks with low harmonic content?

If you wish to generate a minimum jitter signal, then the sine wave is what you want because is can be filtered most easily. You may think your triangle waveform has the best properties for this, but you aren\'t being realistic about the properties. I expect you are picturing a single wave in your mind and not picturing the eye diagram. At some point in the process the triangle or trapezoid has to be applied to a threshold to become a clock. The steeper the waveform is, the more pronounced will be the jitter from the quantization errors. Filtering will only attenuate this, not eliminate. The sine wave is the waveform with the least spurious content, and so the most easily filtered. What is most important, are the close in spurs which are difficult to attenuate. Pay attention to those and the rest is just mental masturbation.

--

Rick C.

+ Get 1,000 miles of free Supercharging
+ Tesla referral code - https://ts.la/richard11209

 

[whit3rd]

On Sunday, August 7, 2022 at 9:08:13 AM UTC-7, John Larkin wrote:

On Sun, 7 Aug 2022 08:23:49 -0700 (PDT), whit3rd <whi...@gmail.com
wrote:
On Sunday, August 7, 2022 at 6:55:32 AM UTC-7, John Larkin wrote:
To make a programmable-frequency clock, the usual DDS chip has
....
M most-significant bits of that goes into a sine lookup table

The sine lookup minimizes the difference function, which is the target of
the (analog) lowpass filter. That makes it a kind of digital filter doing the
bulk of the work.

The positive zero crossing of a sine wave and a triangle look a lot
alike, a straight line within the attention span of the lowpass
filter. It can\'t remember enough long-ago to tell the difference.

But one wouldn\'t use the zero crossing (adds voltage offset error
to the timing signal) when a trangle wave has a nice crisp
cusp to define a timing.

We don\'t push the Nyquist rate, which needs an ideal lowpass filter.
In fact, the sawtooth looks better to me... there is more linear
history before the zero cross than a sine.

Other than synchronization possibilities, the triangle-wave basis hasn\'t an
advantage to speak of.

No sine lookup table and no error contributions from that.

But, the triangle wave, for a given amplitude, has lower slew rate (lower
V signal at delta-T from the zero) than a sine wave. So, lower signal/noise.

It\'s a clock. We don\'t want to filter out harmonics. Who designs
digital clocks with low harmonic content?

A \'digital clock\' would usually be square-wave, neither triangle or sine.
The \'trapezoidal wave\' suggestion is just a slew-limited square wave.
Reasons to use a sine for clocking would be analog
phase comparison in a PLL, or bandwidth limiting (as in,
a WWVB transmission).

 

[John Larkin]

On Sun, 7 Aug 2022 10:11:44 -0700 (PDT), whit3rd <whit3rd@gmail.com>
wrote:

On Sunday, August 7, 2022 at 9:08:13 AM UTC-7, John Larkin wrote:
On Sun, 7 Aug 2022 08:23:49 -0700 (PDT), whit3rd <whi...@gmail.com
wrote:
On Sunday, August 7, 2022 at 6:55:32 AM UTC-7, John Larkin wrote:
To make a programmable-frequency clock, the usual DDS chip has
...
M most-significant bits of that goes into a sine lookup table

The sine lookup minimizes the difference function, which is the target of
the (analog) lowpass filter. That makes it a kind of digital filter doing the
bulk of the work.

The positive zero crossing of a sine wave and a triangle look a lot
alike, a straight line within the attention span of the lowpass
filter. It can\'t remember enough long-ago to tell the difference.

But one wouldn\'t use the zero crossing (adds voltage offset error
to the timing signal) when a trangle wave has a nice crisp
cusp to define a timing.

The point of the DDS lowpass filter is to interpolate multiple samples
and reduce jitter. If we use sharp edges on the waveform, the filter
just delays but doesn\'t reduce jitter. May as well use the phase
accumulator MSB.

A sawtooth has a nice long straight line rising edge. The filter will
love that.

We don\'t push the Nyquist rate, which needs an ideal lowpass filter.
In fact, the sawtooth looks better to me... there is more linear
history before the zero cross than a sine.

Other than synchronization possibilities, the triangle-wave basis hasn\'t an
advantage to speak of.

No sine lookup table and no error contributions from that.

But, the triangle wave, for a given amplitude, has lower slew rate (lower
V signal at delta-T from the zero) than a sine wave. So, lower signal/noise.

If D MSBs of the phase accumulator are pushed into the DAC, we get a
sawtooth that goes rail-to-rail in one DDS cycle. Nice. We conjecture
that some digital tricks could do even better, make a steeper
waveform, especially at low frequencies.

It\'s a clock. We don\'t want to filter out harmonics. Who designs
digital clocks with low harmonic content?

A \'digital clock\' would usually be square-wave, neither triangle or sine.

Exactly. Synchronous harmonics add no period jitter. But we want to
make the square clock *after* the analog filter does its Shannon
thing.



--

John Larkin Highland Technology, Inc trk

The cork popped merrily, and Lord Peter rose to his feet.
\"Bunter\", he said, \"I give you a toast. The triumph of Instinct over Reason\"

 

[John Larkin]

On Sun, 7 Aug 2022 19:07:02 +0200, Gerhard Hoffmann <dk4xp@arcor.de>
wrote:

Am 07.08.22 um 15:55 schrieb John Larkin:

Why do the sine lookup? The ms D bits of the accumulator are a
triangle waveform. Why not DAC and filter that? The lowpass filter
wouldn\'t know... it would interpolate as usual.

Why not use some clever VHDL and make a trapezoid with faster rise
time, especially at low frequencies where time quantization and
comparator errors make a lot of period jitter and the filter doesn\'t
interpolate.

If one just takes the MSB of the phase accumulator, you have a
programmable-frequency clock without all that other junk. But its
period is quantized to the clock, which gets totally ugly at high
frequencies. I wonder if some clever math could make that output
always some perfect multiple of, say 1 Hz or 1 mHz.

There was a DDS from Stanford Telecom (Standard? T.) that was
BCD and that thusly could produce exact mHz from 10 MHz etc.

We discussed a radix-10 phase accumulator. That\'s not awful.

Just using the MSB would inherit awful phase modulation / noise.

The MSB is the exact average programmed frequency but has one clock of
p-p jitter.

I have published a sine table on opencores.org with a
DDS as test bed. It stores only one quarter of the circle and
mirrors the rest. Table size is generic and taken automagically
from the connected busses. 0 up to 10 pipeline registers may be
selected and are strategically inserted as food for the register
balancer.

Without any work it ran at 230 MHz on a Spartan6 eval board,
just by asking for 250 MHz. I needed only 200 MHz.
Sine and cosine are available at no extra table cost to feed
the multipliers of a complex mixer.

It is pure VHDL that does not lock you into a silicon vendor.

https://opencores.org/projects/sincos

Cordic was ruled out for me because of its delays.
It is hard to get a digital Costas loop stable when
it takes a year for the oscillator to follow and it\'s
staggering around in the mean time after a frequency change.

Cheers, Gerhard

My question was, why make a sine wave if the final result is a digital
clock?



--

John Larkin Highland Technology, Inc trk

The cork popped merrily, and Lord Peter rose to his feet.
\"Bunter\", he said, \"I give you a toast. The triumph of Instinct over Reason\"

 

[whit3rd]

On Sunday, August 7, 2022 at 10:57:17 AM UTC-7, John Larkin wrote:

My question was, why make a sine wave if the final result is a digital
clock?

Do you want the digital clock edges to be synchronous with an existing source, or
asynchronous? Mathematically, the creation of an asynchronous clock is
not gonna happen in clocked logic circuitry, it has to have an analog component.

 

[Gerhard Hoffmann]

Am 07.08.22 um 19:57 schrieb John Larkin:

My question was, why make a sine wave if the final result is a digital
clock?

You can get by with a counter if you are happy with an exact subharmonic
of the clock source.

Trying to build a DDS without a sine table is like shooting
oneself into both feet and then enjoying the feeling as the
proud winner of the filtering wheelchair championchip.

I said it here 2 or 3 years ago that the cleanest time stamp
is a sine zero crossing and maybe a qualifier.
No dispersion, minimum noise bandwidth.


Least jitter sine -> square conversion:

Oliver Collins, Member, IEEE
The Design of Low Jitter Hard Limiters
IEEE TRANSACTIONS ON COMMUNICATIONS, VOL. 44, NO. 5, MAY 1996

It resurfaces now & then in the time nuts list on febo.com.


>> Cheers, Gerhard

 

[John Larkin]

On Sun, 7 Aug 2022 11:09:02 -0700 (PDT), whit3rd <whit3rd@gmail.com>
wrote:

On Sunday, August 7, 2022 at 10:57:17 AM UTC-7, John Larkin wrote:

My question was, why make a sine wave if the final result is a digital
clock?

Do you want the digital clock edges to be synchronous with an existing source, or
asynchronous? Mathematically, the creation of an asynchronous clock is
not gonna happen in clocked logic circuitry, it has to have an analog component.

Of course. The analog components are dac, filter, comparator.

I want a programmable internal trigger rate for a pulse generator.

A 48-bit DDS will make a frequency of Fclk * N / 2^48 for arbitrary N,
up to Nyquist. But it gets messy at low frequencies where the dac is
incremented infrequently and the filter doesn\'t do much.

--

John Larkin Highland Technology, Inc trk

The cork popped merrily, and Lord Peter rose to his feet.
\"Bunter\", he said, \"I give you a toast. The triumph of Instinct over Reason\"

 

[John Larkin]

On Sun, 7 Aug 2022 21:00:02 +0200, Gerhard Hoffmann <dk4xp@arcor.de>
wrote:

Am 07.08.22 um 19:57 schrieb John Larkin:


My question was, why make a sine wave if the final result is a digital
clock?

You can get by with a counter if you are happy with an exact subharmonic
of the clock source.

Trying to build a DDS without a sine table is like shooting
oneself into both feet and then enjoying the feeling as the
proud winner of the filtering wheelchair championchip.

What advantage does a sine table have over making a sawtooth directly
from the MSBs of the phase accumulator? The sine conversion just adds
errors, seems to me.

Near the zero crossing, the filter can\'t tell them apart. The
comparator isn\'t very smart.



--

John Larkin Highland Technology, Inc trk

The cork popped merrily, and Lord Peter rose to his feet.
\"Bunter\", he said, \"I give you a toast. The triumph of Instinct over Reason\"

 

[Ricky]

On Sunday, August 7, 2022 at 3:53:55 PM UTC-4, John Larkin wrote:

On Sun, 7 Aug 2022 21:00:02 +0200, Gerhard Hoffmann <dk...@arcor.de
wrote:
Am 07.08.22 um 19:57 schrieb John Larkin:


My question was, why make a sine wave if the final result is a digital
clock?

You can get by with a counter if you are happy with an exact subharmonic
of the clock source.

Trying to build a DDS without a sine table is like shooting
oneself into both feet and then enjoying the feeling as the
proud winner of the filtering wheelchair championchip.
What advantage does a sine table have over making a sawtooth directly
from the MSBs of the phase accumulator? The sine conversion just adds
errors, seems to me.

Near the zero crossing, the filter can\'t tell them apart. The
comparator isn\'t very smart.

What a myopic view. The most difficult part of designing a DDS, is the phase truncation error which produces close in spurs, which can not be effectively filtered.

Whatever. In many ways, Larkin is like many others here who come for expert advice, then ignore it when they don\'t understand it. It would be so much more productive if he would ask relevant questions instead of trying to think in terms that don\'t apply like localizing the action of a filter to a small segment of the waveform, when filters are typically IIR and so reflect a history of the signal.

--

Rick C.

-- Get 1,000 miles of free Supercharging
-- Tesla referral code - https://ts.la/richard11209

 

[Ricky]

On Sunday, August 7, 2022 at 3:48:51 PM UTC-4, John Larkin wrote:

On Sun, 7 Aug 2022 11:09:02 -0700 (PDT), whit3rd <whi...@gmail.com
wrote:
On Sunday, August 7, 2022 at 10:57:17 AM UTC-7, John Larkin wrote:

My question was, why make a sine wave if the final result is a digital
clock?

Do you want the digital clock edges to be synchronous with an existing source, or
asynchronous? Mathematically, the creation of an asynchronous clock is
not gonna happen in clocked logic circuitry, it has to have an analog component.
Of course. The analog components are dac, filter, comparator.

I want a programmable internal trigger rate for a pulse generator.

A 48-bit DDS will make a frequency of Fclk * N / 2^48 for arbitrary N,
up to Nyquist. But it gets messy at low frequencies where the dac is
incremented infrequently and the filter doesn\'t do much.

Sounds like an application for dithering.

--

Rick C.

-+ Get 1,000 miles of free Supercharging
-+ Tesla referral code - https://ts.la/richard11209

 

[Lasse Langwadt Christensen]

søndag den 7. august 2022 kl. 21.48.51 UTC+2 skrev John Larkin:

On Sun, 7 Aug 2022 11:09:02 -0700 (PDT), whit3rd <whi...@gmail.com
wrote:
On Sunday, August 7, 2022 at 10:57:17 AM UTC-7, John Larkin wrote:

My question was, why make a sine wave if the final result is a digital
clock?

Do you want the digital clock edges to be synchronous with an existing source, or
asynchronous? Mathematically, the creation of an asynchronous clock is
not gonna happen in clocked logic circuitry, it has to have an analog component.
Of course. The analog components are dac, filter, comparator.

I want a programmable internal trigger rate for a pulse generator.

A 48-bit DDS will make a frequency of Fclk * N / 2^48 for arbitrary N,
up to Nyquist. But it gets messy at low frequencies where the dac is
incremented infrequently and the filter doesn\'t do much.

if there is no more timing or amplitude steps to use, the only thing you can do it lower the filter cutoff

 

[Gerhard Hoffmann]

Am 07.08.22 um 21:53 schrieb John Larkin:

On Sun, 7 Aug 2022 21:00:02 +0200, Gerhard Hoffmann <dk4xp@arcor.de
wrote:

Am 07.08.22 um 19:57 schrieb John Larkin:


My question was, why make a sine wave if the final result is a digital
clock?

You can get by with a counter if you are happy with an exact subharmonic
of the clock source.

Trying to build a DDS without a sine table is like shooting
oneself into both feet and then enjoying the feeling as the
proud winner of the filtering wheelchair championchip.

What advantage does a sine table have over making a sawtooth directly
from the MSBs of the phase accumulator? The sine conversion just adds
errors, seems to me.

Near the zero crossing, the filter can\'t tell them apart. The
comparator isn\'t very smart.

A sine is nowhere steeper than at the zero crossing.
The essence of the Collins paper is that it takes several
pairs of (filter + amplifier) in cascade, not a dumb comparator.

Talking of comparators, I just got quite disappointing results
from an ADCMP580, CML.

~70 ps rise and fall time, should be half of that, typ.

rising edge, falling edge is abt. the same:
<
https://www.flickr.com/photos/137684711@N07/52270474769/in/dateposted-public/
>

entire cycle:
<
https://www.flickr.com/photos/137684711@N07/52269244147/in/dateposted-public/

Gerhard

 

[John Larkin]

On Sun, 7 Aug 2022 13:27:44 -0700 (PDT), Lasse Langwadt Christensen
<langwadt@fonz.dk> wrote:

søndag den 7. august 2022 kl. 21.48.51 UTC+2 skrev John Larkin:
On Sun, 7 Aug 2022 11:09:02 -0700 (PDT), whit3rd <whi...@gmail.com
wrote:
On Sunday, August 7, 2022 at 10:57:17 AM UTC-7, John Larkin wrote:

My question was, why make a sine wave if the final result is a digital
clock?

Do you want the digital clock edges to be synchronous with an existing source, or
asynchronous? Mathematically, the creation of an asynchronous clock is
not gonna happen in clocked logic circuitry, it has to have an analog component.
Of course. The analog components are dac, filter, comparator.

I want a programmable internal trigger rate for a pulse generator.

A 48-bit DDS will make a frequency of Fclk * N / 2^48 for arbitrary N,
up to Nyquist. But it gets messy at low frequencies where the dac is
incremented infrequently and the filter doesn\'t do much.

if there is no more timing or amplitude steps to use, the only thing you can do it lower the filter cutoff

That has problems too.

We were thinking that you could gain-up and clip the sine wave to
increase the zero-cross slope. The logical end of that is to make a
trapezoid with a steep rise.

The DAC lsb increments rarely at low frequencies, so magically include
some lower phase accumulator bits to effectively increase the DAC
sample rate on that steep slope. Digitally interpolate.

One way to get low trigger rates, which we do now, is synthesize an
octave or so at the high end of the DDS and divide after the
comparator. That has uglies if the DDS is slow to program, like an SPI
interface. It\'s not so awful if we make our own DDS in an FPGA, so we
can change the DDS frequency and the divisor (almost) simultaneously.

--

John Larkin Highland Technology, Inc trk

The cork popped merrily, and Lord Peter rose to his feet.
\"Bunter\", he said, \"I give you a toast. The triumph of Instinct over Reason\"