DDS question: why sine lookup?...

[john larkin]

A DDS clock generator uses an NCO (a phase accumulator) and takes some
number of MSBs, maps through a sine lookup table, drives a DAC and a
lowpass filter and finally a comparator. The DAC output gets pretty
ratty near Nyquist, and the filter smooths out and interpolates the
steps and reduces jitter.

But why do the sine lookup? Why not use the phase accumulator MSBs
directly and get a sawtooth, and filter that?

The lowpass filter looks backwards in time for a bunch of ugly samples
to average into a straight line. The older sine samples are the wrong
polarity! If the filter impulse response is basically zero over the
period of the sawtooth, and we compare near the peak, we\'ll average a
lot of steps and forget the big sawtooth reset.

I want to make four programmable clocks and don\'t want to buy DDS
chips. So use a cheap FPGA and a few resistors as the DAC. Synthesize
one octave and divide down for lower frequencies. Gotta sim that.

LT Spice really sucks with digital stuff. Building a phase accumulator
would be a horror. I\'m working on a PowerBasic program that can dump
waveforms to a PWL file that LT Spice can import and filter. Qspice
would be better but I\'d have to learn that and hack the phase
accumulator in c.

 

[Gerhard Hoffmann]

Am 06.05.25 um 17:48 schrieb john larkin:

A DDS clock generator uses an NCO (a phase accumulator) and takes some
number of MSBs, maps through a sine lookup table, drives a DAC and a
lowpass filter and finally a comparator. The DAC output gets pretty
ratty near Nyquist, and the filter smooths out and interpolates the
steps and reduces jitter.

But why do the sine lookup? Why not use the phase accumulator MSBs
directly and get a sawtooth, and filter that?

The lowpass filter looks backwards in time for a bunch of ugly samples
to average into a straight line. The older sine samples are the wrong
polarity! If the filter impulse response is basically zero over the
period of the sawtooth, and we compare near the peak, we\'ll average a
lot of steps and forget the big sawtooth reset.

I want to make four programmable clocks and don\'t want to buy DDS
chips. So use a cheap FPGA and a few resistors as the DAC. Synthesize
one octave and divide down for lower frequencies. Gotta sim that.

LT Spice really sucks with digital stuff. Building a phase accumulator
would be a horror. I\'m working on a PowerBasic program that can dump
waveforms to a PWL file that LT Spice can import and filter. Qspice
would be better but I\'d have to learn that and hack the phase
accumulator in c.

Spice was made for solving systems of differential equations with
some semantic sugar added, but it was never intended as a digital
simulator. Yes, you can abuse it but the simulation drowns in
details that no one is interested in. The right tools would be
Modelsim/Questasim/GHDL or
< https://en.wikipedia.org/wiki/List_of_HDL_simulators >

I did publish a DDS in VHDL. It\'s on opencores.org under arithmetic
named sincos.
The number of pipeline stages, log table dimensions etc can be
set at will; bus sizes auto-adjust to the busses that are attached.
Mirroring of the sine table is also automatic. sin and cos are
available at the same time without requiring more hardware.

The only thing that\'s missing is Sunderland\'s lookup table
optimization that decomposes the ROM into two and gets a
10...50 times reduction in ROM size. I did not need it
and its added delay was not welcome in my PLL application.

<
https://www.researchgate.net/publication/220236321_An_Improved_Linear_Difference_Method_with_High_ROM_Compression_Ratio_in_Direct_Digital_Frequency_Synthesizer
>

On a Spartan 6 eval board it runs at 200 MHz out of the box.


Cheers, Gerhard

 

[Don]

Gerhard Hoffmann wrote:

<snip>

Spice was made for solving systems of differential equations with
some semantic sugar added, but it was never intended as a digital
^^^^^^^^^^^^^^^^^^^

Artful alliteration acknowledgement - attaboy!

simulator. Yes, you can abuse it but the simulation drowns in
details that no one is interested in. The right tools would be
Modelsim/Questasim/GHDL or
https://en.wikipedia.org/wiki/List_of_HDL_simulators

I did publish a DDS in VHDL. It\'s on opencores.org under arithmetic
named sincos.

<https://opencores.org/projects/sincos>

Thank you for sharing.

Danke,

--
Don, KB7RPU, https://www.qsl.net/kb7rpu
There was a young lady named Bright Whose speed was far faster than light;
She set out one day In a relative way And returned on the previous night.

 

[john larkin]

On Tue, 6 May 2025 16:46:16 -0400, Phil Hobbs
<pcdhSpamMeSenseless@electrooptical.net> wrote:

On 2025-05-06 15:00, Jeroen Belleman wrote:
On 5/6/25 17:48, john larkin wrote:
A DDS clock generator uses an NCO (a phase accumulator) and takes some
number of MSBs, maps through a sine lookup table, drives a DAC and a
lowpass filter and finally a comparator. The DAC output gets pretty
ratty near Nyquist, and the filter smooths out and interpolates the
steps and reduces jitter.

But why do the sine lookup? Why not use the phase accumulator MSBs
directly and get a sawtooth, and filter that?

The lowpass filter looks backwards in time for a bunch of ugly samples
to average into a straight line. The older sine samples are the wrong
polarity! If the filter impulse response is basically zero over the
period of the sawtooth, and we compare near the peak, we\'ll average a
lot of steps and forget the big sawtooth reset. [...]

Two things are immediately obvious: First, the sawtooth will have
a variable frequency, and the filter won\'t have a zero response
for all possible frequencies.

Second, the usual reconstruction filters do *not* interpolate
into straight lines.

Beyond that, I would have to think this over a bit more.

Jeroen Belleman




You don\'t want to use a sawtooth if you can help it, because it has huge
contributions from all harmonic orders. It also puts a lot of demands
on the slew rate and settling of the DAC and any amplifiers used in the
filtering. Errors there are of course nonlinear, because once an amp is
in slew limiting, it stops responding to its inputs for a bit.

I was thinking that my DAC is just 5 or 6 resistors hanging off some
FPGA pins, and that drives a 3rd order (CLC) LC filter and the
comparator. So no opamps.

It also emphasizes the close-in spurs. Say you have two N-bit DDSes
running at the same average frequency but different phases. The DAC
samples only the M high-order bits. It happens that at time t=0 the
accumulator overflows on the same clock cycle on both.

This will continue to happen until one of them overflows a cycle early
because the bottom N-M bits rolled over.

The resulting voltage difference between them is a full-scale,
one-clock-wide pulse, followed by a noisy baseline as the bottom N-M
bits roll over into the DAC\'s LSB at different times. This will repeat
every cycle until the other DDS catches up. This scenario will play out
some number of times in a full period, i.e. the least common multiple of
the accumulator size and the increment in clocks.

The energy in that glitch is much larger than in the noisy baseline, and
its timing is variable in complicated ways.

A triangle would be better, and of course that could be done pretty
simply, e.g. with a flip flop controlling a bunch of XOR gates, if you
don\'t mind halving the frequency.

Once you have a lookup table, a sine is as easy as anything else, and
minimizes the demands on the DAC, filters and amplifiers.

Cheers

Phil Hobbs

If I\'m using, say, 8 MS phase accumulator bits and a 5-bit DAC and
synthesizing one octave of frequency, the sine table is no big deal.
256 bytes of RAM per DDS unfolded.

I\'ve been playing with sims. The sawtooth works OK but may be too
cute. I\'ll compare it to sines.

The pseudo-DAC output is always positive. It can go into one
comparator input and I can RC lowpass filter same into the other, to
switch on the waveform midpoint.

I reall need to get my FPGA kids to run the phase accumulator at 160
MHz. Run way below Nyquist.

 

[Bill Sloman]

On 7/05/2025 1:48 am, john larkin wrote:

A DDS clock generator uses an NCO (a phase accumulator) and takes some
number of MSBs, maps through a sine lookup table, drives a DAC and a
lowpass filter and finally a comparator. The DAC output gets pretty
ratty near Nyquist, and the filter smooths out and interpolates the
steps and reduces jitter.

But why do the sine lookup? Why not use the phase accumulator MSBs
directly and get a sawtooth, and filter that?

Because the sawtooth has much the same harmonic content as a triangular
wave, all the odd harmonics (up to the speed of the switches involved)
at amplitudes that decrease as the square of the harmonic number

The lowpass filter looks backwards in time for a bunch of ugly samples
to average into a straight line. The older sine samples are the wrong
polarity!

But they are delayed as they go through the low pass filter, and that
gets the polarity right, if you use a linear phase low pass filter,
which doesn\'t have a sharp cut-off.


Read Williams and Taylor\'s \"Electronic Filer Design Handbook\". I\'ve got
the second edition - ISBN 0-07-070434-1 - and the third - 0-07-070430-9
- on my Kindle.

If the filter impulse response is basically zero over the
period of the sawtooth, and we compare near the peak, we\'ll average a
lot of steps and forget the big sawtooth reset.

You can simulate that in LTSpice, whic is safer than hand-waving
speculation.

I want to make four programmable clocks and don\'t want to buy DDS
chips. So use a cheap FPGA and a few resistors as the DAC.

Trading off development time against parts cost. The Analog Devices
development engineers have had longer to get their design right than you
will have, so their end result may be more nearly perfect.

Synthesize
one octave and divide down for lower frequencies. Gotta sim that.

Good idea.

LT Spice really sucks with digital stuff. Building a phase accumulator
would be a horror. I\'m working on a PowerBasic program that can dump
waveforms to a PWL file that LT Spice can import and filter. Qspice
would be better but I\'d have to learn that and hack the phase
accumulator in c.

Since you don\'t need to simulate the digital stuff, LTSpice will work
fine. Getting the PWL file to simulate the phase accumulator output may
be a chore, but google might find one for you.

--
Bill Sloman, Sydney

 

[Arie de Muijnck]

On 2025-05-07 00:50, john larkin wrote:

On Tue, 6 May 2025 16:46:16 -0400, Phil Hobbs
pcdhSpamMeSenseless@electrooptical.net> wrote:

On 2025-05-06 15:00, Jeroen Belleman wrote:
On 5/6/25 17:48, john larkin wrote:
A DDS clock generator uses an NCO (a phase accumulator) and takes some
number of MSBs, maps through a sine lookup table, drives a DAC and a
lowpass filter and finally a comparator. The DAC output gets pretty
ratty near Nyquist, and the filter smooths out and interpolates the
steps and reduces jitter.

But why do the sine lookup? Why not use the phase accumulator MSBs
directly and get a sawtooth, and filter that?

The lowpass filter looks backwards in time for a bunch of ugly samples
to average into a straight line. The older sine samples are the wrong
polarity! If the filter impulse response is basically zero over the
period of the sawtooth, and we compare near the peak, we\'ll average a
lot of steps and forget the big sawtooth reset. [...]

Two things are immediately obvious: First, the sawtooth will have
a variable frequency, and the filter won\'t have a zero response
for all possible frequencies.

Second, the usual reconstruction filters do *not* interpolate
into straight lines.

Beyond that, I would have to think this over a bit more.

Jeroen Belleman




You don\'t want to use a sawtooth if you can help it, because it has huge
contributions from all harmonic orders. It also puts a lot of demands
on the slew rate and settling of the DAC and any amplifiers used in the
filtering. Errors there are of course nonlinear, because once an amp is
in slew limiting, it stops responding to its inputs for a bit.

I was thinking that my DAC is just 5 or 6 resistors hanging off some
FPGA pins, and that drives a 3rd order (CLC) LC filter and the
comparator. So no opamps.




It also emphasizes the close-in spurs. Say you have two N-bit DDSes
running at the same average frequency but different phases. The DAC
samples only the M high-order bits. It happens that at time t=0 the
accumulator overflows on the same clock cycle on both.

This will continue to happen until one of them overflows a cycle early
because the bottom N-M bits rolled over.

The resulting voltage difference between them is a full-scale,
one-clock-wide pulse, followed by a noisy baseline as the bottom N-M
bits roll over into the DAC\'s LSB at different times. This will repeat
every cycle until the other DDS catches up. This scenario will play out
some number of times in a full period, i.e. the least common multiple of
the accumulator size and the increment in clocks.

The energy in that glitch is much larger than in the noisy baseline, and
its timing is variable in complicated ways.

A triangle would be better, and of course that could be done pretty
simply, e.g. with a flip flop controlling a bunch of XOR gates, if you
don\'t mind halving the frequency.

Once you have a lookup table, a sine is as easy as anything else, and
minimizes the demands on the DAC, filters and amplifiers.

Cheers

Phil Hobbs

If I\'m using, say, 8 MS phase accumulator bits and a 5-bit DAC and
synthesizing one octave of frequency, the sine table is no big deal.
256 bytes of RAM per DDS unfolded.

I\'ve been playing with sims. The sawtooth works OK but may be too
cute. I\'ll compare it to sines.

The pseudo-DAC output is always positive. It can go into one
comparator input and I can RC lowpass filter same into the other, to
switch on the waveform midpoint.

I reall need to get my FPGA kids to run the phase accumulator at 160
MHz. Run way below Nyquist.

Can\'t you fold the LIN to SIN conversion in the resistor values?

Arie

 

[john larkin]

On Tue, 6 May 2025 16:46:16 -0400, Phil Hobbs
<pcdhSpamMeSenseless@electrooptical.net> wrote:

On 2025-05-06 15:00, Jeroen Belleman wrote:
On 5/6/25 17:48, john larkin wrote:
A DDS clock generator uses an NCO (a phase accumulator) and takes some
number of MSBs, maps through a sine lookup table, drives a DAC and a
lowpass filter and finally a comparator. The DAC output gets pretty
ratty near Nyquist, and the filter smooths out and interpolates the
steps and reduces jitter.

But why do the sine lookup? Why not use the phase accumulator MSBs
directly and get a sawtooth, and filter that?

The lowpass filter looks backwards in time for a bunch of ugly samples
to average into a straight line. The older sine samples are the wrong
polarity! If the filter impulse response is basically zero over the
period of the sawtooth, and we compare near the peak, we\'ll average a
lot of steps and forget the big sawtooth reset. [...]

Two things are immediately obvious: First, the sawtooth will have
a variable frequency, and the filter won\'t have a zero response
for all possible frequencies.

Second, the usual reconstruction filters do *not* interpolate
into straight lines.

Beyond that, I would have to think this over a bit more.

Jeroen Belleman




You don\'t want to use a sawtooth if you can help it, because it has huge
contributions from all harmonic orders. It also puts a lot of demands
on the slew rate and settling of the DAC and any amplifiers used in the
filtering. Errors there are of course nonlinear, because once an amp is
in slew limiting, it stops responding to its inputs for a bit.

It also emphasizes the close-in spurs. Say you have two N-bit DDSes
running at the same average frequency but different phases. The DAC
samples only the M high-order bits. It happens that at time t=0 the
accumulator overflows on the same clock cycle on both.

This will continue to happen until one of them overflows a cycle early
because the bottom N-M bits rolled over.

The resulting voltage difference between them is a full-scale,
one-clock-wide pulse, followed by a noisy baseline as the bottom N-M
bits roll over into the DAC\'s LSB at different times. This will repeat
every cycle until the other DDS catches up. This scenario will play out
some number of times in a full period, i.e. the least common multiple of
the accumulator size and the increment in clocks.

The energy in that glitch is much larger than in the noisy baseline, and
its timing is variable in complicated ways.

A triangle would be better, and of course that could be done pretty
simply, e.g. with a flip flop controlling a bunch of XOR gates, if you
don\'t mind halving the frequency.

Once you have a lookup table, a sine is as easy as anything else, and
minimizes the demands on the DAC, filters and amplifiers.

Cheers

Phil Hobbs

I\'m Spicing things and what I\'m seeing in the FFT of my DAC output,
with the sawtooth, is giant subharmonics at some magic frequencies.
Those contribute the most period jitter.

May as well use a sine, I guess. Still, my sim tools are useful in
tweaking the detais: NCO clock rate, lookup table size, DAC bits,
filter order. I have several products in design that need DDS clocks,
so some time playing with this is worth it. And it\'s interesting.

My Basic program generates a PWL file, given choices of clock rates,
bits, and waveform. I can import that to LT Spice and take over with
filtering and such. If I just output the obvious steps to the PWL
file, Spice will draw straight lines between points and it looks
awful. I want DAC steps. The fix is to output each point twice,
suitably spaced.

My FPGA guys say that an Efinix T55 can run a 48-bit phase accumulator
at 280 MHz. Yikes. One $10 T20 could make a dozen DDS\'s.

 

[Bill Sloman]

On 7/05/2025 11:32 pm, john larkin wrote:

On Wed, 7 May 2025 11:44:23 +0200, Arie de Muijnck <noreply@ademu.nl
wrote:

On 2025-05-07 00:50, john larkin wrote:
On Tue, 6 May 2025 16:46:16 -0400, Phil Hobbs
pcdhSpamMeSenseless@electrooptical.net> wrote:

On 2025-05-06 15:00, Jeroen Belleman wrote:
On 5/6/25 17:48, john larkin wrote:
A DDS clock generator uses an NCO (a phase accumulator) and takes some
number of MSBs, maps through a sine lookup table, drives a DAC and a
lowpass filter and finally a comparator. The DAC output gets pretty
ratty near Nyquist, and the filter smooths out and interpolates the
steps and reduces jitter.

But why do the sine lookup? Why not use the phase accumulator MSBs
directly and get a sawtooth, and filter that?

The lowpass filter looks backwards in time for a bunch of ugly samples
to average into a straight line. The older sine samples are the wrong
polarity! If the filter impulse response is basically zero over the
period of the sawtooth, and we compare near the peak, we\'ll average a
lot of steps and forget the big sawtooth reset. [...]

Two things are immediately obvious: First, the sawtooth will have
a variable frequency, and the filter won\'t have a zero response
for all possible frequencies.

Second, the usual reconstruction filters do *not* interpolate
into straight lines.

Beyond that, I would have to think this over a bit more.

Jeroen Belleman




You don\'t want to use a sawtooth if you can help it, because it has huge
contributions from all harmonic orders. It also puts a lot of demands
on the slew rate and settling of the DAC and any amplifiers used in the
filtering. Errors there are of course nonlinear, because once an amp is
in slew limiting, it stops responding to its inputs for a bit.

I was thinking that my DAC is just 5 or 6 resistors hanging off some
FPGA pins, and that drives a 3rd order (CLC) LC filter and the
comparator. So no opamps.




It also emphasizes the close-in spurs. Say you have two N-bit DDSes
running at the same average frequency but different phases. The DAC
samples only the M high-order bits. It happens that at time t=0 the
accumulator overflows on the same clock cycle on both.

This will continue to happen until one of them overflows a cycle early
because the bottom N-M bits rolled over.

The resulting voltage difference between them is a full-scale,
one-clock-wide pulse, followed by a noisy baseline as the bottom N-M
bits roll over into the DAC\'s LSB at different times. This will repeat
every cycle until the other DDS catches up. This scenario will play out
some number of times in a full period, i.e. the least common multiple of
the accumulator size and the increment in clocks.

The energy in that glitch is much larger than in the noisy baseline, and
its timing is variable in complicated ways.

A triangle would be better, and of course that could be done pretty
simply, e.g. with a flip flop controlling a bunch of XOR gates, if you
don\'t mind halving the frequency.

Once you have a lookup table, a sine is as easy as anything else, and
minimizes the demands on the DAC, filters and amplifiers.

Cheers

Phil Hobbs

If I\'m using, say, 8 MS phase accumulator bits and a 5-bit DAC and
synthesizing one octave of frequency, the sine table is no big deal.
256 bytes of RAM per DDS unfolded.

I\'ve been playing with sims. The sawtooth works OK but may be too
cute. I\'ll compare it to sines.

The pseudo-DAC output is always positive. It can go into one
comparator input and I can RC lowpass filter same into the other, to
switch on the waveform midpoint.

I reall need to get my FPGA kids to run the phase accumulator at 160
MHz. Run way below Nyquist.



Can\'t you fold the LIN to SIN conversion in the resistor values?

I don\'t know.

You really ought to find out. Hanging resistors on successive taps of a
shift register creates a Finite Impulse Response Filter. You have to
taper the resistor values with a Hamming window to avoid Gibbs
oscillations - I found out about that the hard way, but it isn\'t difficult.

You can certainly use one to convert a square wave into a pretty good
approximation to a sine wave.

It doesn\'t lend itself to non-integer frequency division.

I can buy a small cheap R-2R resistor network, and a 8-8
bit sine lookup is easy in an FPGA.

I ended up having to use 10ppm 0.1% E96 resistors, and the more critical
to get each resistance sufficiently correct, but I used a fairly long
shift register. I was quite fond of the female bat acoustician I put the
gear together for, and went in for a bit of over-kill.

> Resistors are linear and sine is nonlinear.

Not a relevant point.

--
Bill Sloman, Sydney

 

[Martin Brown]

On 06/05/2025 16:48, john larkin wrote:

A DDS clock generator uses an NCO (a phase accumulator) and takes some
number of MSBs, maps through a sine lookup table, drives a DAC and a
lowpass filter and finally a comparator. The DAC output gets pretty
ratty near Nyquist, and the filter smooths out and interpolates the
steps and reduces jitter.

But why do the sine lookup? Why not use the phase accumulator MSBs
directly and get a sawtooth, and filter that?

A saw tooth wave has a huge step like discontinuity in it which looks
very ugly in the frequency domain with strong harmonics. Strong sharp
features in time domain are broad in frequency space and vice versa.

If you wanted something a bit different then detecting the phase
accumulator overflow and reversing the count sense to get a triangle
wave might be an option (at half the frequency). Needs some very careful
maths at the boundary flips to avoid introducing jitter.

From that triangle wave you can use HP\'s wizard diode shaping network
trick to get a pretty good clean sine wave.

--
Martin Brown

 

[john larkin]

On Wed, 7 May 2025 20:32:41 +0100, Martin Brown
<\'\'\'newspam\'\'\'@nonad.co.uk> wrote:

On 06/05/2025 16:48, john larkin wrote:
A DDS clock generator uses an NCO (a phase accumulator) and takes some
number of MSBs, maps through a sine lookup table, drives a DAC and a
lowpass filter and finally a comparator. The DAC output gets pretty
ratty near Nyquist, and the filter smooths out and interpolates the
steps and reduces jitter.

But why do the sine lookup? Why not use the phase accumulator MSBs
directly and get a sawtooth, and filter that?

A saw tooth wave has a huge step like discontinuity in it which looks
very ugly in the frequency domain with strong harmonics. Strong sharp
features in time domain are broad in frequency space and vice versa.

If you wanted something a bit different then detecting the phase
accumulator overflow and reversing the count sense to get a triangle
wave might be an option (at half the frequency). Needs some very careful
maths at the boundary flips to avoid introducing jitter.

From that triangle wave you can use HP\'s wizard diode shaping network
trick to get a pretty good clean sine wave.

Yes, a triangle would be better than a sawtooth... fewer nasty
subharmonics. But we may as well stick with the classic boring sine
wave. The sine lookup is trivial in an FPGA.

 

[john larkin]

On Wed, 7 May 2025 20:27:58 -0400, bitrex <user@example.net> wrote:

On 5/7/2025 4:01 PM, john larkin wrote:
On Wed, 7 May 2025 20:32:41 +0100, Martin Brown
\'\'\'newspam\'\'\'@nonad.co.uk> wrote:

On 06/05/2025 16:48, john larkin wrote:
A DDS clock generator uses an NCO (a phase accumulator) and takes some
number of MSBs, maps through a sine lookup table, drives a DAC and a
lowpass filter and finally a comparator. The DAC output gets pretty
ratty near Nyquist, and the filter smooths out and interpolates the
steps and reduces jitter.

But why do the sine lookup? Why not use the phase accumulator MSBs
directly and get a sawtooth, and filter that?

A saw tooth wave has a huge step like discontinuity in it which looks
very ugly in the frequency domain with strong harmonics. Strong sharp
features in time domain are broad in frequency space and vice versa.

If you wanted something a bit different then detecting the phase
accumulator overflow and reversing the count sense to get a triangle
wave might be an option (at half the frequency). Needs some very careful
maths at the boundary flips to avoid introducing jitter.

From that triangle wave you can use HP\'s wizard diode shaping network
trick to get a pretty good clean sine wave.

Yes, a triangle would be better than a sawtooth... fewer nasty
subharmonics. But we may as well stick with the classic boring sine
wave. The sine lookup is trivial in an FPGA.


A band-limited square wave is pretty space & computation-efficient, you
just store the Gibbs phenomena portion of the wave to whatever harmonic
level you desire, play it back, and then sit there and wait during the
DC parts of the wave.

If you then integrate a band-limited square wave you get a band-limited
triangle wave directly.

If I could make a square wave from the MSBs of the phase accumulator,
I might not need the DAC and filter and comparator.

Just using the MSB of the phase accumulator is the right frequency,
but it\'s very jitterey.

So, is there a way to examine some number of MSBs and make an edge
with high time resolution, all digitally, all inside the FPGA? To even
1 clock resolution, preferably better?

There probably is.

 

[Phil Hobbs]

On 2025-05-07 22:21, john larkin wrote:

On Wed, 7 May 2025 20:27:58 -0400, bitrex <user@example.net> wrote:

On 5/7/2025 4:01 PM, john larkin wrote:
On Wed, 7 May 2025 20:32:41 +0100, Martin Brown
\'\'\'newspam\'\'\'@nonad.co.uk> wrote:

On 06/05/2025 16:48, john larkin wrote:
A DDS clock generator uses an NCO (a phase accumulator) and takes some
number of MSBs, maps through a sine lookup table, drives a DAC and a
lowpass filter and finally a comparator. The DAC output gets pretty
ratty near Nyquist, and the filter smooths out and interpolates the
steps and reduces jitter.

But why do the sine lookup? Why not use the phase accumulator MSBs
directly and get a sawtooth, and filter that?

A saw tooth wave has a huge step like discontinuity in it which looks
very ugly in the frequency domain with strong harmonics. Strong sharp
features in time domain are broad in frequency space and vice versa.

If you wanted something a bit different then detecting the phase
accumulator overflow and reversing the count sense to get a triangle
wave might be an option (at half the frequency). Needs some very careful
maths at the boundary flips to avoid introducing jitter.

From that triangle wave you can use HP\'s wizard diode shaping network
trick to get a pretty good clean sine wave.

Yes, a triangle would be better than a sawtooth... fewer nasty
subharmonics. But we may as well stick with the classic boring sine
wave. The sine lookup is trivial in an FPGA.


A band-limited square wave is pretty space & computation-efficient, you
just store the Gibbs phenomena portion of the wave to whatever harmonic
level you desire, play it back, and then sit there and wait during the
DC parts of the wave.

If you then integrate a band-limited square wave you get a band-limited
triangle wave directly.

If I could make a square wave from the MSBs of the phase accumulator,
I might not need the DAC and filter and comparator.

Just using the MSB of the phase accumulator is the right frequency,
but it\'s very jitterey.

So, is there a way to examine some number of MSBs and make an edge
with high time resolution, all digitally, all inside the FPGA? To even
1 clock resolution, preferably better?

There probably is.

Don\'t think so. Since you have exactly two edges per cycle, it would
have the same problem as the sawtooth, for the same reason. You could
interpolate the same sort of way as in a DDG.

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC / Hobbs ElectroOptics
Optics, Electro-optics, Photonics, Analog Electronics
Briarcliff Manor NY 10510

http://electrooptical.net
http://hobbs-eo.com

 

[john larkin]

On Thu, 8 May 2025 14:20:21 -0400, Phil Hobbs
<pcdhSpamMeSenseless@electrooptical.net> wrote:

On 2025-05-07 22:21, john larkin wrote:
On Wed, 7 May 2025 20:27:58 -0400, bitrex <user@example.net> wrote:

On 5/7/2025 4:01 PM, john larkin wrote:
On Wed, 7 May 2025 20:32:41 +0100, Martin Brown
\'\'\'newspam\'\'\'@nonad.co.uk> wrote:

On 06/05/2025 16:48, john larkin wrote:
A DDS clock generator uses an NCO (a phase accumulator) and takes some
number of MSBs, maps through a sine lookup table, drives a DAC and a
lowpass filter and finally a comparator. The DAC output gets pretty
ratty near Nyquist, and the filter smooths out and interpolates the
steps and reduces jitter.

But why do the sine lookup? Why not use the phase accumulator MSBs
directly and get a sawtooth, and filter that?

A saw tooth wave has a huge step like discontinuity in it which looks
very ugly in the frequency domain with strong harmonics. Strong sharp
features in time domain are broad in frequency space and vice versa.

If you wanted something a bit different then detecting the phase
accumulator overflow and reversing the count sense to get a triangle
wave might be an option (at half the frequency). Needs some very careful
maths at the boundary flips to avoid introducing jitter.

From that triangle wave you can use HP\'s wizard diode shaping network
trick to get a pretty good clean sine wave.

Yes, a triangle would be better than a sawtooth... fewer nasty
subharmonics. But we may as well stick with the classic boring sine
wave. The sine lookup is trivial in an FPGA.


A band-limited square wave is pretty space & computation-efficient, you
just store the Gibbs phenomena portion of the wave to whatever harmonic
level you desire, play it back, and then sit there and wait during the
DC parts of the wave.

If you then integrate a band-limited square wave you get a band-limited
triangle wave directly.

If I could make a square wave from the MSBs of the phase accumulator,
I might not need the DAC and filter and comparator.

Just using the MSB of the phase accumulator is the right frequency,
but it\'s very jitterey.

So, is there a way to examine some number of MSBs and make an edge
with high time resolution, all digitally, all inside the FPGA? To even
1 clock resolution, preferably better?

There probably is.




Don\'t think so. Since you have exactly two edges per cycle, it would
have the same problem as the sawtooth, for the same reason. You could
interpolate the same sort of way as in a DDG.

Cheers

Phil Hobbs

If some N bits can be sent to a DAC and a filter, to interpolate to
better time accuracy than just using the MS bit, then the equivalent
interpolation should be possible digitally, inside the FPGA.

We can always spin up a PLL to get as fast a clock as the logic can
stand. And sub-clock tricks have been done.

 

[Phil Hobbs]

On 2025-05-08 14:58, john larkin wrote:

On Thu, 8 May 2025 14:20:21 -0400, Phil Hobbs
pcdhSpamMeSenseless@electrooptical.net> wrote:

On 2025-05-07 22:21, john larkin wrote:
On Wed, 7 May 2025 20:27:58 -0400, bitrex <user@example.net> wrote:

On 5/7/2025 4:01 PM, john larkin wrote:
On Wed, 7 May 2025 20:32:41 +0100, Martin Brown
\'\'\'newspam\'\'\'@nonad.co.uk> wrote:

On 06/05/2025 16:48, john larkin wrote:
A DDS clock generator uses an NCO (a phase accumulator) and takes some
number of MSBs, maps through a sine lookup table, drives a DAC and a
lowpass filter and finally a comparator. The DAC output gets pretty
ratty near Nyquist, and the filter smooths out and interpolates the
steps and reduces jitter.

But why do the sine lookup? Why not use the phase accumulator MSBs
directly and get a sawtooth, and filter that?

A saw tooth wave has a huge step like discontinuity in it which looks
very ugly in the frequency domain with strong harmonics. Strong sharp
features in time domain are broad in frequency space and vice versa.

If you wanted something a bit different then detecting the phase
accumulator overflow and reversing the count sense to get a triangle
wave might be an option (at half the frequency). Needs some very careful
maths at the boundary flips to avoid introducing jitter.

From that triangle wave you can use HP\'s wizard diode shaping network
trick to get a pretty good clean sine wave.

Yes, a triangle would be better than a sawtooth... fewer nasty
subharmonics. But we may as well stick with the classic boring sine
wave. The sine lookup is trivial in an FPGA.


A band-limited square wave is pretty space & computation-efficient, you
just store the Gibbs phenomena portion of the wave to whatever harmonic
level you desire, play it back, and then sit there and wait during the
DC parts of the wave.

If you then integrate a band-limited square wave you get a band-limited
triangle wave directly.

If I could make a square wave from the MSBs of the phase accumulator,
I might not need the DAC and filter and comparator.

Just using the MSB of the phase accumulator is the right frequency,
but it\'s very jitterey.

So, is there a way to examine some number of MSBs and make an edge
with high time resolution, all digitally, all inside the FPGA? To even
1 clock resolution, preferably better?

There probably is.




Don\'t think so. Since you have exactly two edges per cycle, it would
have the same problem as the sawtooth, for the same reason. You could
interpolate the same sort of way as in a DDG.

Cheers

Phil Hobbs

If some N bits can be sent to a DAC and a filter, to interpolate to
better time accuracy than just using the MS bit, then the equivalent
interpolation should be possible digitally, inside the FPGA.

We can always spin up a PLL to get as fast a clock as the logic can
stand. And sub-clock tricks have been done.

You still have the giant spike between the actual position of the edge
and where it ought to be for a subharmonic-free signal. That\'s less
than one clock wide, so there\'s no way to get rid of it digitally. You
could maybe do some noise shaping thing to put the subharmonics
someplace else, but unless your increment is a factor of 2**(accumulator
width), they\'ll be there.

A full-width DAC, followed by a brickwall lowpass, followed by a
comparator, will get rid of the subharmonics, as would a ramp/threshold
analog delay calculated on a per-cycle basis.

Cheers

Phil Hobbs



--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC / Hobbs ElectroOptics
Optics, Electro-optics, Photonics, Analog Electronics
Briarcliff Manor NY 10510

http://electrooptical.net
http://hobbs-eo.com

 

[john larkin]

On Thu, 8 May 2025 16:24:29 -0400, Phil Hobbs
<pcdhSpamMeSenseless@electrooptical.net> wrote:

On 2025-05-08 14:58, john larkin wrote:
On Thu, 8 May 2025 14:20:21 -0400, Phil Hobbs
pcdhSpamMeSenseless@electrooptical.net> wrote:

On 2025-05-07 22:21, john larkin wrote:
On Wed, 7 May 2025 20:27:58 -0400, bitrex <user@example.net> wrote:

On 5/7/2025 4:01 PM, john larkin wrote:
On Wed, 7 May 2025 20:32:41 +0100, Martin Brown
\'\'\'newspam\'\'\'@nonad.co.uk> wrote:

On 06/05/2025 16:48, john larkin wrote:
A DDS clock generator uses an NCO (a phase accumulator) and takes some
number of MSBs, maps through a sine lookup table, drives a DAC and a
lowpass filter and finally a comparator. The DAC output gets pretty
ratty near Nyquist, and the filter smooths out and interpolates the
steps and reduces jitter.

But why do the sine lookup? Why not use the phase accumulator MSBs
directly and get a sawtooth, and filter that?

A saw tooth wave has a huge step like discontinuity in it which looks
very ugly in the frequency domain with strong harmonics. Strong sharp
features in time domain are broad in frequency space and vice versa.

If you wanted something a bit different then detecting the phase
accumulator overflow and reversing the count sense to get a triangle
wave might be an option (at half the frequency). Needs some very careful
maths at the boundary flips to avoid introducing jitter.

From that triangle wave you can use HP\'s wizard diode shaping network
trick to get a pretty good clean sine wave.

Yes, a triangle would be better than a sawtooth... fewer nasty
subharmonics. But we may as well stick with the classic boring sine
wave. The sine lookup is trivial in an FPGA.


A band-limited square wave is pretty space & computation-efficient, you
just store the Gibbs phenomena portion of the wave to whatever harmonic
level you desire, play it back, and then sit there and wait during the
DC parts of the wave.

If you then integrate a band-limited square wave you get a band-limited
triangle wave directly.

If I could make a square wave from the MSBs of the phase accumulator,
I might not need the DAC and filter and comparator.

Just using the MSB of the phase accumulator is the right frequency,
but it\'s very jitterey.

So, is there a way to examine some number of MSBs and make an edge
with high time resolution, all digitally, all inside the FPGA? To even
1 clock resolution, preferably better?

There probably is.




Don\'t think so. Since you have exactly two edges per cycle, it would
have the same problem as the sawtooth, for the same reason. You could
interpolate the same sort of way as in a DDG.

Cheers

Phil Hobbs

If some N bits can be sent to a DAC and a filter, to interpolate to
better time accuracy than just using the MS bit, then the equivalent
interpolation should be possible digitally, inside the FPGA.

We can always spin up a PLL to get as fast a clock as the logic can
stand. And sub-clock tricks have been done.

You still have the giant spike between the actual position of the edge
and where it ought to be for a subharmonic-free signal. That\'s less
than one clock wide, so there\'s no way to get rid of it digitally. You
could maybe do some noise shaping thing to put the subharmonics
someplace else, but unless your increment is a factor of 2**(accumulator
width), they\'ll be there.

A full-width DAC, followed by a brickwall lowpass, followed by a
comparator, will get rid of the subharmonics, as would a ramp/threshold
analog delay calculated on a per-cycle basis.

Cheers

Phil Hobbs

We could take the phase accumulator \"dac\" MSBs and stuff them into a
brickwall digital lowpass filter, maybe even do the sine mapping
first. The result would be a wide smooth waveform, similar to what the
analog comparator would see, only digital. The zero cross of that
would be our \"DDS comparator output\" clock, to one system clock
quantization. Going to half clock resolution wouldn\'t be hard.

If the phase accumulator clock is 160 MHz, half a clock gives us 3 ns
p-p jitter, and the RMS jitter is 900 ps. (Why square root of 12? We
live in a strange universe.)

That filter logic could be clocked faster than the phase accumulator
clock too. Some crazy PLL rate.

I don\'t want to drive a bunch of 20-bit parallel DACs, or make some
13-pole LC filters, but bits are cheap inside an FPGA.

We know what the output frequency will be, so the digital filter can
be tuned for that. Maybe a narrow bandpass? Kills subharmonics?

Some truly terrible things have been done in FPGAs to get picosecond
resolution delays and time interval measuring.

Sounds like a good senior project.

 

[Phil Hobbs]

john larkin <jl@glen--canyon.com> wrote:

On Thu, 8 May 2025 16:24:29 -0400, Phil Hobbs
pcdhSpamMeSenseless@electrooptical.net> wrote:

On 2025-05-08 14:58, john larkin wrote:
On Thu, 8 May 2025 14:20:21 -0400, Phil Hobbs
pcdhSpamMeSenseless@electrooptical.net> wrote:

On 2025-05-07 22:21, john larkin wrote:
On Wed, 7 May 2025 20:27:58 -0400, bitrex <user@example.net> wrote:

On 5/7/2025 4:01 PM, john larkin wrote:
On Wed, 7 May 2025 20:32:41 +0100, Martin Brown
\'\'\'newspam\'\'\'@nonad.co.uk> wrote:

On 06/05/2025 16:48, john larkin wrote:
A DDS clock generator uses an NCO (a phase accumulator) and takes some
number of MSBs, maps through a sine lookup table, drives a DAC and a
lowpass filter and finally a comparator. The DAC output gets pretty
ratty near Nyquist, and the filter smooths out and interpolates the
steps and reduces jitter.

But why do the sine lookup? Why not use the phase accumulator MSBs
directly and get a sawtooth, and filter that?

A saw tooth wave has a huge step like discontinuity in it which looks
very ugly in the frequency domain with strong harmonics. Strong sharp
features in time domain are broad in frequency space and vice versa.

If you wanted something a bit different then detecting the phase
accumulator overflow and reversing the count sense to get a triangle
wave might be an option (at half the frequency). Needs some very careful
maths at the boundary flips to avoid introducing jitter.

From that triangle wave you can use HP\'s wizard diode shaping network
trick to get a pretty good clean sine wave.

Yes, a triangle would be better than a sawtooth... fewer nasty
subharmonics. But we may as well stick with the classic boring sine
wave. The sine lookup is trivial in an FPGA.


A band-limited square wave is pretty space & computation-efficient, you
just store the Gibbs phenomena portion of the wave to whatever harmonic
level you desire, play it back, and then sit there and wait during the
DC parts of the wave.

If you then integrate a band-limited square wave you get a band-limited
triangle wave directly.

If I could make a square wave from the MSBs of the phase accumulator,
I might not need the DAC and filter and comparator.

Just using the MSB of the phase accumulator is the right frequency,
but it\'s very jitterey.

So, is there a way to examine some number of MSBs and make an edge
with high time resolution, all digitally, all inside the FPGA? To even
1 clock resolution, preferably better?

There probably is.




Don\'t think so. Since you have exactly two edges per cycle, it would
have the same problem as the sawtooth, for the same reason. You could
interpolate the same sort of way as in a DDG.

Cheers

Phil Hobbs

If some N bits can be sent to a DAC and a filter, to interpolate to
better time accuracy than just using the MS bit, then the equivalent
interpolation should be possible digitally, inside the FPGA.

We can always spin up a PLL to get as fast a clock as the logic can
stand. And sub-clock tricks have been done.

You still have the giant spike between the actual position of the edge
and where it ought to be for a subharmonic-free signal. That\'s less
than one clock wide, so there\'s no way to get rid of it digitally. You
could maybe do some noise shaping thing to put the subharmonics
someplace else, but unless your increment is a factor of 2**(accumulator
width), they\'ll be there.

A full-width DAC, followed by a brickwall lowpass, followed by a
comparator, will get rid of the subharmonics, as would a ramp/threshold
analog delay calculated on a per-cycle basis.

Cheers

Phil Hobbs

We could take the phase accumulator \"dac\" MSBs and stuff them into a
brickwall digital lowpass filter, maybe even do the sine mapping
first. The result would be a wide smooth waveform, similar to what the
analog comparator would see, only digital. The zero cross of that
would be our \"DDS comparator output\" clock, to one system clock
quantization. Going to half clock resolution wouldn\'t be hard.

If the phase accumulator clock is 160 MHz, half a clock gives us 3 ns
p-p jitter, and the RMS jitter is 900 ps. (Why square root of 12? We
live in a strange universe.)

That filter logic could be clocked faster than the phase accumulator
clock too. Some crazy PLL rate.

I don\'t want to drive a bunch of 20-bit parallel DACs, or make some
13-pole LC filters, but bits are cheap inside an FPGA.

We know what the output frequency will be, so the digital filter can
be tuned for that. Maybe a narrow bandpass? Kills subharmonics?

Some truly terrible things have been done in FPGAs to get picosecond
resolution delays and time interval measuring.

Sounds like a good senior project.

If the output frequency is known in advance, all ought to be
straightforward—pick a clock frequency that’s an integer multiple.

One VCXO-based PLL should be able to make that.

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs Principal Consultant ElectroOptical Innovations LLC /
Hobbs ElectroOptics Optics, Electro-optics, Photonics, Analog Electronics

 

[john larkin]

On Thu, 8 May 2025 22:28:40 -0000 (UTC), Phil Hobbs
<pcdhSpamMeSenseless@electrooptical.net> wrote:

john larkin <jl@glen--canyon.com> wrote:
On Thu, 8 May 2025 16:24:29 -0400, Phil Hobbs
pcdhSpamMeSenseless@electrooptical.net> wrote:

On 2025-05-08 14:58, john larkin wrote:
On Thu, 8 May 2025 14:20:21 -0400, Phil Hobbs
pcdhSpamMeSenseless@electrooptical.net> wrote:

On 2025-05-07 22:21, john larkin wrote:
On Wed, 7 May 2025 20:27:58 -0400, bitrex <user@example.net> wrote:

On 5/7/2025 4:01 PM, john larkin wrote:
On Wed, 7 May 2025 20:32:41 +0100, Martin Brown
\'\'\'newspam\'\'\'@nonad.co.uk> wrote:

On 06/05/2025 16:48, john larkin wrote:
A DDS clock generator uses an NCO (a phase accumulator) and takes some
number of MSBs, maps through a sine lookup table, drives a DAC and a
lowpass filter and finally a comparator. The DAC output gets pretty
ratty near Nyquist, and the filter smooths out and interpolates the
steps and reduces jitter.

But why do the sine lookup? Why not use the phase accumulator MSBs
directly and get a sawtooth, and filter that?

A saw tooth wave has a huge step like discontinuity in it which looks
very ugly in the frequency domain with strong harmonics. Strong sharp
features in time domain are broad in frequency space and vice versa.

If you wanted something a bit different then detecting the phase
accumulator overflow and reversing the count sense to get a triangle
wave might be an option (at half the frequency). Needs some very careful
maths at the boundary flips to avoid introducing jitter.

From that triangle wave you can use HP\'s wizard diode shaping network
trick to get a pretty good clean sine wave.

Yes, a triangle would be better than a sawtooth... fewer nasty
subharmonics. But we may as well stick with the classic boring sine
wave. The sine lookup is trivial in an FPGA.


A band-limited square wave is pretty space & computation-efficient, you
just store the Gibbs phenomena portion of the wave to whatever harmonic
level you desire, play it back, and then sit there and wait during the
DC parts of the wave.

If you then integrate a band-limited square wave you get a band-limited
triangle wave directly.

If I could make a square wave from the MSBs of the phase accumulator,
I might not need the DAC and filter and comparator.

Just using the MSB of the phase accumulator is the right frequency,
but it\'s very jitterey.

So, is there a way to examine some number of MSBs and make an edge
with high time resolution, all digitally, all inside the FPGA? To even
1 clock resolution, preferably better?

There probably is.




Don\'t think so. Since you have exactly two edges per cycle, it would
have the same problem as the sawtooth, for the same reason. You could
interpolate the same sort of way as in a DDG.

Cheers

Phil Hobbs

If some N bits can be sent to a DAC and a filter, to interpolate to
better time accuracy than just using the MS bit, then the equivalent
interpolation should be possible digitally, inside the FPGA.

We can always spin up a PLL to get as fast a clock as the logic can
stand. And sub-clock tricks have been done.

You still have the giant spike between the actual position of the edge
and where it ought to be for a subharmonic-free signal. That\'s less
than one clock wide, so there\'s no way to get rid of it digitally. You
could maybe do some noise shaping thing to put the subharmonics
someplace else, but unless your increment is a factor of 2**(accumulator
width), they\'ll be there.

A full-width DAC, followed by a brickwall lowpass, followed by a
comparator, will get rid of the subharmonics, as would a ramp/threshold
analog delay calculated on a per-cycle basis.

Cheers

Phil Hobbs

We could take the phase accumulator \"dac\" MSBs and stuff them into a
brickwall digital lowpass filter, maybe even do the sine mapping
first. The result would be a wide smooth waveform, similar to what the
analog comparator would see, only digital. The zero cross of that
would be our \"DDS comparator output\" clock, to one system clock
quantization. Going to half clock resolution wouldn\'t be hard.

If the phase accumulator clock is 160 MHz, half a clock gives us 3 ns
p-p jitter, and the RMS jitter is 900 ps. (Why square root of 12? We
live in a strange universe.)

That filter logic could be clocked faster than the phase accumulator
clock too. Some crazy PLL rate.

I don\'t want to drive a bunch of 20-bit parallel DACs, or make some
13-pole LC filters, but bits are cheap inside an FPGA.

We know what the output frequency will be, so the digital filter can
be tuned for that. Maybe a narrow bandpass? Kills subharmonics?

Some truly terrible things have been done in FPGAs to get picosecond
resolution delays and time interval measuring.

Sounds like a good senior project.



If the output frequency is known in advance, all ought to be
straightforward—pick a clock frequency that’s an integer multiple.

One VCXO-based PLL should be able to make that.

Cheers

Phil Hobbs

The gadget\'s output frequency is known when the user programs it, not
years in advance. When we know the frequency we have to do the math to
program the Fset register over our octave range, and program a
downstream divisor (for, say, a 12 Hz trigger rate) so we have time to
program a digital filter too.

An 8-bit R-2R network and a modest LC filter and an LVDS buffer as a
comparator isn\'t awful, but getting the entire DDS system inside the
FPGA would be cool.

I did consider having a fixed frequency clock and a divisor as our
internal trigger source, and telling the user he has to live with
Fxo/N as the possible choices, but even I have my limits of tackiness.

 

[Phil Hobbs]

john larkin <jl@glen--canyon.com> wrote:

On Thu, 8 May 2025 22:28:40 -0000 (UTC), Phil Hobbs
pcdhSpamMeSenseless@electrooptical.net> wrote:

john larkin <jl@glen--canyon.com> wrote:
On Thu, 8 May 2025 16:24:29 -0400, Phil Hobbs
pcdhSpamMeSenseless@electrooptical.net> wrote:

On 2025-05-08 14:58, john larkin wrote:
On Thu, 8 May 2025 14:20:21 -0400, Phil Hobbs
pcdhSpamMeSenseless@electrooptical.net> wrote:

On 2025-05-07 22:21, john larkin wrote:
On Wed, 7 May 2025 20:27:58 -0400, bitrex <user@example.net> wrote:

On 5/7/2025 4:01 PM, john larkin wrote:
On Wed, 7 May 2025 20:32:41 +0100, Martin Brown
\'\'\'newspam\'\'\'@nonad.co.uk> wrote:

On 06/05/2025 16:48, john larkin wrote:
A DDS clock generator uses an NCO (a phase accumulator) and takes some
number of MSBs, maps through a sine lookup table, drives a DAC and a
lowpass filter and finally a comparator. The DAC output gets pretty
ratty near Nyquist, and the filter smooths out and interpolates the
steps and reduces jitter.

But why do the sine lookup? Why not use the phase accumulator MSBs
directly and get a sawtooth, and filter that?

A saw tooth wave has a huge step like discontinuity in it which looks
very ugly in the frequency domain with strong harmonics. Strong sharp
features in time domain are broad in frequency space and vice versa.

If you wanted something a bit different then detecting the phase
accumulator overflow and reversing the count sense to get a triangle
wave might be an option (at half the frequency). Needs some very careful
maths at the boundary flips to avoid introducing jitter.

From that triangle wave you can use HP\'s wizard diode shaping network
trick to get a pretty good clean sine wave.

Yes, a triangle would be better than a sawtooth... fewer nasty
subharmonics. But we may as well stick with the classic boring sine
wave. The sine lookup is trivial in an FPGA.


A band-limited square wave is pretty space & computation-efficient, you
just store the Gibbs phenomena portion of the wave to whatever harmonic
level you desire, play it back, and then sit there and wait during the
DC parts of the wave.

If you then integrate a band-limited square wave you get a band-limited
triangle wave directly.

If I could make a square wave from the MSBs of the phase accumulator,
I might not need the DAC and filter and comparator.

Just using the MSB of the phase accumulator is the right frequency,
but it\'s very jitterey.

So, is there a way to examine some number of MSBs and make an edge
with high time resolution, all digitally, all inside the FPGA? To even
1 clock resolution, preferably better?

There probably is.




Don\'t think so. Since you have exactly two edges per cycle, it would
have the same problem as the sawtooth, for the same reason. You could
interpolate the same sort of way as in a DDG.

Cheers

Phil Hobbs

If some N bits can be sent to a DAC and a filter, to interpolate to
better time accuracy than just using the MS bit, then the equivalent
interpolation should be possible digitally, inside the FPGA.

We can always spin up a PLL to get as fast a clock as the logic can
stand. And sub-clock tricks have been done.

You still have the giant spike between the actual position of the edge
and where it ought to be for a subharmonic-free signal. That\'s less
than one clock wide, so there\'s no way to get rid of it digitally. You
could maybe do some noise shaping thing to put the subharmonics
someplace else, but unless your increment is a factor of 2**(accumulator
width), they\'ll be there.

A full-width DAC, followed by a brickwall lowpass, followed by a
comparator, will get rid of the subharmonics, as would a ramp/threshold
analog delay calculated on a per-cycle basis.

Cheers

Phil Hobbs

We could take the phase accumulator \"dac\" MSBs and stuff them into a
brickwall digital lowpass filter, maybe even do the sine mapping
first. The result would be a wide smooth waveform, similar to what the
analog comparator would see, only digital. The zero cross of that
would be our \"DDS comparator output\" clock, to one system clock
quantization. Going to half clock resolution wouldn\'t be hard.

If the phase accumulator clock is 160 MHz, half a clock gives us 3 ns
p-p jitter, and the RMS jitter is 900 ps. (Why square root of 12? We
live in a strange universe.)

That filter logic could be clocked faster than the phase accumulator
clock too. Some crazy PLL rate.

I don\'t want to drive a bunch of 20-bit parallel DACs, or make some
13-pole LC filters, but bits are cheap inside an FPGA.

We know what the output frequency will be, so the digital filter can
be tuned for that. Maybe a narrow bandpass? Kills subharmonics?

Some truly terrible things have been done in FPGAs to get picosecond
resolution delays and time interval measuring.

Sounds like a good senior project.



If the output frequency is known in advance, all ought to be
straightforward—pick a clock frequency that’s an integer multiple.

One VCXO-based PLL should be able to make that.

Cheers

Phil Hobbs

The gadget\'s output frequency is known when the user programs it, not
years in advance. When we know the frequency we have to do the math to
program the Fset register over our octave range, and program a
downstream divisor (for, say, a 12 Hz trigger rate) so we have time to
program a digital filter too.

An 8-bit R-2R network and a modest LC filter and an LVDS buffer as a
comparator isn\'t awful, but getting the entire DDS system inside the
FPGA would be cool.

I did consider having a fixed frequency clock and a divisor as our
internal trigger source, and telling the user he has to live with
Fxo/N as the possible choices, but even I have my limits of tackiness.

The difference between adjacent magic increments isn’t that large, at least
at lowish frequencies. It might well be possible to dork the clock to get
to the nearest one.

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs Principal Consultant ElectroOptical Innovations LLC /
Hobbs ElectroOptics Optics, Electro-optics, Photonics, Analog Electronics

 

[piglet]

Phil Hobbs <pcdhSpamMeSenseless@electrooptical.net> wrote:

john larkin <jl@glen--canyon.com> wrote:
On Thu, 8 May 2025 22:28:40 -0000 (UTC), Phil Hobbs
pcdhSpamMeSenseless@electrooptical.net> wrote:

john larkin <jl@glen--canyon.com> wrote:
On Thu, 8 May 2025 16:24:29 -0400, Phil Hobbs
pcdhSpamMeSenseless@electrooptical.net> wrote:

On 2025-05-08 14:58, john larkin wrote:
On Thu, 8 May 2025 14:20:21 -0400, Phil Hobbs
pcdhSpamMeSenseless@electrooptical.net> wrote:

On 2025-05-07 22:21, john larkin wrote:
On Wed, 7 May 2025 20:27:58 -0400, bitrex <user@example.net> wrote:

On 5/7/2025 4:01 PM, john larkin wrote:
On Wed, 7 May 2025 20:32:41 +0100, Martin Brown
\'\'\'newspam\'\'\'@nonad.co.uk> wrote:

On 06/05/2025 16:48, john larkin wrote:
A DDS clock generator uses an NCO (a phase accumulator) and takes some
number of MSBs, maps through a sine lookup table, drives a DAC and a
lowpass filter and finally a comparator. The DAC output gets pretty
ratty near Nyquist, and the filter smooths out and interpolates the
steps and reduces jitter.

But why do the sine lookup? Why not use the phase accumulator MSBs
directly and get a sawtooth, and filter that?

A saw tooth wave has a huge step like discontinuity in it which looks
very ugly in the frequency domain with strong harmonics. Strong sharp
features in time domain are broad in frequency space and vice versa.

If you wanted something a bit different then detecting the phase
accumulator overflow and reversing the count sense to get a triangle
wave might be an option (at half the frequency). Needs some very careful
maths at the boundary flips to avoid introducing jitter.

From that triangle wave you can use HP\'s wizard diode shaping network
trick to get a pretty good clean sine wave.

Yes, a triangle would be better than a sawtooth... fewer nasty
subharmonics. But we may as well stick with the classic boring sine
wave. The sine lookup is trivial in an FPGA.


A band-limited square wave is pretty space & computation-efficient, you
just store the Gibbs phenomena portion of the wave to whatever harmonic
level you desire, play it back, and then sit there and wait during the
DC parts of the wave.

If you then integrate a band-limited square wave you get a band-limited
triangle wave directly.

If I could make a square wave from the MSBs of the phase accumulator,
I might not need the DAC and filter and comparator.

Just using the MSB of the phase accumulator is the right frequency,
but it\'s very jitterey.

So, is there a way to examine some number of MSBs and make an edge
with high time resolution, all digitally, all inside the FPGA? To even
1 clock resolution, preferably better?

There probably is.




Don\'t think so. Since you have exactly two edges per cycle, it would
have the same problem as the sawtooth, for the same reason. You could
interpolate the same sort of way as in a DDG.

Cheers

Phil Hobbs

If some N bits can be sent to a DAC and a filter, to interpolate to
better time accuracy than just using the MS bit, then the equivalent
interpolation should be possible digitally, inside the FPGA.

We can always spin up a PLL to get as fast a clock as the logic can
stand. And sub-clock tricks have been done.

You still have the giant spike between the actual position of the edge
and where it ought to be for a subharmonic-free signal. That\'s less
than one clock wide, so there\'s no way to get rid of it digitally. You
could maybe do some noise shaping thing to put the subharmonics
someplace else, but unless your increment is a factor of 2**(accumulator
width), they\'ll be there.

A full-width DAC, followed by a brickwall lowpass, followed by a
comparator, will get rid of the subharmonics, as would a ramp/threshold
analog delay calculated on a per-cycle basis.

Cheers

Phil Hobbs

We could take the phase accumulator \"dac\" MSBs and stuff them into a
brickwall digital lowpass filter, maybe even do the sine mapping
first. The result would be a wide smooth waveform, similar to what the
analog comparator would see, only digital. The zero cross of that
would be our \"DDS comparator output\" clock, to one system clock
quantization. Going to half clock resolution wouldn\'t be hard.

If the phase accumulator clock is 160 MHz, half a clock gives us 3 ns
p-p jitter, and the RMS jitter is 900 ps. (Why square root of 12? We
live in a strange universe.)

That filter logic could be clocked faster than the phase accumulator
clock too. Some crazy PLL rate.

I don\'t want to drive a bunch of 20-bit parallel DACs, or make some
13-pole LC filters, but bits are cheap inside an FPGA.

We know what the output frequency will be, so the digital filter can
be tuned for that. Maybe a narrow bandpass? Kills subharmonics?

Some truly terrible things have been done in FPGAs to get picosecond
resolution delays and time interval measuring.

Sounds like a good senior project.



If the output frequency is known in advance, all ought to be
straightforward—pick a clock frequency that’s an integer multiple.

One VCXO-based PLL should be able to make that.

Cheers

Phil Hobbs

The gadget\'s output frequency is known when the user programs it, not
years in advance. When we know the frequency we have to do the math to
program the Fset register over our octave range, and program a
downstream divisor (for, say, a 12 Hz trigger rate) so we have time to
program a digital filter too.

An 8-bit R-2R network and a modest LC filter and an LVDS buffer as a
comparator isn\'t awful, but getting the entire DDS system inside the
FPGA would be cool.

I did consider having a fixed frequency clock and a divisor as our
internal trigger source, and telling the user he has to live with
Fxo/N as the possible choices, but even I have my limits of tackiness.





The difference between adjacent magic increments isn’t that large, at least
at lowish frequencies. It might well be possible to dork the clock to get
to the nearest one.

Cheers

Phil Hobbs

Yes. Surely these are lowish frequencies as early on in the discussion JL
said all this was to simulate rotating machines?

--
piglet

 

[Bill Sloman]

On 9/05/2025 8:28 am, Phil Hobbs wrote:

john larkin <jl@glen--canyon.com> wrote:
On Thu, 8 May 2025 16:24:29 -0400, Phil Hobbs
pcdhSpamMeSenseless@electrooptical.net> wrote:

On 2025-05-08 14:58, john larkin wrote:
On Thu, 8 May 2025 14:20:21 -0400, Phil Hobbs
pcdhSpamMeSenseless@electrooptical.net> wrote:

On 2025-05-07 22:21, john larkin wrote:
On Wed, 7 May 2025 20:27:58 -0400, bitrex <user@example.net> wrote:

On 5/7/2025 4:01 PM, john larkin wrote:
On Wed, 7 May 2025 20:32:41 +0100, Martin Brown
\'\'\'newspam\'\'\'@nonad.co.uk> wrote:

On 06/05/2025 16:48, john larkin wrote:


If the output frequency is known in advance, all ought to be
straightforward—pick a clock frequency that’s an integer multiple.

One VCXO-based PLL should be able to make that.

You can\'t pull a VCXO all that far

https://www.analog.com/en/resources/technical-articles/using-a-vcxo-voltagecontrolled-crystal-oscillator-as-a-clock-clk-generator.html

says in the range +/-100ppm to +/-200ppm. That implies having a VCXO
clock running about 10,000 times faster than the output frequency you
are trying to generate.

There\'s going to be a tolerance on the VCXO centre frequency as well.
which isn\'t gong to help.

There\'s a reason why Direct Digital Synthesis is popular - it does
finesse a lot of awkward problems.

--
Bill Sloman, Sydney