DC transformer

On Mon, 21 Oct 2019 02:12:01 -0700 (PDT), Phil Allison
<pallison49@gmail.com> wrote:

jla...@highlandsniptechnology.com wrote:

--------------------------------------


Not relevant in this instance.

It might be to people who actually design electronics.
?


** Try getting JL to explain just what HE thinks that means.

Cos he has very weird ideas on the topic.

By design and years of refinement [1]. If you have a lot of ideas,
many will be weird. And many of the goofy ideas, properly played with,
can become good ideas.

Give ideas a chance. Don't kill them just because they are ugly
infants.


[1] nice concept, refining chaos.

You know, people who aren't hostile to having ideas.


** Who's ideas are they ?

JL's or other peoples ??

When brainstorming for ideas, it's best to not assign credit or blame.
Just let it happen.

IME, here and elsewhere over the last 50 years, electronics designers are the most HOLSTILE group that exists when it comes to any idea THEY did not come up with.

That rigid attitude (well, they may allow textbooks) is poisonous to
creative design. Ideas need to be played with.

Cos they are SUCH ginormous egomaniacs and colossal bullshitters.

Some, but some engineers are brilliant.

Never met or heard of a genuinely modest one.

That is not a requirement for designing great stuff.

Don't exist.

FYI:

Rowan Atkinson ( comedian & EE ) commented very pointedly that:

" Electronics Engineers are THE the most obnoxious people on earth "

Not by far. Consider lawyers and politicians. But many EEs are not
very social. There are certainly autistic trends.

I've noticed that many EEs are OK 1-on-1 but need to perform when in a
group, especially if management is present.

I guess that behavior isn't unique to EEs.

"comedian & EE" is a contradiction right there. Comedians manipulate
people, EEs manipulate things.



--

John Larkin Highland Technology, Inc

lunatic fringe electronics

 

[John Larkin]

On Sun, 20 Oct 2019 15:36:25 +0000 (UTC),
DecadentLinuxUserNumeroUno@decadence.org wrote:

Winfield Hill <winfieldhill@yahoo.com> wrote in
news:qohta001j9c@drn.newsguy.com:

edward.ming.lee@gmail.com wrote...

On Sunday, October 20, 2019 at 12:57:39 AM UTC-7, Piotr Wyderski
wrote:
www.paytongroup.com/webfiles/files/OTS350.pdf

Read carefully. It seems I have always underestimated the
technological progress...

Best regards, Piotr

I think they forgot the "m". 350mW?

No, the largest type are 350W max, but only with
a heat sink (PCB with Aluminum substrate). That
one has two "planar" PCBs with the turns. The
smallest 40W version has only one PCB with both
primary and secondary turns. Payton calls them
planar, even tho they mount above your PCB, 14mm
high in the case of the 350-watt version.



'Planar' in transformer nomenclature, used to refer to how the
winding is arrayed. Not so much 'co-planar' to the PCB, but each
turn in the same plane.

The flat turns reduce skin loss, and some air can get in there to cool
the windings.


--

John Larkin Highland Technology, Inc
picosecond timing precision measurement

jlarkin att highlandtechnology dott com
http://www.highlandtechnology.com

 

[Tim Williams]

"Bill Sloman" <bill.sloman@ieee.org> wrote in message
news:ea02381f-7c58-420d-88f7-04e712b4922e@googlegroups.com...

Perhaps. I spent half an hour at a trade show some years ago talking to a
printed circuit guy who specialised in the business, and a couple of years
ago we had thread here about a similar sort of firm. They could get the
copper layer thicker than the substrate.

It's certainly going to worth talking to somebody like that.
>

Wonder if it's more of a potting operation than lamination -- or if the
result simply has voids; give or take what spec you order?

You can of course get more copper density within a given layer, by using
wide traces, but you can't fill in those gaps with regular prepreg of
inferior thickness.

Typical dimensions might be, like...

2oz/layer: ~2.8 mil copper, 7-10 mil prepreg. Fills in fine. Trace
width/space minimum about 7 mils (some 8 or 10, some down to 5 or 4).
Meager winding factor (~15%).

Heavy copper, say 12oz/layer: ~20 mil copper. 5-10 mil prepreg is just
going to sit on top of it. Can't deposit copper that heavy on a flimsy
core, either (so at least one dielectric layer has to be thicker).
Apparently they need closer to 20 mil (as finished?) prepreg to fill in the
gaps (and it's probably high-resin% prepreg at that?). Width/space about 30
mils, so you can't get many turns in a given area (should you happen to need
them). Result, still a meager winding factor (~20%?).

But yeah, if someone can do thin prepreg + fill, and someone else can do
vertical sidewalls (Lintek comes to mind?), the fill rate could get pretty
amazing.

Actually that's even a bit concerning, simply because all the facing area
(edges between adjacent turns), and the sharp corners, are going to make for
wicked eddy currents / skin / proximity effect (whatever, all basically the
same jumble of up-close AC effects).

I know! Bring back that laminated-wire-PCB technology and make printed litz
windings! :^)

Tim

--
Seven Transistor Labs, LLC
Electrical Engineering Consultation and Design
Website: https://www.seventransistorlabs.com/

 

[Bill Sloman]

On Tuesday, October 22, 2019 at 3:27:49 AM UTC+11, jla...@highlandsniptechnology.com wrote:

On Mon, 21 Oct 2019 02:12:01 -0700 (PDT), Phil Allison
pallison49@gmail.com> wrote:

jla...@highlandsniptechnology.com wrote:

--------------------------------------


Not relevant in this instance.

It might be to people who actually design electronics.
?

** Try getting JL to explain just what HE thinks that means.

Cos he has very weird ideas on the topic.

By design and years of refinement [1].

It's John's ideas about what constitutes design that are weird.

His unwillingess to put in the effort required to design special-purpose transformers, ostensibly because it take extra effort to find somebody to make them. are even weirder.

The "years of refinement" seem to have been devoted to find ever-better excuses for avoiding ding anything demanding.

If you have a lot of ideas,
many will be weird. And many of the goofy ideas, properly played with,
can become good ideas.

Give ideas a chance. Don't kill them just because they are ugly
infants.

[1] nice concept, refining chaos.

Charles Darwin and Alfred Wallace has the same idea some 150 years ago. John Larkin doesn't seem to have taken it on board yet.

You know, people who aren't hostile to having ideas.

** Who's ideas are they ?

JL's or other peoples ??

When brainstorming for ideas, it's best to not assign credit or blame.
Just let it happen.

Sadly, if there's an egomaniac in the group, what happens is that he talks too much.

IME, here and elsewhere over the last 50 years, electronics designers are the most HOLSTILE group that exists when it comes to any idea THEY did not come up with.

That rigid attitude (well, they may allow textbooks) is poisonous to
creative design. Ideas need to be played with.

But the father of the idea tends to be a very indulgent parent.

Cos they are SUCH ginormous egomaniacs and colossal bullshitters.

Some, but some engineers are brilliant.

Rather fewer than those who think they are.

Never met or heard of a genuinely modest one.

That is not a requirement for designing great stuff.

It tends to be a requirement for getting complicated great stuff together. Modest people tend to work together better.

Don't exist.

FYI:

Rowan Atkinson ( comedian & EE ) commented very pointedly that:

" Electronics Engineers are THE the most obnoxious people on earth "

Not by far. Consider lawyers and politicians. But many EEs are not
very social. There are certainly autistic trends.

Autism is a mental disease. There are pop-psychologists who like to see the normal range - from extravert to introvert - as tacked onto the the autism spectrum. This is decidedly unhelpful

I've noticed that many EEs are OK 1-on-1 but need to perform when in a
group, especially if management is present.

I guess that behavior isn't unique to EEs.

"comedian & EE" is a contradiction right there. Comedians manipulate
people, EEs manipulate things.

Then Rowan Atkinson doesn't exist. Getting people to laugh may be "manipulating them" but so is getting them to vote for you, or getting them to invest in a business project that you have thought up, or even persuading them that a particular electronic device can work.

The techniques involved can vary - EE's really can't afford to lie because their claims are more testable than most - but it's all manipulation.

--
Bill Sloman, Sydney

 

On Monday, 21 October 2019 17:27:49 UTC+1, jla...@highlandsniptechnology.com wrote:

On Mon, 21 Oct 2019 02:12:01 -0700 (PDT), Phil Allison
pallison49@gmail.com> wrote:
jla...@highlandsniptechnology.com wrote:

** Try getting JL to explain just what HE thinks that means.

Cos he has very weird ideas on the topic.

By design and years of refinement [1]. If you have a lot of ideas,
many will be weird. And many of the goofy ideas, properly played with,
can become good ideas.

Give ideas a chance. Don't kill them just because they are ugly
infants.


[1] nice concept, refining chaos.

+1 on both points. One has to understand that to develop new technology. Without that realisation the progress made will always be limited & incremental only.

IME, here and elsewhere over the last 50 years, electronics designers are the most HOLSTILE group that exists when it comes to any idea THEY did not come up with.

That rigid attitude (well, they may allow textbooks) is poisonous to
creative design. Ideas need to be played with.

Yup. Turns out that's harder than expected. When still a student I presented something I'd already used as an idea in brainstorming, and the universal reaction was it write it off as useless, despite it being a winner in the real world. Never underestimate gimmicks.

Cos they are SUCH ginormous egomaniacs and colossal bullshitters.

Some, but some engineers are brilliant.

One thing I like about dealing with engineers of any kind is they're far less prone to bs than the rest of the world. That does not make everyone immune to it though.

Never met or heard of a genuinely modest one.

That is not a requirement for designing great stuff.

If you design stuff that beats whats already out there, it doesn't tend to result in, what's the word, seeing oneself as always incapable, ignorant.

"comedian & EE" is a contradiction right there. Comedians manipulate
people, EEs manipulate things.

That's so not true. EEs play with circuit ideas, comedians play with concepts - plenty of overlap.


NT

 

[Winfield Hill]

klaus.kragelund@gmail.com wrote...

http://www.paytongroup.com/webfiles/files/5%20Up%20to%20350W%20SMT%20Standard%20transformers.pdf

They call these SMT transformers, but they
should call them low-voltage transformers,
because both input and output voltages are
so low, probably limited by low turns count.


--
Thanks,
- Win

 

On Tuesday, 22 October 2019 09:48:23 UTC+2, klaus.k...@gmail.com wrote:

On Tuesday, 22 October 2019 02:24:07 UTC+2, Tim Williams wrote:
"Bill Sloman" <bill.sloman@ieee.org> wrote in message
news:ea02381f-7c58-420d-88f7-04e712b4922e@googlegroups.com...
Perhaps. I spent half an hour at a trade show some years ago talking to a
printed circuit guy who specialised in the business, and a couple of years
ago we had thread here about a similar sort of firm. They could get the
copper layer thicker than the substrate.

It's certainly going to worth talking to somebody like that.


Wonder if it's more of a potting operation than lamination -- or if the
result simply has voids; give or take what spec you order?

At that power level it is more likely to be copper sheets, with a lacquer layer.

This datasheet for the same part, looks like copper sheets:

https://www.edn.com/design-ideas/all

Cheers

Klaus

Crap, wrong link. Right link:

http://www.paytongroup.com/webfiles/files/5%20Up%20to%20350W%20SMT%20Standard%20transformers.pdf

 

On Tuesday, 22 October 2019 02:24:07 UTC+2, Tim Williams wrote:

"Bill Sloman" <bill.sloman@ieee.org> wrote in message
news:ea02381f-7c58-420d-88f7-04e712b4922e@googlegroups.com...
Perhaps. I spent half an hour at a trade show some years ago talking to a
printed circuit guy who specialised in the business, and a couple of years
ago we had thread here about a similar sort of firm. They could get the
copper layer thicker than the substrate.

It's certainly going to worth talking to somebody like that.


Wonder if it's more of a potting operation than lamination -- or if the
result simply has voids; give or take what spec you order?

At that power level it is more likely to be copper sheets, with a lacquer layer.

This datasheet for the same part, looks like copper sheets:

https://www.edn.com/design-ideas/all

Cheers

Klaus

 

On Tue, 22 Oct 2019 01:13:37 -0700 (PDT), tabbypurr@gmail.com wrote:

On Monday, 21 October 2019 17:27:49 UTC+1, jla...@highlandsniptechnology.com wrote:
On Mon, 21 Oct 2019 02:12:01 -0700 (PDT), Phil Allison
pallison49@gmail.com> wrote:
jla...@highlandsniptechnology.com wrote:

** Try getting JL to explain just what HE thinks that means.

Cos he has very weird ideas on the topic.

By design and years of refinement [1]. If you have a lot of ideas,
many will be weird. And many of the goofy ideas, properly played with,
can become good ideas.

Give ideas a chance. Don't kill them just because they are ugly
infants.


[1] nice concept, refining chaos.

+1 on both points. One has to understand that to develop new technology. Without that realisation the progress made will always be limited & incremental only.


IME, here and elsewhere over the last 50 years, electronics designers are the most HOLSTILE group that exists when it comes to any idea THEY did not come up with.

That rigid attitude (well, they may allow textbooks) is poisonous to
creative design. Ideas need to be played with.

Yup. Turns out that's harder than expected. When still a student I presented something I'd already used as an idea in brainstorming, and the universal reaction was it write it off as useless, despite it being a winner in the real world. Never underestimate gimmicks.


Cos they are SUCH ginormous egomaniacs and colossal bullshitters.

Some, but some engineers are brilliant.

One thing I like about dealing with engineers of any kind is they're far less prone to bs than the rest of the world. That does not make everyone immune to it though.


Never met or heard of a genuinely modest one.

That is not a requirement for designing great stuff.

If you design stuff that beats whats already out there, it doesn't tend to result in, what's the word, seeing oneself as always incapable, ignorant.


"comedian & EE" is a contradiction right there. Comedians manipulate
people, EEs manipulate things.

That's so not true. EEs play with circuit ideas, comedians play with concepts - plenty of overlap.


NT

He's probably not a very good EE.



--

John Larkin Highland Technology, Inc

lunatic fringe electronics

 

On Mon, 21 Oct 2019 04:13:24 -0500, "Tim Williams"
<tiwill@seventransistorlabs.com> wrote:

"Bill Sloman" <bill.sloman@ieee.org> wrote in message
news:8a9a70b7-a792-4184-a737-f234ea77dee6@googlegroups.com...

You do need to go to a specialist printed circuit board shop if you want
to do it right. It needs a lot layers of of thin substrate and some very
thick copper winding tracks if you want to fill even half of the winding
window with copper.

The outer layers can get by thinner copper (which does allows narrower
tracks).


Half!? Impossible from any fab I'm aware of. Fortunately the winding
length is short and the heat transfer is good, so it's not a big deal to use
high current density. 10% winding factor is good when you're talking
planars, and it's really not very different from say a toroid winding, which
has similar aspect ratios.

Tim

Here's one of my inductors, hand-wound from #14 magnet wire on a
Sharpie, heat sunk to the PCB hence the cold plate below.

https://www.dropbox.com/s/lmkj7tavf2ou77t/L1C.JPG?raw=1

Given the RMS current, that wire size seems entirely unjustified. It
needs the surface area to reduce skin loss and get rid of heat. The
coil spacing reduces proximity effect and further helps cooling.

Now I'm thinking that this could be a "planar", namely PCB-based,
inductor. Better cooling, less skin loss per pound of copper, saves
wear and tear on Sharpies.




--

John Larkin Highland Technology, Inc

lunatic fringe electronics

 

On Mon, 21 Oct 2019 19:24:37 -0500, "Tim Williams"
<tiwill@seventransistorlabs.com> wrote:

"Bill Sloman" <bill.sloman@ieee.org> wrote in message
news:ea02381f-7c58-420d-88f7-04e712b4922e@googlegroups.com...
Perhaps. I spent half an hour at a trade show some years ago talking to a
printed circuit guy who specialised in the business, and a couple of years
ago we had thread here about a similar sort of firm. They could get the
copper layer thicker than the substrate.

It's certainly going to worth talking to somebody like that.


Wonder if it's more of a potting operation than lamination -- or if the
result simply has voids; give or take what spec you order?

You can of course get more copper density within a given layer, by using
wide traces, but you can't fill in those gaps with regular prepreg of
inferior thickness.

Typical dimensions might be, like...

2oz/layer: ~2.8 mil copper, 7-10 mil prepreg. Fills in fine. Trace
width/space minimum about 7 mils (some 8 or 10, some down to 5 or 4).
Meager winding factor (~15%).

Heavy copper, say 12oz/layer: ~20 mil copper. 5-10 mil prepreg is just
going to sit on top of it. Can't deposit copper that heavy on a flimsy
core, either (so at least one dielectric layer has to be thicker).
Apparently they need closer to 20 mil (as finished?) prepreg to fill in the
gaps (and it's probably high-resin% prepreg at that?). Width/space about 30
mils, so you can't get many turns in a given area (should you happen to need
them). Result, still a meager winding factor (~20%?).

But yeah, if someone can do thin prepreg + fill, and someone else can do
vertical sidewalls (Lintek comes to mind?), the fill rate could get pretty
amazing.

Actually that's even a bit concerning, simply because all the facing area
(edges between adjacent turns), and the sharp corners, are going to make for
wicked eddy currents / skin / proximity effect (whatever, all basically the
same jumble of up-close AC effects).

I know! Bring back that laminated-wire-PCB technology and make printed litz
windings! :^)

Tim

As switcher frequency goes up, skin depth starts to make extra-thick
copper not worthwhile. Very roughly, 2 oz copper is good enough around
1 or 2 MHz sinewave. For switcher waveforms, the tradeoff further
favors not wasting copper.

Exotic PCB material probably doesn't help much. The main cooling is
air at the surface. [1]

I'm guessing that adding more loops on more internal layers doesn't
help. There's basically no cooling, and proximity effect will be
serious. It might help if you need a lot of inductance.

[1] how about a rising-sun copper pattern on some inner layers, to
conduct heat out?



--

John Larkin Highland Technology, Inc

lunatic fringe electronics

 

On Tue, 22 Oct 2019 17:57:00 +0200, Piotr Wyderski
<peter.pan@neverland.mil> wrote:

jlarkin@highlandsniptechnology.com wrote:

Here's one of my inductors, hand-wound from #14 magnet wire on a
Sharpie, heat sunk to the PCB hence the cold plate below.

https://www.dropbox.com/s/lmkj7tavf2ou77t/L1C.JPG?raw=1

What exactly is that thermal goo? I think I may need something like that
in my recent project.

Best regards, Piotr

It's a soft sheet material,

3GSHIELDING TW-T600-2MM

It feels like used chewing gum. Compress it to about half its nominal
thickness for good heat transfer. Use thinner stuff if you can. I have
high voltages so went with the 2 mm thickness.

Ask for a sample. They are good about that.

I use biggish pads of that between my PCB and the cold plate, and a
scrap between the inductor and the PCB. Thermal vias conduct the heat
from the inductor to the bottom of the board, then another pad below
to the cold plate.

https://www.dropbox.com/s/6g80f5yw695e8ah/Baseplate.jpg?raw=1



--

John Larkin Highland Technology, Inc

lunatic fringe electronics

 

[Piotr Wyderski]

jlarkin@highlandsniptechnology.com wrote:

Here's one of my inductors, hand-wound from #14 magnet wire on a
Sharpie, heat sunk to the PCB hence the cold plate below.

https://www.dropbox.com/s/lmkj7tavf2ou77t/L1C.JPG?raw=1

What exactly is that thermal goo? I think I may need something like that
in my recent project.

Best regards, Piotr

 

[Piotr Wyderski]

Tim Williams wrote:

I know!  Bring back that laminated-wire-PCB technology and make printed
litz windings! :^)

Maybe not a litz, but I am sure it would be possible to get a really
decent interleaving. Pity the PWB technology is so dead... :-/

Best regards, Piotr

 

[John Larkin]

On Tue, 22 Oct 2019 17:47:27 +0200, Piotr Wyderski
<peter.pan@neverland.mil> wrote:

Tim Williams wrote:

I know!  Bring back that laminated-wire-PCB technology and make printed
litz windings! :^)

Maybe not a litz, but I am sure it would be possible to get a really
decent interleaving. Pity the PWB technology is so dead... :-/

Best regards, Piotr

PCBs are like piston engines, very old but still the best way so far.

--

John Larkin Highland Technology, Inc
picosecond timing precision measurement

jlarkin att highlandtechnology dott com
http://www.highlandtechnology.com

 

[Tim Williams]

<jlarkin@highlandsniptechnology.com> wrote in message
news:ne6uqehg85l32a69aphqvdl88eo0itiftp@4ax.com...

Now I'm thinking that this could be a "planar", namely PCB-based,
inductor. Better cooling, less skin loss per pound of copper, saves
wear and tear on Sharpies.

Playing with this lately,
https://www.seventransistorlabs.com/Images/ResonantGateDriver.jpg
note the planar coil L1 with the red coil above it. Currently L1 is cut out
of circuit to try a high Q coil.

The small-signal measurement of L1 shows a rather poor Q of 14 (at 3.5MHz),
which would account for about a watt at the ~15VA I'm throwing at it
(depending on operating point). Efficiency seems similar with the good coil
though.

The biggest single loss seems to be the >1W burned purely in gate drive, a
combination of the LDO supplying it and the MOSFET's ~15nC gate charge being
driven at 3MHz. I should've given that a double-check and went straight to
GaN instead. (Which can pretty much drop in, too, since the gate drive is
only 6V. Swap the 78L06 --> 78L05 and there we go. Shame about the GaN
footprints being different.)

Looks like this in the CAD,
https://www.seventransistorlabs.com/Images/PlanarInductor4t.png
4 layers, 2oz, and, think it was something like 15-20-15 mil dielectric
stackup (62 mil overall). So it's very much like one of those edge-wound
flat wire inductors you see so often, sans core.

The transformer does very nicely, seems less core loss than I designed it
based on. 3F46 material.

It's too bad there's no high frequency (>1MHz) resonant controllers out
there yet, all that area (the discretes) would be easy to save.

Tim

--
Seven Transistor Labs, LLC
Electrical Engineering Consultation and Design
Website: https://www.seventransistorlabs.com/

 

[Winfield Hill]

Tim Williams wrote...

Playing with this lately,
https://www.seventransistorlabs.com/Images/ResonantGateDriver.jpg
note the planar coil L1 with the red coil above it.
Currently L1 is cut out of circuit to try a high Q coil.

Can you show us the schematic? How did you pick 3MHz?


--
Thanks,
- Win

 

[Piotr Wyderski]

Tim Williams wrote:

> https://www.seventransistorlabs.com/Images/PlanarInductor4t.png

This layout is a beauty. Is a single VIA sufficient?

4 layers, 2oz, and, think it was something like 15-20-15 mil dielectric
stackup (62 mil overall).  So it's very much like one of those
edge-wound flat wire inductors you see so often, sans core.

Why "very much like"? Those are 1mm thick or more, so the 2oz does not
even come close. Or do you mean the entire stackup?

Anyways, I like it.

Best regards, Piotr

 

[Piotr Wyderski]

John Larkin wrote:

> PCBs are like piston engines, very old but still the best way so far.

They are most cost-effective and very repeatable, but "best" in purely
technical terms -- no, I don't think so. The limitations imposed by this
technology are severe.

Kind of the best description of socialism I know of: a system bravely
fighting problems unknown in other systems. Exactly the same with the PCBs.

Best regards, Piotr

 

[Tim Williams]

"Winfield Hill" <winfieldhill@yahoo.com> wrote in message
news:qonsm301fq4@drn.newsguy.com...

Tim Williams wrote...

Playing with this lately,
https://www.seventransistorlabs.com/Images/ResonantGateDriver.jpg
note the planar coil L1 with the red coil above it.
Currently L1 is cut out of circuit to try a high Q coil.

Can you show us the schematic? How did you pick 3MHz?

Uh, sure what the hell--
https://www.seventransistorlabs.com/Images/ResonantSupplySch.png
Some component values changed since proto testing, of course it's an
exercise for the student to find out which ones. :^)

L2 is only there because the planar core isn't gapped, of course (Np = 2t,
Lp = 2.7uH).

Really I just wanted to use the ELP14 because I had already made some
footprints, and I wanted to push up to 15V out of them (3V/turn). For a
total 30V output (full wave doubler). Which comes to something like 2MHz
for comfortable core loss. Although because of economy of scale, I could
push the core loss quite a bit higher: 1MHz or even maybe 500kHz would be
reasonable, which is within reach of many controllers/regulators, no need
for custom.

As mentioned, pushing silicon quite this fast is something of a mistake, but
GaN would drop in with little change, giving a significant boost in
efficiency.

Which by the way, is only about 70% here, rather embarassing for a resonant
converter. :^)

Controller behavior is roughly based on L6599 which I did a project with
earlier this year; I think I get the idea. Resonant control may seem
intimidating, but I think because controlling it precisely would be both
very intensive (e.g., state space control?), and not very useful at that
(the Q is low so the feedback doesn't need to be very gradual; except when
it is, but *hand waving*), they usually settle for a simple burst mode with
CW operation under heavy loads.

Main difference here being, I didn't opt for the 74HC74 to latch the enable,
so it just starts and stops whenever, gladly making runt pulses. Likely far
from optimal, but it's under light load at the same time too, so... meh?

Oh hm, I should feed in a bit of CLK to the comparator so it gets injection
locked, duh. That'll solve that...

Tim

--
Seven Transistor Labs, LLC
Electrical Engineering Consultation and Design
Website: https://www.seventransistorlabs.com/