DC fifo behaviour at underflow/overflow

[Michael S]

On Dec 17, 11:17 am, "kaz" <3619@embeddedrelated> wrote:

On Dec 16, 3:57=A0pm, "kaz" <3619@embeddedrelated> wrote:
Yes there is extra term.
Here is some excerpt:

TX_SRX_FIFO_inst : TX_SRX_FIFO
=A0 PORT MAP (
=A0 =A0 data =A0 =A0 =3D> TX_SRX_FIFO_DATA,
=A0 =A0 rdclk =A0 =A0=3D> iCLK245,
=A0 =A0 rdreq =A0 =A0=3D> TX_SRX_FIFO_rdreq,
=A0 =A0 wrclk =A0 =A0=3D> iCLK368,
=A0 =A0 wrreq =A0 =A0=3D> TX_SRX_FIFO_wrreq,
=A0 =A0 q =A0 =A0 =A0 =A0=3D> TX_SRX_FIFO_q,
=A0 =A0 rdempty =A0=3D> TX_SRX_FIFO_empty,
=A0 =A0 wrfull =A0 =3D> TX_SRX_FIFO_full
=A0 =A0 );

=A0 =A0 -- 2 in 3 clock enables is used
=A0 =A0 TX_SRX_FIFO_wrreq <=3D (Sync_23_1b(1) AND (not

TX_SRX_FIFO_full))
;
=A0 =A0 TX_SRX_FIFO_rdreq <=3D not TX_SRX_FIFO_empty;

Hi Michael,

below is definition of fifo.
What troubles me is that write/read are tied up to full/empty respectively
so I don't see why flow problems should occur. Moreover the write/read is
protected internally as well.

Could you also please let me know was it timing simulation that you did?

I disabled built-in protections and forcefully overwrote protections
in user logic.

rdreq <= (not rdempty or force1_rdreq) and not force0_rdreq;
wrreq <= ((not wrfull and (not xx(1))) or force1_wrreq) and not
force0_wrreq;

Thanks

LIBRARY ieee;
USE ieee.std_logic_1164.all;

LIBRARY altera_mf;
USE altera_mf.all;

ENTITY TX_SRX_FIFO IS
        PORT    (
                data            : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
                rdclk           : IN STD_LOGIC ;
                rdreq           : IN STD_LOGIC ;
                wrclk           : IN STD_LOGIC ;
                wrreq           : IN STD_LOGIC ;
                q               : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
                rdempty         : OUT STD_LOGIC ;
                wrfull          : OUT STD_LOGIC
        );
END TX_SRX_FIFO;

ARCHITECTURE SYN OF tx_srx_fifo IS

        SIGNAL sub_wire0        : STD_LOGIC ;
        SIGNAL sub_wire1        : STD_LOGIC ;
        SIGNAL sub_wire2        : STD_LOGIC_VECTOR (31 DOWNTO 0);

        COMPONENT dcfifo
        GENERIC (
                intended_device_family  : STRING;
                lpm_numwords            : NATURAL;
                lpm_showahead           : STRING;
                lpm_type                : STRING;
                lpm_width               : NATURAL;
                lpm_widthu              : NATURAL;
                overflow_checking       : STRING;
                rdsync_delaypipe        : NATURAL;
                underflow_checking      : STRING;
                use_eab                 : STRING;
                wrsync_delaypipe        : NATURAL
        );
        PORT (
                        wrclk   : IN STD_LOGIC ;
                        rdempty : OUT STD_LOGIC ;
                        rdreq   : IN STD_LOGIC ;
                        wrfull  : OUT STD_LOGIC ;
                        rdclk   : IN STD_LOGIC ;
                        q       : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
                        wrreq   : IN STD_LOGIC ;
                        data    : IN STD_LOGIC_VECTOR (31 DOWNTO 0)
        );
        END COMPONENT;

BEGIN
        rdempty    <= sub_wire0;
        wrfull    <= sub_wire1;
        q    <= sub_wire2(31 DOWNTO 0);

        dcfifo_component : dcfifo
        GENERIC MAP (
                intended_device_family => "Stratix IV",
                lpm_numwords => 8,
                lpm_showahead => "OFF",
                lpm_type => "dcfifo",
                lpm_width => 32,
                lpm_widthu => 3,
                overflow_checking => "ON",
                rdsync_delaypipe => 5,
                underflow_checking => "ON",
                use_eab => "ON",
                wrsync_delaypipe => 5
        )
        PORT MAP (
                wrclk => wrclk,
                rdreq => rdreq,
                rdclk => rdclk,
                wrreq => wrreq,
                data => data,
                rdempty => sub_wire0,
                wrfull => sub_wire1,
                q => sub_wire2
        );

END SYN;

Kaz

---------------------------------------
Posted throughhttp://www.FPGARelated.com

There is a known bug in Quartus 11.1 that applies to use_eab => "ON".
According to the knowledge base, it was fixed in 11.1SP1.
http://www.altera.com/support/kdb/solutions/rd11182011_10.html

There is another known bug that is not fixed in 11.1SP1/11.1SP2, but
it only applies to use_eab => "OFF" so you shouldn't care about it.

Looking at your parameters, rdsync_delaypipe => 5 and wrsync_delaypipe
=> 5 sound like an overkill.
It's unlikely that value of 5 really improve anything over value of 4.
And if overflow happens nevertheless (don't ask me how, I don't know)
then longer sync pipelines certainly make self-recovery more
difficult.

 

[Michael S]

On Dec 17, 11:17 am, "kaz" <3619@embeddedrelated> wrote:

Could you also please let me know was it timing simulation that you did?

No, I did a functional simulation in Quartus 9.1 internal simulator.
Quartus 9.1 ISIM can't simulate Stratix-IV, so I told him that it is
Cyclone-III. For a functional simulation it should make no difference.