DC Blocker

[Tim Wescott]

On Fri, 23 Oct 2015 02:51:42 -0500, b2508 wrote:

On 10/22/2015 4:50 PM, b2508 wrote:
In article <2Z-dnUTCaKvCqLTLnZ2dnUU7-VOdnZ2d@giganews.com>,
b2508 <108118@FPGARelated> wrote:
Hm.. I tought that multiplication cannot be implemented without
delay.

This could cause timing issues to my knowledge.

Moreover, full formula is

y[n] = Q {x[n] - x[n-1] + p*y[n-1] - e[n-1]}
e[n] = x[n] - x[n-1] + p*y[n-1] - e[n-1] - y[n]

Error is difference between output before and after quantization.
I asked for the initial one because even that i don't know how to
implement.

if x1 appears at t1, corresponding y1 is ready at earlies at
t2=t1+1.
If
I
register subtracting operation as well, e1 is available at t3=t1+1.
However x2 arrives at t2 and neither y1 (corresponding y[n-1]) or e1
are
ready at that time.

Without really looking at your required function in detail (just
noting
that it has feedback terms) - I'll just note in general.

The statement "multiplication cannot be implemented without delay" is
false, in many ways. It all depends on your processing requirements.
What is your sample rate? What are your bit widths?

You're processing clock does NOT need to be the same as your sample
clock.
If you wish them to be the same - it may be easier for new FPGA users
to

design - then you MAY be able to run the multiplier full
combinational
-

If you're sample rate is low enough.

The alternative (at a high level) is to buffer an input and output,
and
process with a faster processing clock. Modern FPGA's these days can
run

DSP functions upwards to around 400-500 MHz. This is likely much
faster

than your sample rate.

Regards,
Mark

OK, I was taught that it is always safer to put registers wherever you
can. I have no choice in my project but to have same sampling and
processing rate.

My rate is 100 MHz.
Input data or x[n] has data format - unsigned, 16 bit, 1 bit for
integer.

Also, I am not sure how to select data widths after each of these
operations.

If x[n] and x[n-1] are 16/1 and their subtraction is 17 bit unsigned
with
2 bit integers, how do I proceed with data width selection? Feedback
loop
part is unclear to me.
Also, should I use DSP48 for the multiplication with P or should I
make
it
somehow power of two and do it by shifting?

Q is quantization, or reducing number of samples after all these
operations.

Do you know the value of P? Multiplies are done by shifting and adding.

I don't know which chip you are planning to use, but all the
multipliers I know of require pipelining, the only option is how many
stages, 1, 2, etc... Since P is a constant (it *is* a constant, right?)

you only need to use adders for the 1s, or if there are long runs of 1s
or 0s, you can subtract at the lsb of the run and add in at the bit just

past the msb of the run. The point is you may not need to use a built
in multiplier.

Your filter seems very complex for a feedback filter. Is there some
special need driving this? Can you use a simpler filter?

--

Rick

I do not really know the value of P or how to determine it. I was
thinking to use 0.99 because I tried it out in software simulation and
it seems to do what I wanted it to do. The idea for this filter came
from this article / second filter on Figure 2.

http://www.digitalsignallabs.com/dcblock.pdf

Someone said to forget equations and do as it is drawn in figure, but
these figures never account for potential latency of the
add/subtract/multiply blocks or if I do not add registers, then I may
have timing issues.

Anyway, I will try to do add and multiply in one clock cycle and see
where this gets me.

So, the set of equations that I suggested elsewhere pretty much implement
what you claim to want, you can use d = 2^-N, which implies a shift, and
-- as I stated -- you can use some delay in the "servo to average value"
step.

So what's your problem again?

Equations reiterated:

u: input
y: output
x: state variable

y[n] = u[n] - x[n-1]
x[n] = d * y[n]

--

Tim Wescott
Wescott Design Services
http://www.wescottdesign.com

 

[Richard Damon]

On 10/23/15 1:11 PM, Tim Wescott wrote:

Equations reiterated:

u: input
y: output
x: state variable

y[n] = u[n] - x[n-1]
x[n] = d * y[n]

Something can't be right with these equations.

Let us say we have had signal for awhile with a DC component.

u[n] now goes to that value.

By definition, y[n] should be 0, and thus so would x[n]

if u[n+1] has that same value again, y[n+1] = u[n+1] and not 0 as required,

The equations I tend to use for something like this is:

y[n]= u[n] = x[n-1]
x[n] = x[n-1] + k*y[n]

(k being some power of 0.5 so the multiply is a shift.)
x often needing additional fractional bits, especially if k is very small.

 

[kaz]

op links to this doc
http://www.digitalsignallabs.com/dcblock.pdf

looking into above document I got a bit curious; to get rid of truncatio
dc
bias why add fraction of truncation when you can just use rounding to
nearest integer or to nearest even.

Kaz

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[Mike Field]

Not knowing your exact requirements, the simplest I can see would be a running average of a large number of samples, and subtract that.

E.g total = total + sample - sample(n-2048), output = sample-total/2048.

The division would be a bit shift, and the 2k of samples could be held in a ram block.

It is pretty trivial to show that DC would be blocked, and signals at f/2048 will not be attenuated (as the average would be zero).

It would also be very fast and have minimal latency, however it would introduce some phase distortion as it isn't symetrical.

If that is an issue for your application, then a way around it would be to total over 2047 samples, and subtract the total from 2047*sample(n-1024), then divide by 2048 (once again this can be implemented with addition, subtraction and bitshifts).
The output will be slightly attenuated (by 1/2048), but no phase distortion would occur. It will also have a latency of 1024 cycles or so.

Mike