dangerous profession...

[Lasse Langwadt Christensen]

fredag den 2. oktober 2020 kl. 23.52.20 UTC+2 skrev Joerg:

On 10/2/20 2:10 PM, Phil Hobbs wrote:
On 2020-10-01 11:39, Joerg wrote:
On 10/1/20 7:45 AM, Three Jeeps wrote:
On Thursday, October 1, 2020 at 1:09:03 AM UTC-4, Joerg wrote:
On 9/30/20 8:46 PM, jla...@highlandsniptechnology.com wrote:

In the last week, I\'ve been burned 6 times, shocked once, punctured
(with blood) twice, and had to eat a single burger for three lunches
in a row. And we are out of ice cream sandwiches.

Could be worse. BE-256 yeast is out of stock everywhere for months
and I
can\'t brew Belgian abbaye ales. That\'s serious!



--
Regards, Joerg

http://www.analogconsultants.com/
https://homebrewsupply.com/fermentis-safbrew-be-256-yeast/


Nine bucks, yikes! Oh well, goes like ammo I guess. A poster in the
brew NG pointed out another place but I found that their BE-256 yeast
was quite old.

Somehow production of this stuff must have stopped.


You can\'t culture your own?

The monks didn\'t buy yeast from Amazon.


Sure you can and I do that to some extent. I harvest yeast from previous
batches. For example, because of BE-256 being expensive and now almost
unobtanium I stagger my Belgian beers. A Paterbier is mild and takes one
pouch. Then I siphon off trub but for more 2x the initial number of
yeast cells. Then I brew a Tripel or Quadrupel which needs a high dose
of yeast. Later I siphon that and make a Porter with it. The rest of the
trub doesn\'t go to waste either because we bake bread with it.

However, so far I\'ve never dared to go past 4th generation with yeast.
Mutations can result in off-flavors or worst case a ruined batch.
Considering that 4-5h of work go into each batch that would not be cool.

yeh, Emil Chr. Hansen at Carlsberg figured that out in 1883

 

[Joerg]

On 10/2/20 3:08 PM, Lasse Langwadt Christensen wrote:

fredag den 2. oktober 2020 kl. 23.52.20 UTC+2 skrev Joerg:
On 10/2/20 2:10 PM, Phil Hobbs wrote:
On 2020-10-01 11:39, Joerg wrote:
On 10/1/20 7:45 AM, Three Jeeps wrote:
On Thursday, October 1, 2020 at 1:09:03 AM UTC-4, Joerg wrote:
On 9/30/20 8:46 PM, jla...@highlandsniptechnology.com wrote:

In the last week, I\'ve been burned 6 times, shocked once, punctured
(with blood) twice, and had to eat a single burger for three lunches
in a row. And we are out of ice cream sandwiches.

Could be worse. BE-256 yeast is out of stock everywhere for months
and I
can\'t brew Belgian abbaye ales. That\'s serious!



--
Regards, Joerg

http://www.analogconsultants.com/
https://homebrewsupply.com/fermentis-safbrew-be-256-yeast/


Nine bucks, yikes! Oh well, goes like ammo I guess. A poster in the
brew NG pointed out another place but I found that their BE-256 yeast
was quite old.

Somehow production of this stuff must have stopped.


You can\'t culture your own?

The monks didn\'t buy yeast from Amazon.


Sure you can and I do that to some extent. I harvest yeast from previous
batches. For example, because of BE-256 being expensive and now almost
unobtanium I stagger my Belgian beers. A Paterbier is mild and takes one
pouch. Then I siphon off trub but for more 2x the initial number of
yeast cells. Then I brew a Tripel or Quadrupel which needs a high dose
of yeast. Later I siphon that and make a Porter with it. The rest of the
trub doesn\'t go to waste either because we bake bread with it.

However, so far I\'ve never dared to go past 4th generation with yeast.
Mutations can result in off-flavors or worst case a ruined batch.
Considering that 4-5h of work go into each batch that would not be cool.

yeh, Emil Chr. Hansen at Carlsberg figured that out in 1883

In the end every brewer has to figure out for himself how to deal with
yeast, hops, temperatures and so on. Given the exact same recipe there
can be significant differences in tase.

--
Regards, Joerg

http://www.analogconsultants.com/

 

[John Larkin]

On Fri, 2 Oct 2020 13:14:58 -0700, Joerg <news@analogconsultants.com>
wrote:

On 10/1/20 9:30 AM, jlarkin@highlandsniptechnology.com wrote:
On Thu, 1 Oct 2020 08:42:40 -0700, Joerg <news@analogconsultants.com
wrote:

On 10/1/20 8:06 AM, jlarkin@highlandsniptechnology.com wrote:
On Wed, 30 Sep 2020 22:08:54 -0700, Joerg <news@analogconsultants.com
wrote:

On 9/30/20 8:46 PM, jlarkin@highlandsniptechnology.com wrote:

In the last week, I\'ve been burned 6 times, shocked once, punctured
(with blood) twice, and had to eat a single burger for three lunches
in a row. And we are out of ice cream sandwiches.


Could be worse. BE-256 yeast is out of stock everywhere for months and I
can\'t brew Belgian abbaye ales. That\'s serious!



Poor baby! That\'s terrible.

The ice cream sandwich shortage is at least as bad. You can apply one
directly to a burn, or eat it, and either way you feel better.

I\'m tuning the tempco of my Colpitts oscillator, which is tucked into
the corner of a tallish enclosure, so it\'s really hard to replace 0603
parts; many Metcal burns. Through a modest amount of genius and a lot
of experimenting and dumb luck, I\'ve got the f/t curve parabolic with
the flat at 40c, and maybe 35 ppm p-p over my operating range. I can
tolerate +-500 before my PLL breaks.

Spice only helped a little. As Mike E says, the real value of Spice
isn\'t to prove anything, it\'s to train your instincts.

Part of the compensation is, basically, an FR4 capacitor, which has a
strong positive cap TC. The issue will be, can I get this sort of
tempco in production?

I want very constant sine wave amplitude, beginning with the first
oscillation cycle. Holding that amplitude turned out to be tricky and
of course tangled with the tempco issue.


In production an FR4 cap can get iffy. How about a little local heat
inside a regulator loop that keeps the temperature well above max
expected but constant? The heater could be a 1206 resistor.

That\'s interesting. The uP knows the board temp, so it could PWM a
resistor or so in the oscillator region, probably on the back side of
the board. I\'ll include that on the next PCB rev.

We already tweak the fan speed to try to keep the overall PCB
temperature constant, which will help a lot. That will help other
circuits on the board too. The box will self-heat about 35C or so,
with the fan off.

The fan algorithm is simple: 10 times a second, if the temp is below
40c, jog the fan voltage down. If above 40c, jog it up. The jogs are
small and it powers up slow, so there is no acoustic drama.


That only works if there are no other major variable heat producers far
away from the oscillator.


https://www.dropbox.com/s/uf15erm1nj3tjjk/Colpitts_125.JPG?raw=1

There are varicaps and things too. Everything affects the tempco. I
can tune C4 to zap the 1st order term.

Worst case, every batch of PCBs could have a different value of C4.
Production would *not* like that.


Whenever I had something like that I\'d always use a varicap and some
sort of algorithm. The production guys didn\'t even have to know it was
there.

My oscillator has a varicap, part of the PLL. Of course, a varicap has
a tempco the varies with the applied voltage!

Of course, there is the other option of running the whole board in
transformer oil

Smile when you say that.

It\'s impressive how isothermal a 10-layer board can be. Lots of
copper!

We need to rev the board, so I could add heater resistors and a
dedicated temp sensor under the oscillator. With luck, we\'d never have
to use them. Depends on whether my tempco tuning is reproducible in
production.

Another reason to spin the layout: I was having time-delay jitter
going through one FPGA, synchronous to a switcher in the opposite
corner of the board. I couldn\'t understand that, so I disabled the
switcher with some difficulty and hacked in a linear reg. That fixed
it.

A real pain to do. I had to drill out some vias to disable the
switcher.

https://www.dropbox.com/s/ghu5rid4ks0bbfl/1v8_Hack.jpg?raw=1

https://www.dropbox.com/s/g4llhvgq38cqedh/1v8_hack_Jitter.jpg?raw=1

Much of that jitter is probably from the scope.

 

[John Larkin]

On Fri, 2 Oct 2020 13:11:12 -0700, Joerg <news@analogconsultants.com>
wrote:

On 10/1/20 9:17 AM, Gerhard Hoffmann wrote:
Am 01.10.20 um 17:39 schrieb Joerg:
On 10/1/20 7:45 AM, Three Jeeps wrote:
On Thursday, October 1, 2020 at 1:09:03 AM UTC-4, Joerg wrote:
On 9/30/20 8:46 PM, jla...@highlandsniptechnology.com wrote:

In the last week, I\'ve been burned 6 times, shocked once, punctured
(with blood) twice, and had to eat a single burger for three lunches
in a row. And we are out of ice cream sandwiches.

Could be worse. BE-256 yeast is out of stock everywhere for months
and I
can\'t brew Belgian abbaye ales. That\'s serious!



--
Regards, Joerg

http://www.analogconsultants.com/
https://homebrewsupply.com/fermentis-safbrew-be-256-yeast/


Nine bucks, yikes! Oh well, goes like ammo I guess. A poster in the
brew NG pointed out another place but I found that their BE-256 yeast
was quite old.

Somehow production of this stuff must have stopped.


First google result:


https://www.hobbybrauerversand.de/Safale-BE-256-Abbaye-obergaerige-Trockenhefe-115-g
        

cheers, Gerhard

Sorry, 1st attempt went via PM.

Quote \"Ihr Shop wurde installiert. Lesen Sie in unserem Guide mehr zu
ersten Schritten mit JTL-Shop, der Grundkonfiguration und dem erstem
Abgleich mit JTL-Wawi\".

Ahm ...

Anyhow, there are also a few shops in the US that still have some but
it\'s quite old, expiration date is too close. Yeast viability is a big
thing with brewers and especially so when brewing a Belgian abbaye ale.

Just curious, but do people buy competitor\'s draft beer to steal the
yeast?

 

[Lasse Langwadt Christensen]

lørdag den 3. oktober 2020 kl. 01.45.12 UTC+2 skrev John Larkin:

On Fri, 2 Oct 2020 13:11:12 -0700, Joerg <news@analogconsultants.com
wrote:

On 10/1/20 9:17 AM, Gerhard Hoffmann wrote:
Am 01.10.20 um 17:39 schrieb Joerg:
On 10/1/20 7:45 AM, Three Jeeps wrote:
On Thursday, October 1, 2020 at 1:09:03 AM UTC-4, Joerg wrote:
On 9/30/20 8:46 PM, jla...@highlandsniptechnology.com wrote:

In the last week, I\'ve been burned 6 times, shocked once, punctured
(with blood) twice, and had to eat a single burger for three lunches
in a row. And we are out of ice cream sandwiches.

Could be worse. BE-256 yeast is out of stock everywhere for months
and I
can\'t brew Belgian abbaye ales. That\'s serious!



--
Regards, Joerg

http://www.analogconsultants.com/
https://homebrewsupply.com/fermentis-safbrew-be-256-yeast/


Nine bucks, yikes! Oh well, goes like ammo I guess. A poster in the
brew NG pointed out another place but I found that their BE-256 yeast
was quite old.

Somehow production of this stuff must have stopped.


First google result:


https://www.hobbybrauerversand.de/Safale-BE-256-Abbaye-obergaerige-Trockenhefe-115-g
        

cheers, Gerhard

Sorry, 1st attempt went via PM.

Quote \"Ihr Shop wurde installiert. Lesen Sie in unserem Guide mehr zu
ersten Schritten mit JTL-Shop, der Grundkonfiguration und dem erstem
Abgleich mit JTL-Wawi\".

Ahm ...

Anyhow, there are also a few shops in the US that still have some but
it\'s quite old, expiration date is too close. Yeast viability is a big
thing with brewers and especially so when brewing a Belgian abbaye ale.

Just curious, but do people buy competitor\'s draft beer to steal the
yeast?

if it isn\'t pasteurised an filtered

http://www.bellsbeer.com/news/how-culture-bell-s-house-yeast-bottle-bell-s-beer

 

[Joerg]

On 10/2/20 4:42 PM, John Larkin wrote:

On Fri, 2 Oct 2020 13:14:58 -0700, Joerg <news@analogconsultants.com
wrote:

On 10/1/20 9:30 AM, jlarkin@highlandsniptechnology.com wrote:

[...]

https://www.dropbox.com/s/uf15erm1nj3tjjk/Colpitts_125.JPG?raw=1

There are varicaps and things too. Everything affects the tempco. I
can tune C4 to zap the 1st order term.

Worst case, every batch of PCBs could have a different value of C4.
Production would *not* like that.


Whenever I had something like that I\'d always use a varicap and some
sort of algorithm. The production guys didn\'t even have to know it was
there.

My oscillator has a varicap, part of the PLL. Of course, a varicap has
a tempco the varies with the applied voltage!

Yeah, another error term and probably non-linear.

Of course, there is the other option of running the whole board in
transformer oil

Smile when you say that.

It\'s impressive how isothermal a 10-layer board can be. Lots of
copper!

We need to rev the board, so I could add heater resistors and a
dedicated temp sensor under the oscillator. With luck, we\'d never have
to use them. Depends on whether my tempco tuning is reproducible in
production.

Another reason to spin the layout: I was having time-delay jitter
going through one FPGA, synchronous to a switcher in the opposite
corner of the board. I couldn\'t understand that, so I disabled the
switcher with some difficulty and hacked in a linear reg. That fixed
it.

We\'ve had similar effects in pulsed Doppler ultrasound systems. Those
are like a princess on the pea when it comes to jitter on any of the
clocks. What I sometimes did is run a coax or (after relayout) a trace
over to the oscillator or stage that was affected and coupled in
opposite phase via a sub-pF ceramic cap. The guys usually thought that
was voodoo but it worked reliably and most of all repeatably so
production didnt have to worry about it.

A real pain to do. I had to drill out some vias to disable the
switcher.

https://www.dropbox.com/s/ghu5rid4ks0bbfl/1v8_Hack.jpg?raw=1

https://www.dropbox.com/s/g4llhvgq38cqedh/1v8_hack_Jitter.jpg?raw=1

Much of that jitter is probably from the scope.

Do you have a before-after comparison?

--
Regards, Joerg

http://www.analogconsultants.com/

 

[Joerg]

On 10/2/20 5:02 PM, Lasse Langwadt Christensen wrote:

lørdag den 3. oktober 2020 kl. 01.45.12 UTC+2 skrev John Larkin:
On Fri, 2 Oct 2020 13:11:12 -0700, Joerg <news@analogconsultants.com
wrote:

On 10/1/20 9:17 AM, Gerhard Hoffmann wrote:
Am 01.10.20 um 17:39 schrieb Joerg:
On 10/1/20 7:45 AM, Three Jeeps wrote:
On Thursday, October 1, 2020 at 1:09:03 AM UTC-4, Joerg wrote:
On 9/30/20 8:46 PM, jla...@highlandsniptechnology.com wrote:

In the last week, I\'ve been burned 6 times, shocked once, punctured
(with blood) twice, and had to eat a single burger for three lunches
in a row. And we are out of ice cream sandwiches.

Could be worse. BE-256 yeast is out of stock everywhere for months
and I
can\'t brew Belgian abbaye ales. That\'s serious!



--
Regards, Joerg

http://www.analogconsultants.com/
https://homebrewsupply.com/fermentis-safbrew-be-256-yeast/


Nine bucks, yikes! Oh well, goes like ammo I guess. A poster in the
brew NG pointed out another place but I found that their BE-256 yeast
was quite old.

Somehow production of this stuff must have stopped.


First google result:


https://www.hobbybrauerversand.de/Safale-BE-256-Abbaye-obergaerige-Trockenhefe-115-g
        

cheers, Gerhard

Sorry, 1st attempt went via PM.

Quote \"Ihr Shop wurde installiert. Lesen Sie in unserem Guide mehr zu
ersten Schritten mit JTL-Shop, der Grundkonfiguration und dem erstem
Abgleich mit JTL-Wawi\".

Ahm ...

Anyhow, there are also a few shops in the US that still have some but
it\'s quite old, expiration date is too close. Yeast viability is a big
thing with brewers and especially so when brewing a Belgian abbaye ale.

Just curious, but do people buy competitor\'s draft beer to steal the
yeast?

if it isn\'t pasteurised an filtered

http://www.bellsbeer.com/news/how-culture-bell-s-house-yeast-bottle-bell-s-beer

Harvesting from commercial bottles has become tough. Big breweries try
to make sure there is no to little viable yeast left. Not so much for
\"yeast theft\" reasons but to avoid exploding bottles (bottle greneades)
when stored in warm temperatures.

--
Regards, Joerg

http://www.analogconsultants.com/

 

[server]

On Fri, 2 Oct 2020 22:10:30 -0700, Joerg <news@analogconsultants.com>
wrote:

On 10/2/20 4:42 PM, John Larkin wrote:
On Fri, 2 Oct 2020 13:14:58 -0700, Joerg <news@analogconsultants.com
wrote:

On 10/1/20 9:30 AM, jlarkin@highlandsniptechnology.com wrote:

[...]

https://www.dropbox.com/s/uf15erm1nj3tjjk/Colpitts_125.JPG?raw=1

There are varicaps and things too. Everything affects the tempco. I
can tune C4 to zap the 1st order term.

Worst case, every batch of PCBs could have a different value of C4.
Production would *not* like that.


Whenever I had something like that I\'d always use a varicap and some
sort of algorithm. The production guys didn\'t even have to know it was
there.

My oscillator has a varicap, part of the PLL. Of course, a varicap has
a tempco the varies with the applied voltage!


Yeah, another error term and probably non-linear.


Of course, there is the other option of running the whole board in
transformer oil

Smile when you say that.

It\'s impressive how isothermal a 10-layer board can be. Lots of
copper!

We need to rev the board, so I could add heater resistors and a
dedicated temp sensor under the oscillator. With luck, we\'d never have
to use them. Depends on whether my tempco tuning is reproducible in
production.

Another reason to spin the layout: I was having time-delay jitter
going through one FPGA, synchronous to a switcher in the opposite
corner of the board. I couldn\'t understand that, so I disabled the
switcher with some difficulty and hacked in a linear reg. That fixed
it.


We\'ve had similar effects in pulsed Doppler ultrasound systems. Those
are like a princess on the pea when it comes to jitter on any of the
clocks. What I sometimes did is run a coax or (after relayout) a trace
over to the oscillator or stage that was affected and coupled in
opposite phase via a sub-pF ceramic cap. The guys usually thought that
was voodoo but it worked reliably and most of all repeatably so
production didnt have to worry about it.


A real pain to do. I had to drill out some vias to disable the
switcher.

https://www.dropbox.com/s/ghu5rid4ks0bbfl/1v8_Hack.jpg?raw=1

https://www.dropbox.com/s/g4llhvgq38cqedh/1v8_hack_Jitter.jpg?raw=1

Much of that jitter is probably from the scope.


Do you have a before-after comparison?

I don\'t have a good \"before\" pic handy. P-P jitter was about 2x what
it is now.

I noticed that the jitter would squirm as a function of trigger rate.
The heterodyne frequency corresponded exactly to the switching
frequency of one of the LTM8078 switchers (which are themselves
remarkably frequency stable.) It was the 1.8 volt Vcc_aux power supply
to two FPGAs, one directly in the delay path.

I doubt that Vcc_aux affects prop delay much; it doesn\'t for DC
changes. It may do nasty capacitive things inside the chip.

This Xilinx chip is very sensitive to core voltage, like -5 or -10 ps
per millivolt.

The whole front end of this box could have been ECL, but that takes a
lot of room and power and dollars.

My goal is to make a delay generator with 1 ps RMS jitter. I can
probably get below 5.

We\'ll announce this soon.

https://www.dropbox.com/s/j3fycoyhpus0vpc/a4.jpg?raw=1







--

John Larkin Highland Technology, Inc

Science teaches us to doubt.

Claude Bernard

 

[bitrex]

On 10/3/2020 10:49 AM, jlarkin@highlandsniptechnology.com wrote:

On Fri, 2 Oct 2020 22:10:30 -0700, Joerg <news@analogconsultants.com
wrote:

On 10/2/20 4:42 PM, John Larkin wrote:
On Fri, 2 Oct 2020 13:14:58 -0700, Joerg <news@analogconsultants.com
wrote:

On 10/1/20 9:30 AM, jlarkin@highlandsniptechnology.com wrote:

[...]

https://www.dropbox.com/s/uf15erm1nj3tjjk/Colpitts_125.JPG?raw=1

There are varicaps and things too. Everything affects the tempco. I
can tune C4 to zap the 1st order term.

Worst case, every batch of PCBs could have a different value of C4.
Production would *not* like that.


Whenever I had something like that I\'d always use a varicap and some
sort of algorithm. The production guys didn\'t even have to know it was
there.

My oscillator has a varicap, part of the PLL. Of course, a varicap has
a tempco the varies with the applied voltage!


Yeah, another error term and probably non-linear.


Of course, there is the other option of running the whole board in
transformer oil

Smile when you say that.

It\'s impressive how isothermal a 10-layer board can be. Lots of
copper!

We need to rev the board, so I could add heater resistors and a
dedicated temp sensor under the oscillator. With luck, we\'d never have
to use them. Depends on whether my tempco tuning is reproducible in
production.

Another reason to spin the layout: I was having time-delay jitter
going through one FPGA, synchronous to a switcher in the opposite
corner of the board. I couldn\'t understand that, so I disabled the
switcher with some difficulty and hacked in a linear reg. That fixed
it.


We\'ve had similar effects in pulsed Doppler ultrasound systems. Those
are like a princess on the pea when it comes to jitter on any of the
clocks. What I sometimes did is run a coax or (after relayout) a trace
over to the oscillator or stage that was affected and coupled in
opposite phase via a sub-pF ceramic cap. The guys usually thought that
was voodoo but it worked reliably and most of all repeatably so
production didnt have to worry about it.


A real pain to do. I had to drill out some vias to disable the
switcher.

https://www.dropbox.com/s/ghu5rid4ks0bbfl/1v8_Hack.jpg?raw=1

https://www.dropbox.com/s/g4llhvgq38cqedh/1v8_hack_Jitter.jpg?raw=1

Much of that jitter is probably from the scope.


Do you have a before-after comparison?

I don\'t have a good \"before\" pic handy. P-P jitter was about 2x what
it is now.

I noticed that the jitter would squirm as a function of trigger rate.
The heterodyne frequency corresponded exactly to the switching
frequency of one of the LTM8078 switchers (which are themselves
remarkably frequency stable.) It was the 1.8 volt Vcc_aux power supply
to two FPGAs, one directly in the delay path.

I doubt that Vcc_aux affects prop delay much; it doesn\'t for DC
changes. It may do nasty capacitive things inside the chip.

This Xilinx chip is very sensitive to core voltage, like -5 or -10 ps
per millivolt.

The whole front end of this box could have been ECL, but that takes a
lot of room and power and dollars.

My goal is to make a delay generator with 1 ps RMS jitter. I can
probably get below 5.

We\'ll announce this soon.

https://www.dropbox.com/s/j3fycoyhpus0vpc/a4.jpg?raw=1

Thank u for keeping in mind that 10-12% of the adult male population is
color-blind and that labels on heavily-used buttons wear off

 

[bitrex]

On 9/30/2020 11:50 PM, John Robertson wrote:

On 2020/09/30 8:46 p.m., jlarkin@highlandsniptechnology.com wrote:

In the last week, I\'ve been burned 6 times, shocked once, punctured
(with blood) twice, and had to eat a single burger for three lunches
in a row. And we are out of ice cream sandwiches.


Does your state not have Workers Compensation boards that check for
proper working conditions?

Or were you trying to cook hamburgers and only got three actually done?
Perhaps experimenting with electrocuting hot dogs at the same time??

John ;-#)#

Prospecting in abandoned mines in the Southwest for preserved denim
jeans from the 1800s is a dangerous job, but well-preserved 150 y/o
American denim jeans are a hot item on like the Japanese collectors
market and sell for up to $10,000 per I guess

<https://www.youtube.com/watch?v=WI6ApUvuToM>

 

[David Lesher]

jlarkin@highlandsniptechnology.com writes:

In the last week, I\'ve been burned 6 times, shocked once, punctured
(with blood) twice, and had to eat a single burger for three lunches
in a row. And we are out of ice cream sandwiches.

Speaking of \"out of..\".
<https://youtu.be/Du5YK5FnyF4>

As for you:
<https://en.wikipedia.org/wiki/Purple_Heart#/media/Fileurple_Heart_Medal.svg>

 

[Phil Hobbs]

On 2020-10-03 10:49, jlarkin@highlandsniptechnology.com wrote:

On Fri, 2 Oct 2020 22:10:30 -0700, Joerg <news@analogconsultants.com
wrote:

On 10/2/20 4:42 PM, John Larkin wrote:
On Fri, 2 Oct 2020 13:14:58 -0700, Joerg <news@analogconsultants.com
wrote:

On 10/1/20 9:30 AM, jlarkin@highlandsniptechnology.com wrote:

[...]

https://www.dropbox.com/s/uf15erm1nj3tjjk/Colpitts_125.JPG?raw=1

There are varicaps and things too. Everything affects the tempco. I
can tune C4 to zap the 1st order term.

Worst case, every batch of PCBs could have a different value of C4.
Production would *not* like that.


Whenever I had something like that I\'d always use a varicap and some
sort of algorithm. The production guys didn\'t even have to know it was
there.

My oscillator has a varicap, part of the PLL. Of course, a varicap has
a tempco the varies with the applied voltage!


Yeah, another error term and probably non-linear.


Of course, there is the other option of running the whole board in
transformer oil

Smile when you say that.

It\'s impressive how isothermal a 10-layer board can be. Lots of
copper!

We need to rev the board, so I could add heater resistors and a
dedicated temp sensor under the oscillator. With luck, we\'d never have
to use them. Depends on whether my tempco tuning is reproducible in
production.

Another reason to spin the layout: I was having time-delay jitter
going through one FPGA, synchronous to a switcher in the opposite
corner of the board. I couldn\'t understand that, so I disabled the
switcher with some difficulty and hacked in a linear reg. That fixed
it.


We\'ve had similar effects in pulsed Doppler ultrasound systems. Those
are like a princess on the pea when it comes to jitter on any of the
clocks. What I sometimes did is run a coax or (after relayout) a trace
over to the oscillator or stage that was affected and coupled in
opposite phase via a sub-pF ceramic cap. The guys usually thought that
was voodoo but it worked reliably and most of all repeatably so
production didnt have to worry about it.


A real pain to do. I had to drill out some vias to disable the
switcher.

https://www.dropbox.com/s/ghu5rid4ks0bbfl/1v8_Hack.jpg?raw=1

https://www.dropbox.com/s/g4llhvgq38cqedh/1v8_hack_Jitter.jpg?raw=1

Much of that jitter is probably from the scope.


Do you have a before-after comparison?

I don\'t have a good \"before\" pic handy. P-P jitter was about 2x what
it is now.

I noticed that the jitter would squirm as a function of trigger rate.
The heterodyne frequency corresponded exactly to the switching
frequency of one of the LTM8078 switchers (which are themselves
remarkably frequency stable.) It was the 1.8 volt Vcc_aux power supply
to two FPGAs, one directly in the delay path.

I doubt that Vcc_aux affects prop delay much; it doesn\'t for DC
changes. It may do nasty capacitive things inside the chip.

This Xilinx chip is very sensitive to core voltage, like -5 or -10 ps
per millivolt.

The whole front end of this box could have been ECL, but that takes a
lot of room and power and dollars.

My goal is to make a delay generator with 1 ps RMS jitter. I can
probably get below 5.

We\'ll announce this soon.

https://www.dropbox.com/s/j3fycoyhpus0vpc/a4.jpg?raw=1

Cool. I\'ve long used the P400 very happily as you know.

Cheers

Phil Hobbs


--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC / Hobbs ElectroOptics
Optics, Electro-optics, Photonics, Analog Electronics
Briarcliff Manor NY 10510

http://electrooptical.net
http://hobbs-eo.com

 

[server]

On Sat, 3 Oct 2020 20:03:19 -0400, Phil Hobbs
<pcdhSpamMeSenseless@electrooptical.net> wrote:

On 2020-10-03 10:49, jlarkin@highlandsniptechnology.com wrote:
On Fri, 2 Oct 2020 22:10:30 -0700, Joerg <news@analogconsultants.com
wrote:

On 10/2/20 4:42 PM, John Larkin wrote:
On Fri, 2 Oct 2020 13:14:58 -0700, Joerg <news@analogconsultants.com
wrote:

On 10/1/20 9:30 AM, jlarkin@highlandsniptechnology.com wrote:

[...]

https://www.dropbox.com/s/uf15erm1nj3tjjk/Colpitts_125.JPG?raw=1

There are varicaps and things too. Everything affects the tempco. I
can tune C4 to zap the 1st order term.

Worst case, every batch of PCBs could have a different value of C4.
Production would *not* like that.


Whenever I had something like that I\'d always use a varicap and some
sort of algorithm. The production guys didn\'t even have to know it was
there.

My oscillator has a varicap, part of the PLL. Of course, a varicap has
a tempco the varies with the applied voltage!


Yeah, another error term and probably non-linear.


Of course, there is the other option of running the whole board in
transformer oil

Smile when you say that.

It\'s impressive how isothermal a 10-layer board can be. Lots of
copper!

We need to rev the board, so I could add heater resistors and a
dedicated temp sensor under the oscillator. With luck, we\'d never have
to use them. Depends on whether my tempco tuning is reproducible in
production.

Another reason to spin the layout: I was having time-delay jitter
going through one FPGA, synchronous to a switcher in the opposite
corner of the board. I couldn\'t understand that, so I disabled the
switcher with some difficulty and hacked in a linear reg. That fixed
it.


We\'ve had similar effects in pulsed Doppler ultrasound systems. Those
are like a princess on the pea when it comes to jitter on any of the
clocks. What I sometimes did is run a coax or (after relayout) a trace
over to the oscillator or stage that was affected and coupled in
opposite phase via a sub-pF ceramic cap. The guys usually thought that
was voodoo but it worked reliably and most of all repeatably so
production didnt have to worry about it.


A real pain to do. I had to drill out some vias to disable the
switcher.

https://www.dropbox.com/s/ghu5rid4ks0bbfl/1v8_Hack.jpg?raw=1

https://www.dropbox.com/s/g4llhvgq38cqedh/1v8_hack_Jitter.jpg?raw=1

Much of that jitter is probably from the scope.


Do you have a before-after comparison?

I don\'t have a good \"before\" pic handy. P-P jitter was about 2x what
it is now.

I noticed that the jitter would squirm as a function of trigger rate.
The heterodyne frequency corresponded exactly to the switching
frequency of one of the LTM8078 switchers (which are themselves
remarkably frequency stable.) It was the 1.8 volt Vcc_aux power supply
to two FPGAs, one directly in the delay path.

I doubt that Vcc_aux affects prop delay much; it doesn\'t for DC
changes. It may do nasty capacitive things inside the chip.

This Xilinx chip is very sensitive to core voltage, like -5 or -10 ps
per millivolt.

The whole front end of this box could have been ECL, but that takes a
lot of room and power and dollars.

My goal is to make a delay generator with 1 ps RMS jitter. I can
probably get below 5.

We\'ll announce this soon.

https://www.dropbox.com/s/j3fycoyhpus0vpc/a4.jpg?raw=1

Cool. I\'ve long used the P400 very happily as you know.

Cheers

Phil Hobbs

I\'ll send you a P500.

I\'m especially happy with the GaN output stage. Vhigh can go from -5
to +20, and Vlow +-5, very clean all the way. If I showed you the
circuit, you\'d laugh and say \"that can\'t work.\"

I made a simple pulse generator with that same output circuit, just to
stay amused during the early lockdown.

http://www.highlandtechnology.com/DSS/J270DS.shtml

If you define a plane with pulse rate on one axis and voltage on the
other, there are inhabited regions, Schmoo diagram style, like for
instance avalanche transistors in one blob, mosfets in another. We may
have our own little turf, say 100 MHz and 100 volts. Somebody might
want that.



--

John Larkin Highland Technology, Inc

Science teaches us to doubt.

Claude Bernard

 

[Phil Hobbs]

On 2020-10-03 23:58, jlarkin@highlandsniptechnology.com wrote:

On Sat, 3 Oct 2020 20:03:19 -0400, Phil Hobbs
pcdhSpamMeSenseless@electrooptical.net> wrote:

On 2020-10-03 10:49, jlarkin@highlandsniptechnology.com wrote:
On Fri, 2 Oct 2020 22:10:30 -0700, Joerg <news@analogconsultants.com
wrote:

On 10/2/20 4:42 PM, John Larkin wrote:
On Fri, 2 Oct 2020 13:14:58 -0700, Joerg <news@analogconsultants.com
wrote:

On 10/1/20 9:30 AM, jlarkin@highlandsniptechnology.com wrote:

[...]

https://www.dropbox.com/s/uf15erm1nj3tjjk/Colpitts_125.JPG?raw=1

There are varicaps and things too. Everything affects the tempco. I
can tune C4 to zap the 1st order term.

Worst case, every batch of PCBs could have a different value of C4.
Production would *not* like that.


Whenever I had something like that I\'d always use a varicap and some
sort of algorithm. The production guys didn\'t even have to know it was
there.

My oscillator has a varicap, part of the PLL. Of course, a varicap has
a tempco the varies with the applied voltage!


Yeah, another error term and probably non-linear.


Of course, there is the other option of running the whole board in
transformer oil

Smile when you say that.

It\'s impressive how isothermal a 10-layer board can be. Lots of
copper!

We need to rev the board, so I could add heater resistors and a
dedicated temp sensor under the oscillator. With luck, we\'d never have
to use them. Depends on whether my tempco tuning is reproducible in
production.

Another reason to spin the layout: I was having time-delay jitter
going through one FPGA, synchronous to a switcher in the opposite
corner of the board. I couldn\'t understand that, so I disabled the
switcher with some difficulty and hacked in a linear reg. That fixed
it.


We\'ve had similar effects in pulsed Doppler ultrasound systems. Those
are like a princess on the pea when it comes to jitter on any of the
clocks. What I sometimes did is run a coax or (after relayout) a trace
over to the oscillator or stage that was affected and coupled in
opposite phase via a sub-pF ceramic cap. The guys usually thought that
was voodoo but it worked reliably and most of all repeatably so
production didnt have to worry about it.


A real pain to do. I had to drill out some vias to disable the
switcher.

https://www.dropbox.com/s/ghu5rid4ks0bbfl/1v8_Hack.jpg?raw=1

https://www.dropbox.com/s/g4llhvgq38cqedh/1v8_hack_Jitter.jpg?raw=1

Much of that jitter is probably from the scope.


Do you have a before-after comparison?

I don\'t have a good \"before\" pic handy. P-P jitter was about 2x what
it is now.

I noticed that the jitter would squirm as a function of trigger rate.
The heterodyne frequency corresponded exactly to the switching
frequency of one of the LTM8078 switchers (which are themselves
remarkably frequency stable.) It was the 1.8 volt Vcc_aux power supply
to two FPGAs, one directly in the delay path.

I doubt that Vcc_aux affects prop delay much; it doesn\'t for DC
changes. It may do nasty capacitive things inside the chip.

This Xilinx chip is very sensitive to core voltage, like -5 or -10 ps
per millivolt.

The whole front end of this box could have been ECL, but that takes a
lot of room and power and dollars.

My goal is to make a delay generator with 1 ps RMS jitter. I can
probably get below 5.

We\'ll announce this soon.

https://www.dropbox.com/s/j3fycoyhpus0vpc/a4.jpg?raw=1

Cool. I\'ve long used the P400 very happily as you know.


I\'ll send you a P500.

Looking forward to trying it out! We\'re planning to use the P400 to
calibrate a time-stretcher for geophysical lidar, where you want many
samples in a short time but the rep rate is slow. We\'d certainly use
the swoopy new one if it gets here in the next couple of months.

I\'m especially happy with the GaN output stage. Vhigh can go from -5
to +20, and Vlow +-5, very clean all the way. If I showed you the
circuit, you\'d laugh and say \"that can\'t work.\"

I feel that way about some of your other circuits too. Fortunately I
know enough not to start a fight when the data goes the other way.

I made a simple pulse generator with that same output circuit, just to
stay amused during the early lockdown.

http://www.highlandtechnology.com/DSS/J270DS.shtml

If you define a plane with pulse rate on one axis and voltage on the
other, there are inhabited regions, Schmoo diagram style, like for
instance avalanche transistors in one blob, mosfets in another. We may
have our own little turf, say 100 MHz and 100 volts. Somebody might
want that.

That regime sounds pretty physicsy, but there are a fair number of
interesting electron-microscope-style applications, I expect. Dunno if
any would lead to sales volumes that would excite you.

I really like instruments whose limits I don\'t have to worry about.

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC / Hobbs ElectroOptics
Optics, Electro-optics, Photonics, Analog Electronics
Briarcliff Manor NY 10510

http://electrooptical.net
http://hobbs-eo.com

 

[John Larkin]

On Sat, 3 Oct 2020 11:29:28 -0400, bitrex <user@example.net> wrote:

On 10/3/2020 10:49 AM, jlarkin@highlandsniptechnology.com wrote:
On Fri, 2 Oct 2020 22:10:30 -0700, Joerg <news@analogconsultants.com
wrote:

On 10/2/20 4:42 PM, John Larkin wrote:
On Fri, 2 Oct 2020 13:14:58 -0700, Joerg <news@analogconsultants.com
wrote:

On 10/1/20 9:30 AM, jlarkin@highlandsniptechnology.com wrote:

[...]

https://www.dropbox.com/s/uf15erm1nj3tjjk/Colpitts_125.JPG?raw=1

There are varicaps and things too. Everything affects the tempco. I
can tune C4 to zap the 1st order term.

Worst case, every batch of PCBs could have a different value of C4.
Production would *not* like that.


Whenever I had something like that I\'d always use a varicap and some
sort of algorithm. The production guys didn\'t even have to know it was
there.

My oscillator has a varicap, part of the PLL. Of course, a varicap has
a tempco the varies with the applied voltage!


Yeah, another error term and probably non-linear.


Of course, there is the other option of running the whole board in
transformer oil

Smile when you say that.

It\'s impressive how isothermal a 10-layer board can be. Lots of
copper!

We need to rev the board, so I could add heater resistors and a
dedicated temp sensor under the oscillator. With luck, we\'d never have
to use them. Depends on whether my tempco tuning is reproducible in
production.

Another reason to spin the layout: I was having time-delay jitter
going through one FPGA, synchronous to a switcher in the opposite
corner of the board. I couldn\'t understand that, so I disabled the
switcher with some difficulty and hacked in a linear reg. That fixed
it.


We\'ve had similar effects in pulsed Doppler ultrasound systems. Those
are like a princess on the pea when it comes to jitter on any of the
clocks. What I sometimes did is run a coax or (after relayout) a trace
over to the oscillator or stage that was affected and coupled in
opposite phase via a sub-pF ceramic cap. The guys usually thought that
was voodoo but it worked reliably and most of all repeatably so
production didnt have to worry about it.


A real pain to do. I had to drill out some vias to disable the
switcher.

https://www.dropbox.com/s/ghu5rid4ks0bbfl/1v8_Hack.jpg?raw=1

https://www.dropbox.com/s/g4llhvgq38cqedh/1v8_hack_Jitter.jpg?raw=1

Much of that jitter is probably from the scope.


Do you have a before-after comparison?

I don\'t have a good \"before\" pic handy. P-P jitter was about 2x what
it is now.

I noticed that the jitter would squirm as a function of trigger rate.
The heterodyne frequency corresponded exactly to the switching
frequency of one of the LTM8078 switchers (which are themselves
remarkably frequency stable.) It was the 1.8 volt Vcc_aux power supply
to two FPGAs, one directly in the delay path.

I doubt that Vcc_aux affects prop delay much; it doesn\'t for DC
changes. It may do nasty capacitive things inside the chip.

This Xilinx chip is very sensitive to core voltage, like -5 or -10 ps
per millivolt.

The whole front end of this box could have been ECL, but that takes a
lot of room and power and dollars.

My goal is to make a delay generator with 1 ps RMS jitter. I can
probably get below 5.

We\'ll announce this soon.

https://www.dropbox.com/s/j3fycoyhpus0vpc/a4.jpg?raw=1


Thank u for keeping in mind that 10-12% of the adult male population is
color-blind and that labels on heavily-used buttons wear off

The LCD is black on white. Each button is single color backlit with
obvious text.

You\'re straining to disapprove of a beautiful box. Why?

You\'d better not buy one.

 

[John Larkin]

On Sun, 4 Oct 2020 17:05:41 -0400, Phil Hobbs
<pcdhSpamMeSenseless@electrooptical.net> wrote:

On 2020-10-03 23:58, jlarkin@highlandsniptechnology.com wrote:
On Sat, 3 Oct 2020 20:03:19 -0400, Phil Hobbs
pcdhSpamMeSenseless@electrooptical.net> wrote:

On 2020-10-03 10:49, jlarkin@highlandsniptechnology.com wrote:
On Fri, 2 Oct 2020 22:10:30 -0700, Joerg <news@analogconsultants.com
wrote:

On 10/2/20 4:42 PM, John Larkin wrote:
On Fri, 2 Oct 2020 13:14:58 -0700, Joerg <news@analogconsultants.com
wrote:

On 10/1/20 9:30 AM, jlarkin@highlandsniptechnology.com wrote:

[...]

https://www.dropbox.com/s/uf15erm1nj3tjjk/Colpitts_125.JPG?raw=1

There are varicaps and things too. Everything affects the tempco. I
can tune C4 to zap the 1st order term.

Worst case, every batch of PCBs could have a different value of C4.
Production would *not* like that.


Whenever I had something like that I\'d always use a varicap and some
sort of algorithm. The production guys didn\'t even have to know it was
there.

My oscillator has a varicap, part of the PLL. Of course, a varicap has
a tempco the varies with the applied voltage!


Yeah, another error term and probably non-linear.


Of course, there is the other option of running the whole board in
transformer oil

Smile when you say that.

It\'s impressive how isothermal a 10-layer board can be. Lots of
copper!

We need to rev the board, so I could add heater resistors and a
dedicated temp sensor under the oscillator. With luck, we\'d never have
to use them. Depends on whether my tempco tuning is reproducible in
production.

Another reason to spin the layout: I was having time-delay jitter
going through one FPGA, synchronous to a switcher in the opposite
corner of the board. I couldn\'t understand that, so I disabled the
switcher with some difficulty and hacked in a linear reg. That fixed
it.


We\'ve had similar effects in pulsed Doppler ultrasound systems. Those
are like a princess on the pea when it comes to jitter on any of the
clocks. What I sometimes did is run a coax or (after relayout) a trace
over to the oscillator or stage that was affected and coupled in
opposite phase via a sub-pF ceramic cap. The guys usually thought that
was voodoo but it worked reliably and most of all repeatably so
production didnt have to worry about it.


A real pain to do. I had to drill out some vias to disable the
switcher.

https://www.dropbox.com/s/ghu5rid4ks0bbfl/1v8_Hack.jpg?raw=1

https://www.dropbox.com/s/g4llhvgq38cqedh/1v8_hack_Jitter.jpg?raw=1

Much of that jitter is probably from the scope.


Do you have a before-after comparison?

I don\'t have a good \"before\" pic handy. P-P jitter was about 2x what
it is now.

I noticed that the jitter would squirm as a function of trigger rate.
The heterodyne frequency corresponded exactly to the switching
frequency of one of the LTM8078 switchers (which are themselves
remarkably frequency stable.) It was the 1.8 volt Vcc_aux power supply
to two FPGAs, one directly in the delay path.

I doubt that Vcc_aux affects prop delay much; it doesn\'t for DC
changes. It may do nasty capacitive things inside the chip.

This Xilinx chip is very sensitive to core voltage, like -5 or -10 ps
per millivolt.

The whole front end of this box could have been ECL, but that takes a
lot of room and power and dollars.

My goal is to make a delay generator with 1 ps RMS jitter. I can
probably get below 5.

We\'ll announce this soon.

https://www.dropbox.com/s/j3fycoyhpus0vpc/a4.jpg?raw=1

Cool. I\'ve long used the P400 very happily as you know.


I\'ll send you a P500.

Looking forward to trying it out! We\'re planning to use the P400 to
calibrate a time-stretcher for geophysical lidar, where you want many
samples in a short time but the rep rate is slow. We\'d certainly use
the swoopy new one if it gets here in the next couple of months.

I\'m especially happy with the GaN output stage. Vhigh can go from -5
to +20, and Vlow +-5, very clean all the way. If I showed you the
circuit, you\'d laugh and say \"that can\'t work.\"

I feel that way about some of your other circuits too. Fortunately I
know enough not to start a fight when the data goes the other way.

We\'re curently implementing the \"trains and frames\" option. A \"train\"
is a series of programmable pulses on all channels, after a trigger.
\"Frames\" is a series of timing settings that change every trigger.
They can be combined.

Our problem isn\'t so much how to implement it, but how to explain it
to users and provide them a language to program it. We don\'t want a
zillion emails and phone calls from grad students or whoever.

 

[John Larkin]

On Sat, 3 Oct 2020 23:27:35 +0000 (UTC), David Lesher
<wb8foz@panix.com> wrote:

jlarkin@highlandsniptechnology.com writes:


In the last week, I\'ve been burned 6 times, shocked once, punctured
(with blood) twice, and had to eat a single burger for three lunches
in a row. And we are out of ice cream sandwiches.

Speaking of \"out of..\".
https://youtu.be/Du5YK5FnyF4

Shooting and killing and explosions and hatred is mostly what
Hollywood does nowadays, while preaching gun control and peace and
love.

As for you:
https://en.wikipedia.org/wiki/Purple_Heart#/media/Fileurple_Heart_Medal.svg

My reward is purchase orders.

 

[bitrex]

On 10/5/2020 2:04 PM, John Larkin wrote:

On Sat, 3 Oct 2020 23:27:35 +0000 (UTC), David Lesher
wb8foz@panix.com> wrote:

jlarkin@highlandsniptechnology.com writes:


In the last week, I\'ve been burned 6 times, shocked once, punctured
(with blood) twice, and had to eat a single burger for three lunches
in a row. And we are out of ice cream sandwiches.

Speaking of \"out of..\".
https://youtu.be/Du5YK5FnyF4


Shooting and killing and explosions and hatred is mostly what
Hollywood does nowadays, while preaching gun control and peace and
love.

Almost like they\'ve learned that overestimating American\'s intelligence
is rarely profitable.

That is to say they know their market.

Or China\'s for that matter, which will soon make up the bulk of
Hollywood\'s market, if it hasn\'t already. Much English-language nuance
doesn\'t translate well to Mandarin. Kind of like telling jokes to engineers

As for you:
https://en.wikipedia.org/wiki/Purple_Heart#/media/Fileurple_Heart_Medal.svg

My reward is purchase orders.

 

[bitrex]

On 10/5/2020 1:53 PM, John Larkin wrote:

On Sat, 3 Oct 2020 11:29:28 -0400, bitrex <user@example.net> wrote:

On 10/3/2020 10:49 AM, jlarkin@highlandsniptechnology.com wrote:
On Fri, 2 Oct 2020 22:10:30 -0700, Joerg <news@analogconsultants.com
wrote:

On 10/2/20 4:42 PM, John Larkin wrote:
On Fri, 2 Oct 2020 13:14:58 -0700, Joerg <news@analogconsultants.com
wrote:

On 10/1/20 9:30 AM, jlarkin@highlandsniptechnology.com wrote:

[...]

https://www.dropbox.com/s/uf15erm1nj3tjjk/Colpitts_125.JPG?raw=1

There are varicaps and things too. Everything affects the tempco. I
can tune C4 to zap the 1st order term.

Worst case, every batch of PCBs could have a different value of C4.
Production would *not* like that.


Whenever I had something like that I\'d always use a varicap and some
sort of algorithm. The production guys didn\'t even have to know it was
there.

My oscillator has a varicap, part of the PLL. Of course, a varicap has
a tempco the varies with the applied voltage!


Yeah, another error term and probably non-linear.


Of course, there is the other option of running the whole board in
transformer oil

Smile when you say that.

It\'s impressive how isothermal a 10-layer board can be. Lots of
copper!

We need to rev the board, so I could add heater resistors and a
dedicated temp sensor under the oscillator. With luck, we\'d never have
to use them. Depends on whether my tempco tuning is reproducible in
production.

Another reason to spin the layout: I was having time-delay jitter
going through one FPGA, synchronous to a switcher in the opposite
corner of the board. I couldn\'t understand that, so I disabled the
switcher with some difficulty and hacked in a linear reg. That fixed
it.


We\'ve had similar effects in pulsed Doppler ultrasound systems. Those
are like a princess on the pea when it comes to jitter on any of the
clocks. What I sometimes did is run a coax or (after relayout) a trace
over to the oscillator or stage that was affected and coupled in
opposite phase via a sub-pF ceramic cap. The guys usually thought that
was voodoo but it worked reliably and most of all repeatably so
production didnt have to worry about it.


A real pain to do. I had to drill out some vias to disable the
switcher.

https://www.dropbox.com/s/ghu5rid4ks0bbfl/1v8_Hack.jpg?raw=1

https://www.dropbox.com/s/g4llhvgq38cqedh/1v8_hack_Jitter.jpg?raw=1

Much of that jitter is probably from the scope.


Do you have a before-after comparison?

I don\'t have a good \"before\" pic handy. P-P jitter was about 2x what
it is now.

I noticed that the jitter would squirm as a function of trigger rate.
The heterodyne frequency corresponded exactly to the switching
frequency of one of the LTM8078 switchers (which are themselves
remarkably frequency stable.) It was the 1.8 volt Vcc_aux power supply
to two FPGAs, one directly in the delay path.

I doubt that Vcc_aux affects prop delay much; it doesn\'t for DC
changes. It may do nasty capacitive things inside the chip.

This Xilinx chip is very sensitive to core voltage, like -5 or -10 ps
per millivolt.

The whole front end of this box could have been ECL, but that takes a
lot of room and power and dollars.

My goal is to make a delay generator with 1 ps RMS jitter. I can
probably get below 5.

We\'ll announce this soon.

https://www.dropbox.com/s/j3fycoyhpus0vpc/a4.jpg?raw=1


Thank u for keeping in mind that 10-12% of the adult male population is
color-blind and that labels on heavily-used buttons wear off

The LCD is black on white. Each button is single color backlit with
obvious text.

You\'re straining to disapprove of a beautiful box. Why?

?????

You\'d better not buy one.

No I was actually thanking you

 

[bitrex]

On 10/5/2020 1:53 PM, John Larkin wrote:

On Sat, 3 Oct 2020 11:29:28 -0400, bitrex <user@example.net> wrote:

On 10/3/2020 10:49 AM, jlarkin@highlandsniptechnology.com wrote:
On Fri, 2 Oct 2020 22:10:30 -0700, Joerg <news@analogconsultants.com
wrote:

On 10/2/20 4:42 PM, John Larkin wrote:
On Fri, 2 Oct 2020 13:14:58 -0700, Joerg <news@analogconsultants.com
wrote:

On 10/1/20 9:30 AM, jlarkin@highlandsniptechnology.com wrote:

[...]

https://www.dropbox.com/s/uf15erm1nj3tjjk/Colpitts_125.JPG?raw=1

There are varicaps and things too. Everything affects the tempco. I
can tune C4 to zap the 1st order term.

Worst case, every batch of PCBs could have a different value of C4.
Production would *not* like that.


Whenever I had something like that I\'d always use a varicap and some
sort of algorithm. The production guys didn\'t even have to know it was
there.

My oscillator has a varicap, part of the PLL. Of course, a varicap has
a tempco the varies with the applied voltage!


Yeah, another error term and probably non-linear.


Of course, there is the other option of running the whole board in
transformer oil

Smile when you say that.

It\'s impressive how isothermal a 10-layer board can be. Lots of
copper!

We need to rev the board, so I could add heater resistors and a
dedicated temp sensor under the oscillator. With luck, we\'d never have
to use them. Depends on whether my tempco tuning is reproducible in
production.

Another reason to spin the layout: I was having time-delay jitter
going through one FPGA, synchronous to a switcher in the opposite
corner of the board. I couldn\'t understand that, so I disabled the
switcher with some difficulty and hacked in a linear reg. That fixed
it.


We\'ve had similar effects in pulsed Doppler ultrasound systems. Those
are like a princess on the pea when it comes to jitter on any of the
clocks. What I sometimes did is run a coax or (after relayout) a trace
over to the oscillator or stage that was affected and coupled in
opposite phase via a sub-pF ceramic cap. The guys usually thought that
was voodoo but it worked reliably and most of all repeatably so
production didnt have to worry about it.


A real pain to do. I had to drill out some vias to disable the
switcher.

https://www.dropbox.com/s/ghu5rid4ks0bbfl/1v8_Hack.jpg?raw=1

https://www.dropbox.com/s/g4llhvgq38cqedh/1v8_hack_Jitter.jpg?raw=1

Much of that jitter is probably from the scope.


Do you have a before-after comparison?

I don\'t have a good \"before\" pic handy. P-P jitter was about 2x what
it is now.

I noticed that the jitter would squirm as a function of trigger rate.
The heterodyne frequency corresponded exactly to the switching
frequency of one of the LTM8078 switchers (which are themselves
remarkably frequency stable.) It was the 1.8 volt Vcc_aux power supply
to two FPGAs, one directly in the delay path.

I doubt that Vcc_aux affects prop delay much; it doesn\'t for DC
changes. It may do nasty capacitive things inside the chip.

This Xilinx chip is very sensitive to core voltage, like -5 or -10 ps
per millivolt.

The whole front end of this box could have been ECL, but that takes a
lot of room and power and dollars.

My goal is to make a delay generator with 1 ps RMS jitter. I can
probably get below 5.

We\'ll announce this soon.

https://www.dropbox.com/s/j3fycoyhpus0vpc/a4.jpg?raw=1


Thank u for keeping in mind that 10-12% of the adult male population is
color-blind and that labels on heavily-used buttons wear off

The LCD is black on white. Each button is single color backlit with
obvious text.

You\'re straining to disapprove of a beautiful box. Why?

You\'d better not buy one.

My Rigol scope for example uses one button called START/STOP to start
and stop and uses a green/red LED to indicate which mode it\'s in

10-12% of the adult male population is color blind with red/green the
most common!