S
server
Guest
Thanks, Lasse ð
S
server
Guest
Thanks, Lasse ð
P
Phil Hobbs
Guest
On 2020-07-23 16:25, Ricketty C wrote:
Right. It\'ll be done only occasionally, since R_E of a BJT is a weak
function of everything. In a diff pair, R_E produces degeneration,
which tends to make the current split by the ratios of the R_E values,
whereas we want it to do the Ebers-Moll thing and split strictly as
exp(delta V_BE/kT):1. R_E degeneration generally dominates the error
budget at higher photocurrents.
If transistors Q1 and Q2 have resistances R_E1 and R_E2, then the
required voltage is
dV_BEcor = I_E2 * R_E2 - I_E1 * R_E1.
Since V_B1 is controlled by a feedback loop trying to make the total DC
current from two or more photodiodes cancel out, the correction voltage
gets applied to the base of Q2. Since the resistances are nearly
constant, rapid adjustment of the correction law is not required.
However, the unwanted degeneration applies at AC as well as DC, and the
attainable benefit is limited by phase shift and amplitude error in the
correction voltage. Thus I do need to form the correction in analogue
with as high a bandwidth as reasonably possible.
There\'ll be a cal table in flash, which will probably rely on the
AD5273\'s decent DNL to interpolate relatively coarsely between
steps--aiming for, say, 8-bit accuracy. That\'s potentially enough to
reduce the degeneration effect by 50 dB in the spherical cow universe.
Then there\'ll be a magic pushbutton on the box so that users in lab
settings can tell it that their experiment is all set up, so please
optimize the noise cancellation for these exact conditions. Nobody will
mind if that takes 5 seconds or so. (The command will be available
electronically as well--USB serial or maybe a dedicated control line.)
The magic BFP640, with its ~1-kV Early voltage, excellent saturation
behaviour, and ultralow C_CB, allows all sorts of cute tricks. I\'m
dorking V_CE on one side of the diff pair in real time to force the
power dissipation of Q1 and Q2 to be equal irrespective of the splitting
ratio (within limits).
With some routed slots to control local temperature gradients, it looks
like I can get performance equivalent to a 40-GHz monolithic dual.
(We\'ll see how spherical the cows are in real life--I\'ve seen some
pretty fat ones.)
Fun.
Cheers
Phil Hobbs
(Who\'s stocking up on BFP640s as he did on BF862s)
--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC / Hobbs ElectroOptics
Optics, Electro-optics, Photonics, Analog Electronics
Briarcliff Manor NY 10510
http://electrooptical.net
http://hobbs-eo.com
On Thursday, July 23, 2020 at 7:39:36 AM UTC-4, pcdh...@gmail.com
wrote:
I guess I\'m not following what this gains? You get lots more
steps, but >you don\'t know any more about where they are. What
am I missing?
What it gets me is a combination of settability and bandwidth that
I can\'t get in any single part at any price. I\'ll dump in a bit of
pseudorandom DNL and see if that causes any issues. I don\'t expect
it to--it\'ll get homogenized much like the regular steps.
For an iterative adjustment (think LC filter tuning) I can get
close by setting the fine pot to 0, adjusting the coarse pot, then
walking the two together to find the optimum. Near full scale the
possible search range is wider, but I don\'t think it\'ll take too
long provided that I\'m willing to settle for \"good enough\" rather
than a global optimum.
There are two mildly-interacting adjustments, but the response
surface is simple--no local minima.
It\'s for taking out the effect of extrinsic emitter resistance in
the BJT diff pair that\'s the heart of the circuit. It works by
applying a signal to one of the bases that cancels out the
effective emitter degeneration and so restores the desired
Ebers-Moll behaviour at higher photocurrents.
If I feel like getting fancy, once I\'ve found the right
neighbourhood I can give the turd a final polish to get a bit
closer.
There are non-negligible effects such as the tempco of wiper
resistance that limit how good this approach can be. Sure beats a
trimpot on a motor though!
Ok, so this circuit is not a real time control loop as much as it is
like a successive approximation. You don\'t mind the value varying
unpredictably as long as it eventually reaches a setting.
Right. It\'ll be done only occasionally, since R_E of a BJT is a weak
function of everything. In a diff pair, R_E produces degeneration,
which tends to make the current split by the ratios of the R_E values,
whereas we want it to do the Ebers-Moll thing and split strictly as
exp(delta V_BE/kT):1. R_E degeneration generally dominates the error
budget at higher photocurrents.
If transistors Q1 and Q2 have resistances R_E1 and R_E2, then the
required voltage is
dV_BEcor = I_E2 * R_E2 - I_E1 * R_E1.
Since V_B1 is controlled by a feedback loop trying to make the total DC
current from two or more photodiodes cancel out, the correction voltage
gets applied to the base of Q2. Since the resistances are nearly
constant, rapid adjustment of the correction law is not required.
However, the unwanted degeneration applies at AC as well as DC, and the
attainable benefit is limited by phase shift and amplitude error in the
correction voltage. Thus I do need to form the correction in analogue
with as high a bandwidth as reasonably possible.
There\'ll be a cal table in flash, which will probably rely on the
AD5273\'s decent DNL to interpolate relatively coarsely between
steps--aiming for, say, 8-bit accuracy. That\'s potentially enough to
reduce the degeneration effect by 50 dB in the spherical cow universe.
Then there\'ll be a magic pushbutton on the box so that users in lab
settings can tell it that their experiment is all set up, so please
optimize the noise cancellation for these exact conditions. Nobody will
mind if that takes 5 seconds or so. (The command will be available
electronically as well--USB serial or maybe a dedicated control line.)
The magic BFP640, with its ~1-kV Early voltage, excellent saturation
behaviour, and ultralow C_CB, allows all sorts of cute tricks. I\'m
dorking V_CE on one side of the diff pair in real time to force the
power dissipation of Q1 and Q2 to be equal irrespective of the splitting
ratio (within limits).
With some routed slots to control local temperature gradients, it looks
like I can get performance equivalent to a 40-GHz monolithic dual.
(We\'ll see how spherical the cows are in real life--I\'ve seen some
pretty fat ones.)
Fun.
Cheers
Phil Hobbs
(Who\'s stocking up on BFP640s as he did on BF862s)
--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC / Hobbs ElectroOptics
Optics, Electro-optics, Photonics, Analog Electronics
Briarcliff Manor NY 10510
http://electrooptical.net
http://hobbs-eo.com
P
Phil Hobbs
Guest
On 2020-07-23 16:25, Ricketty C wrote:
Right. It\'ll be done only occasionally, since R_E of a BJT is a weak
function of everything. In a diff pair, R_E produces degeneration,
which tends to make the current split by the ratios of the R_E values,
whereas we want it to do the Ebers-Moll thing and split strictly as
exp(delta V_BE/kT):1. R_E degeneration generally dominates the error
budget at higher photocurrents.
If transistors Q1 and Q2 have resistances R_E1 and R_E2, then the
required voltage is
dV_BEcor = I_E2 * R_E2 - I_E1 * R_E1.
Since V_B1 is controlled by a feedback loop trying to make the total DC
current from two or more photodiodes cancel out, the correction voltage
gets applied to the base of Q2. Since the resistances are nearly
constant, rapid adjustment of the correction law is not required.
However, the unwanted degeneration applies at AC as well as DC, and the
attainable benefit is limited by phase shift and amplitude error in the
correction voltage. Thus I do need to form the correction in analogue
with as high a bandwidth as reasonably possible.
There\'ll be a cal table in flash, which will probably rely on the
AD5273\'s decent DNL to interpolate relatively coarsely between
steps--aiming for, say, 8-bit accuracy. That\'s potentially enough to
reduce the degeneration effect by 50 dB in the spherical cow universe.
Then there\'ll be a magic pushbutton on the box so that users in lab
settings can tell it that their experiment is all set up, so please
optimize the noise cancellation for these exact conditions. Nobody will
mind if that takes 5 seconds or so. (The command will be available
electronically as well--USB serial or maybe a dedicated control line.)
The magic BFP640, with its ~1-kV Early voltage, excellent saturation
behaviour, and ultralow C_CB, allows all sorts of cute tricks. I\'m
dorking V_CE on one side of the diff pair in real time to force the
power dissipation of Q1 and Q2 to be equal irrespective of the splitting
ratio (within limits).
With some routed slots to control local temperature gradients, it looks
like I can get performance equivalent to a 40-GHz monolithic dual.
(We\'ll see how spherical the cows are in real life--I\'ve seen some
pretty fat ones.)
Fun.
Cheers
Phil Hobbs
(Who\'s stocking up on BFP640s as he did on BF862s)
--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC / Hobbs ElectroOptics
Optics, Electro-optics, Photonics, Analog Electronics
Briarcliff Manor NY 10510
http://electrooptical.net
http://hobbs-eo.com
On Thursday, July 23, 2020 at 7:39:36 AM UTC-4, pcdh...@gmail.com
wrote:
I guess I\'m not following what this gains? You get lots more
steps, but >you don\'t know any more about where they are. What
am I missing?
What it gets me is a combination of settability and bandwidth that
I can\'t get in any single part at any price. I\'ll dump in a bit of
pseudorandom DNL and see if that causes any issues. I don\'t expect
it to--it\'ll get homogenized much like the regular steps.
For an iterative adjustment (think LC filter tuning) I can get
close by setting the fine pot to 0, adjusting the coarse pot, then
walking the two together to find the optimum. Near full scale the
possible search range is wider, but I don\'t think it\'ll take too
long provided that I\'m willing to settle for \"good enough\" rather
than a global optimum.
There are two mildly-interacting adjustments, but the response
surface is simple--no local minima.
It\'s for taking out the effect of extrinsic emitter resistance in
the BJT diff pair that\'s the heart of the circuit. It works by
applying a signal to one of the bases that cancels out the
effective emitter degeneration and so restores the desired
Ebers-Moll behaviour at higher photocurrents.
If I feel like getting fancy, once I\'ve found the right
neighbourhood I can give the turd a final polish to get a bit
closer.
There are non-negligible effects such as the tempco of wiper
resistance that limit how good this approach can be. Sure beats a
trimpot on a motor though!
Ok, so this circuit is not a real time control loop as much as it is
like a successive approximation. You don\'t mind the value varying
unpredictably as long as it eventually reaches a setting.
Right. It\'ll be done only occasionally, since R_E of a BJT is a weak
function of everything. In a diff pair, R_E produces degeneration,
which tends to make the current split by the ratios of the R_E values,
whereas we want it to do the Ebers-Moll thing and split strictly as
exp(delta V_BE/kT):1. R_E degeneration generally dominates the error
budget at higher photocurrents.
If transistors Q1 and Q2 have resistances R_E1 and R_E2, then the
required voltage is
dV_BEcor = I_E2 * R_E2 - I_E1 * R_E1.
Since V_B1 is controlled by a feedback loop trying to make the total DC
current from two or more photodiodes cancel out, the correction voltage
gets applied to the base of Q2. Since the resistances are nearly
constant, rapid adjustment of the correction law is not required.
However, the unwanted degeneration applies at AC as well as DC, and the
attainable benefit is limited by phase shift and amplitude error in the
correction voltage. Thus I do need to form the correction in analogue
with as high a bandwidth as reasonably possible.
There\'ll be a cal table in flash, which will probably rely on the
AD5273\'s decent DNL to interpolate relatively coarsely between
steps--aiming for, say, 8-bit accuracy. That\'s potentially enough to
reduce the degeneration effect by 50 dB in the spherical cow universe.
Then there\'ll be a magic pushbutton on the box so that users in lab
settings can tell it that their experiment is all set up, so please
optimize the noise cancellation for these exact conditions. Nobody will
mind if that takes 5 seconds or so. (The command will be available
electronically as well--USB serial or maybe a dedicated control line.)
The magic BFP640, with its ~1-kV Early voltage, excellent saturation
behaviour, and ultralow C_CB, allows all sorts of cute tricks. I\'m
dorking V_CE on one side of the diff pair in real time to force the
power dissipation of Q1 and Q2 to be equal irrespective of the splitting
ratio (within limits).
With some routed slots to control local temperature gradients, it looks
like I can get performance equivalent to a 40-GHz monolithic dual.
(We\'ll see how spherical the cows are in real life--I\'ve seen some
pretty fat ones.)
Fun.
Cheers
Phil Hobbs
(Who\'s stocking up on BFP640s as he did on BF862s)
--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC / Hobbs ElectroOptics
Optics, Electro-optics, Photonics, Analog Electronics
Briarcliff Manor NY 10510
http://electrooptical.net
http://hobbs-eo.com
P
Phil Hobbs
Guest
On 2020-07-23 16:25, Ricketty C wrote:
Right. It\'ll be done only occasionally, since R_E of a BJT is a weak
function of everything. In a diff pair, R_E produces degeneration,
which tends to make the current split by the ratios of the R_E values,
whereas we want it to do the Ebers-Moll thing and split strictly as
exp(delta V_BE/kT):1. R_E degeneration generally dominates the error
budget at higher photocurrents.
If transistors Q1 and Q2 have resistances R_E1 and R_E2, then the
required voltage is
dV_BEcor = I_E2 * R_E2 - I_E1 * R_E1.
Since V_B1 is controlled by a feedback loop trying to make the total DC
current from two or more photodiodes cancel out, the correction voltage
gets applied to the base of Q2. Since the resistances are nearly
constant, rapid adjustment of the correction law is not required.
However, the unwanted degeneration applies at AC as well as DC, and the
attainable benefit is limited by phase shift and amplitude error in the
correction voltage. Thus I do need to form the correction in analogue
with as high a bandwidth as reasonably possible.
There\'ll be a cal table in flash, which will probably rely on the
AD5273\'s decent DNL to interpolate relatively coarsely between
steps--aiming for, say, 8-bit accuracy. That\'s potentially enough to
reduce the degeneration effect by 50 dB in the spherical cow universe.
Then there\'ll be a magic pushbutton on the box so that users in lab
settings can tell it that their experiment is all set up, so please
optimize the noise cancellation for these exact conditions. Nobody will
mind if that takes 5 seconds or so. (The command will be available
electronically as well--USB serial or maybe a dedicated control line.)
The magic BFP640, with its ~1-kV Early voltage, excellent saturation
behaviour, and ultralow C_CB, allows all sorts of cute tricks. I\'m
dorking V_CE on one side of the diff pair in real time to force the
power dissipation of Q1 and Q2 to be equal irrespective of the splitting
ratio (within limits).
With some routed slots to control local temperature gradients, it looks
like I can get performance equivalent to a 40-GHz monolithic dual.
(We\'ll see how spherical the cows are in real life--I\'ve seen some
pretty fat ones.)
Fun.
Cheers
Phil Hobbs
(Who\'s stocking up on BFP640s as he did on BF862s)
--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC / Hobbs ElectroOptics
Optics, Electro-optics, Photonics, Analog Electronics
Briarcliff Manor NY 10510
http://electrooptical.net
http://hobbs-eo.com
On Thursday, July 23, 2020 at 7:39:36 AM UTC-4, pcdh...@gmail.com
wrote:
I guess I\'m not following what this gains? You get lots more
steps, but >you don\'t know any more about where they are. What
am I missing?
What it gets me is a combination of settability and bandwidth that
I can\'t get in any single part at any price. I\'ll dump in a bit of
pseudorandom DNL and see if that causes any issues. I don\'t expect
it to--it\'ll get homogenized much like the regular steps.
For an iterative adjustment (think LC filter tuning) I can get
close by setting the fine pot to 0, adjusting the coarse pot, then
walking the two together to find the optimum. Near full scale the
possible search range is wider, but I don\'t think it\'ll take too
long provided that I\'m willing to settle for \"good enough\" rather
than a global optimum.
There are two mildly-interacting adjustments, but the response
surface is simple--no local minima.
It\'s for taking out the effect of extrinsic emitter resistance in
the BJT diff pair that\'s the heart of the circuit. It works by
applying a signal to one of the bases that cancels out the
effective emitter degeneration and so restores the desired
Ebers-Moll behaviour at higher photocurrents.
If I feel like getting fancy, once I\'ve found the right
neighbourhood I can give the turd a final polish to get a bit
closer.
There are non-negligible effects such as the tempco of wiper
resistance that limit how good this approach can be. Sure beats a
trimpot on a motor though!
Ok, so this circuit is not a real time control loop as much as it is
like a successive approximation. You don\'t mind the value varying
unpredictably as long as it eventually reaches a setting.
Right. It\'ll be done only occasionally, since R_E of a BJT is a weak
function of everything. In a diff pair, R_E produces degeneration,
which tends to make the current split by the ratios of the R_E values,
whereas we want it to do the Ebers-Moll thing and split strictly as
exp(delta V_BE/kT):1. R_E degeneration generally dominates the error
budget at higher photocurrents.
If transistors Q1 and Q2 have resistances R_E1 and R_E2, then the
required voltage is
dV_BEcor = I_E2 * R_E2 - I_E1 * R_E1.
Since V_B1 is controlled by a feedback loop trying to make the total DC
current from two or more photodiodes cancel out, the correction voltage
gets applied to the base of Q2. Since the resistances are nearly
constant, rapid adjustment of the correction law is not required.
However, the unwanted degeneration applies at AC as well as DC, and the
attainable benefit is limited by phase shift and amplitude error in the
correction voltage. Thus I do need to form the correction in analogue
with as high a bandwidth as reasonably possible.
There\'ll be a cal table in flash, which will probably rely on the
AD5273\'s decent DNL to interpolate relatively coarsely between
steps--aiming for, say, 8-bit accuracy. That\'s potentially enough to
reduce the degeneration effect by 50 dB in the spherical cow universe.
Then there\'ll be a magic pushbutton on the box so that users in lab
settings can tell it that their experiment is all set up, so please
optimize the noise cancellation for these exact conditions. Nobody will
mind if that takes 5 seconds or so. (The command will be available
electronically as well--USB serial or maybe a dedicated control line.)
The magic BFP640, with its ~1-kV Early voltage, excellent saturation
behaviour, and ultralow C_CB, allows all sorts of cute tricks. I\'m
dorking V_CE on one side of the diff pair in real time to force the
power dissipation of Q1 and Q2 to be equal irrespective of the splitting
ratio (within limits).
With some routed slots to control local temperature gradients, it looks
like I can get performance equivalent to a 40-GHz monolithic dual.
(We\'ll see how spherical the cows are in real life--I\'ve seen some
pretty fat ones.)
Fun.
Cheers
Phil Hobbs
(Who\'s stocking up on BFP640s as he did on BF862s)
--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC / Hobbs ElectroOptics
Optics, Electro-optics, Photonics, Analog Electronics
Briarcliff Manor NY 10510
http://electrooptical.net
http://hobbs-eo.com
C
Chris Jones
Guest
On 24/07/2020 09:14, Phil Hobbs wrote:
By the way, I don\'t know if you\'ve seen this, but google and skywater
fab are open-sourcing the PDK for a 0.13um CMOS process, and google is
paying for some free shuttle runs, subject to certain rules including
that all designs be open-sourced too.
If you can think of anything that you really wish you could get on a
chip, and that can be made in CMOS, and that is useful to you but not
secret enough to not want to publish the design, now is the time!
Shuttle run in November and you get hundreds of parts back, so maybe
enough for a low-volume product. Lots of people are playing with the
tools so quite likely someone else would lay it out for fun if you
didn\'t have time.
There is a link to the slack workspace here, with many more details:
https://groups.google.com/forum/#!topic/skywater-pdk-announce/zijPNEsqsx4
On 2020-07-23 16:25, Ricketty C wrote:
On Thursday, July 23, 2020 at 7:39:36 AM UTC-4, pcdh...@gmail.com
wrote:
I guess I\'m not following what this gains? You get lots more
steps, but >you don\'t know any more about where they are. What
am I missing?
What it gets me is a combination of settability and bandwidth that
I can\'t get in any single part at any price. I\'ll dump in a bit of
pseudorandom DNL and see if that causes any issues. I don\'t expect
it to--it\'ll get homogenized much like the regular steps.
For an iterative adjustment (think LC filter tuning) I can get
close by setting the fine pot to 0, adjusting the coarse pot, then
walking the two together to find the optimum. Near full scale the
possible search range is wider, but I don\'t think it\'ll take too
long provided that I\'m willing to settle for \"good enough\" rather
than a global optimum.
There are two mildly-interacting adjustments, but the response
surface is simple--no local minima.
It\'s for taking out the effect of extrinsic emitter resistance in
the BJT diff pair that\'s the heart of the circuit. It works by
applying a signal to one of the bases that cancels out the
effective emitter degeneration and so restores the desired
Ebers-Moll behaviour at higher photocurrents.
If I feel like getting fancy, once I\'ve found the right
neighbourhood I can give the turd a final polish to get a bit
closer.
There are non-negligible effects such as the tempco of wiper
resistance that limit how good this approach can be. Sure beats a
trimpot on a motor though!
Ok, so this circuit is not a real time control loop as much as it is
like a successive approximation. You don\'t mind the value varying
unpredictably as long as it eventually reaches a setting.
Right. It\'ll be done only occasionally, since R_E of a BJT is a weak
function of everything. In a diff pair, R_E produces degeneration,
which tends to make the current split by the ratios of the R_E values,
whereas we want it to do the Ebers-Moll thing and split strictly as
exp(delta V_BE/kT):1. R_E degeneration generally dominates the error
budget at higher photocurrents.
If transistors Q1 and Q2 have resistances R_E1 and R_E2, then the
required voltage is
dV_BEcor = I_E2 * R_E2Â - I_E1 * R_E1.
Since V_B1 is controlled by a feedback loop trying to make the total DC
current from two or more photodiodes cancel out, the correction voltage
gets applied to the base of Q2. Since the resistances are nearly
constant, rapid adjustment of the correction law is not required.
However, the unwanted degeneration applies at AC as well as DC, and the
attainable benefit is limited by phase shift and amplitude error in the
correction voltage. Thus I do need to form the correction in analogue
with as high a bandwidth as reasonably possible.
There\'ll be a cal table in flash, which will probably rely on the
AD5273\'s decent DNL to interpolate relatively coarsely between
steps--aiming for, say, 8-bit accuracy. That\'s potentially enough to
reduce the degeneration effect by 50 dB in the spherical cow universe.
Then there\'ll be a magic pushbutton on the box so that users in lab
settings can tell it that their experiment is all set up, so please
optimize the noise cancellation for these exact conditions. Nobody will
mind if that takes 5 seconds or so. (The command will be available
electronically as well--USB serial or maybe a dedicated control line.)
The magic BFP640, with its ~1-kV Early voltage, excellent saturation
behaviour, and ultralow C_CB, allows all sorts of cute tricks. I\'m
dorking V_CE on one side of the diff pair in real time to force the
power dissipation of Q1 and Q2 to be equal irrespective of the splitting
ratio (within limits).
With some routed slots to control local temperature gradients, it looks
like I can get performance equivalent to a 40-GHz monolithic dual.
(We\'ll see how spherical the cows are in real life--I\'ve seen some
pretty fat ones.)
Fun.
Cheers
Phil Hobbs
(Who\'s stocking up on BFP640s as he did on BF862s)
By the way, I don\'t know if you\'ve seen this, but google and skywater
fab are open-sourcing the PDK for a 0.13um CMOS process, and google is
paying for some free shuttle runs, subject to certain rules including
that all designs be open-sourced too.
If you can think of anything that you really wish you could get on a
chip, and that can be made in CMOS, and that is useful to you but not
secret enough to not want to publish the design, now is the time!
Shuttle run in November and you get hundreds of parts back, so maybe
enough for a low-volume product. Lots of people are playing with the
tools so quite likely someone else would lay it out for fun if you
didn\'t have time.
There is a link to the slack workspace here, with many more details:
https://groups.google.com/forum/#!topic/skywater-pdk-announce/zijPNEsqsx4
C
Chris Jones
Guest
On 24/07/2020 09:14, Phil Hobbs wrote:
By the way, I don\'t know if you\'ve seen this, but google and skywater
fab are open-sourcing the PDK for a 0.13um CMOS process, and google is
paying for some free shuttle runs, subject to certain rules including
that all designs be open-sourced too.
If you can think of anything that you really wish you could get on a
chip, and that can be made in CMOS, and that is useful to you but not
secret enough to not want to publish the design, now is the time!
Shuttle run in November and you get hundreds of parts back, so maybe
enough for a low-volume product. Lots of people are playing with the
tools so quite likely someone else would lay it out for fun if you
didn\'t have time.
There is a link to the slack workspace here, with many more details:
https://groups.google.com/forum/#!topic/skywater-pdk-announce/zijPNEsqsx4
On 2020-07-23 16:25, Ricketty C wrote:
On Thursday, July 23, 2020 at 7:39:36 AM UTC-4, pcdh...@gmail.com
wrote:
I guess I\'m not following what this gains? You get lots more
steps, but >you don\'t know any more about where they are. What
am I missing?
What it gets me is a combination of settability and bandwidth that
I can\'t get in any single part at any price. I\'ll dump in a bit of
pseudorandom DNL and see if that causes any issues. I don\'t expect
it to--it\'ll get homogenized much like the regular steps.
For an iterative adjustment (think LC filter tuning) I can get
close by setting the fine pot to 0, adjusting the coarse pot, then
walking the two together to find the optimum. Near full scale the
possible search range is wider, but I don\'t think it\'ll take too
long provided that I\'m willing to settle for \"good enough\" rather
than a global optimum.
There are two mildly-interacting adjustments, but the response
surface is simple--no local minima.
It\'s for taking out the effect of extrinsic emitter resistance in
the BJT diff pair that\'s the heart of the circuit. It works by
applying a signal to one of the bases that cancels out the
effective emitter degeneration and so restores the desired
Ebers-Moll behaviour at higher photocurrents.
If I feel like getting fancy, once I\'ve found the right
neighbourhood I can give the turd a final polish to get a bit
closer.
There are non-negligible effects such as the tempco of wiper
resistance that limit how good this approach can be. Sure beats a
trimpot on a motor though!
Ok, so this circuit is not a real time control loop as much as it is
like a successive approximation. You don\'t mind the value varying
unpredictably as long as it eventually reaches a setting.
Right. It\'ll be done only occasionally, since R_E of a BJT is a weak
function of everything. In a diff pair, R_E produces degeneration,
which tends to make the current split by the ratios of the R_E values,
whereas we want it to do the Ebers-Moll thing and split strictly as
exp(delta V_BE/kT):1. R_E degeneration generally dominates the error
budget at higher photocurrents.
If transistors Q1 and Q2 have resistances R_E1 and R_E2, then the
required voltage is
dV_BEcor = I_E2 * R_E2Â - I_E1 * R_E1.
Since V_B1 is controlled by a feedback loop trying to make the total DC
current from two or more photodiodes cancel out, the correction voltage
gets applied to the base of Q2. Since the resistances are nearly
constant, rapid adjustment of the correction law is not required.
However, the unwanted degeneration applies at AC as well as DC, and the
attainable benefit is limited by phase shift and amplitude error in the
correction voltage. Thus I do need to form the correction in analogue
with as high a bandwidth as reasonably possible.
There\'ll be a cal table in flash, which will probably rely on the
AD5273\'s decent DNL to interpolate relatively coarsely between
steps--aiming for, say, 8-bit accuracy. That\'s potentially enough to
reduce the degeneration effect by 50 dB in the spherical cow universe.
Then there\'ll be a magic pushbutton on the box so that users in lab
settings can tell it that their experiment is all set up, so please
optimize the noise cancellation for these exact conditions. Nobody will
mind if that takes 5 seconds or so. (The command will be available
electronically as well--USB serial or maybe a dedicated control line.)
The magic BFP640, with its ~1-kV Early voltage, excellent saturation
behaviour, and ultralow C_CB, allows all sorts of cute tricks. I\'m
dorking V_CE on one side of the diff pair in real time to force the
power dissipation of Q1 and Q2 to be equal irrespective of the splitting
ratio (within limits).
With some routed slots to control local temperature gradients, it looks
like I can get performance equivalent to a 40-GHz monolithic dual.
(We\'ll see how spherical the cows are in real life--I\'ve seen some
pretty fat ones.)
Fun.
Cheers
Phil Hobbs
(Who\'s stocking up on BFP640s as he did on BF862s)
By the way, I don\'t know if you\'ve seen this, but google and skywater
fab are open-sourcing the PDK for a 0.13um CMOS process, and google is
paying for some free shuttle runs, subject to certain rules including
that all designs be open-sourced too.
If you can think of anything that you really wish you could get on a
chip, and that can be made in CMOS, and that is useful to you but not
secret enough to not want to publish the design, now is the time!
Shuttle run in November and you get hundreds of parts back, so maybe
enough for a low-volume product. Lots of people are playing with the
tools so quite likely someone else would lay it out for fun if you
didn\'t have time.
There is a link to the slack workspace here, with many more details:
https://groups.google.com/forum/#!topic/skywater-pdk-announce/zijPNEsqsx4
C
Chris Jones
Guest
On 24/07/2020 09:14, Phil Hobbs wrote:
By the way, I don\'t know if you\'ve seen this, but google and skywater
fab are open-sourcing the PDK for a 0.13um CMOS process, and google is
paying for some free shuttle runs, subject to certain rules including
that all designs be open-sourced too.
If you can think of anything that you really wish you could get on a
chip, and that can be made in CMOS, and that is useful to you but not
secret enough to not want to publish the design, now is the time!
Shuttle run in November and you get hundreds of parts back, so maybe
enough for a low-volume product. Lots of people are playing with the
tools so quite likely someone else would lay it out for fun if you
didn\'t have time.
There is a link to the slack workspace here, with many more details:
https://groups.google.com/forum/#!topic/skywater-pdk-announce/zijPNEsqsx4
On 2020-07-23 16:25, Ricketty C wrote:
On Thursday, July 23, 2020 at 7:39:36 AM UTC-4, pcdh...@gmail.com
wrote:
I guess I\'m not following what this gains? You get lots more
steps, but >you don\'t know any more about where they are. What
am I missing?
What it gets me is a combination of settability and bandwidth that
I can\'t get in any single part at any price. I\'ll dump in a bit of
pseudorandom DNL and see if that causes any issues. I don\'t expect
it to--it\'ll get homogenized much like the regular steps.
For an iterative adjustment (think LC filter tuning) I can get
close by setting the fine pot to 0, adjusting the coarse pot, then
walking the two together to find the optimum. Near full scale the
possible search range is wider, but I don\'t think it\'ll take too
long provided that I\'m willing to settle for \"good enough\" rather
than a global optimum.
There are two mildly-interacting adjustments, but the response
surface is simple--no local minima.
It\'s for taking out the effect of extrinsic emitter resistance in
the BJT diff pair that\'s the heart of the circuit. It works by
applying a signal to one of the bases that cancels out the
effective emitter degeneration and so restores the desired
Ebers-Moll behaviour at higher photocurrents.
If I feel like getting fancy, once I\'ve found the right
neighbourhood I can give the turd a final polish to get a bit
closer.
There are non-negligible effects such as the tempco of wiper
resistance that limit how good this approach can be. Sure beats a
trimpot on a motor though!
Ok, so this circuit is not a real time control loop as much as it is
like a successive approximation. You don\'t mind the value varying
unpredictably as long as it eventually reaches a setting.
Right. It\'ll be done only occasionally, since R_E of a BJT is a weak
function of everything. In a diff pair, R_E produces degeneration,
which tends to make the current split by the ratios of the R_E values,
whereas we want it to do the Ebers-Moll thing and split strictly as
exp(delta V_BE/kT):1. R_E degeneration generally dominates the error
budget at higher photocurrents.
If transistors Q1 and Q2 have resistances R_E1 and R_E2, then the
required voltage is
dV_BEcor = I_E2 * R_E2Â - I_E1 * R_E1.
Since V_B1 is controlled by a feedback loop trying to make the total DC
current from two or more photodiodes cancel out, the correction voltage
gets applied to the base of Q2. Since the resistances are nearly
constant, rapid adjustment of the correction law is not required.
However, the unwanted degeneration applies at AC as well as DC, and the
attainable benefit is limited by phase shift and amplitude error in the
correction voltage. Thus I do need to form the correction in analogue
with as high a bandwidth as reasonably possible.
There\'ll be a cal table in flash, which will probably rely on the
AD5273\'s decent DNL to interpolate relatively coarsely between
steps--aiming for, say, 8-bit accuracy. That\'s potentially enough to
reduce the degeneration effect by 50 dB in the spherical cow universe.
Then there\'ll be a magic pushbutton on the box so that users in lab
settings can tell it that their experiment is all set up, so please
optimize the noise cancellation for these exact conditions. Nobody will
mind if that takes 5 seconds or so. (The command will be available
electronically as well--USB serial or maybe a dedicated control line.)
The magic BFP640, with its ~1-kV Early voltage, excellent saturation
behaviour, and ultralow C_CB, allows all sorts of cute tricks. I\'m
dorking V_CE on one side of the diff pair in real time to force the
power dissipation of Q1 and Q2 to be equal irrespective of the splitting
ratio (within limits).
With some routed slots to control local temperature gradients, it looks
like I can get performance equivalent to a 40-GHz monolithic dual.
(We\'ll see how spherical the cows are in real life--I\'ve seen some
pretty fat ones.)
Fun.
Cheers
Phil Hobbs
(Who\'s stocking up on BFP640s as he did on BF862s)
By the way, I don\'t know if you\'ve seen this, but google and skywater
fab are open-sourcing the PDK for a 0.13um CMOS process, and google is
paying for some free shuttle runs, subject to certain rules including
that all designs be open-sourced too.
If you can think of anything that you really wish you could get on a
chip, and that can be made in CMOS, and that is useful to you but not
secret enough to not want to publish the design, now is the time!
Shuttle run in November and you get hundreds of parts back, so maybe
enough for a low-volume product. Lots of people are playing with the
tools so quite likely someone else would lay it out for fun if you
didn\'t have time.
There is a link to the slack workspace here, with many more details:
https://groups.google.com/forum/#!topic/skywater-pdk-announce/zijPNEsqsx4
P
Phil Hobbs
Guest
On 2020-07-23 22:16, Chris Jones wrote:
Sounds like a good opportunity for sure. If somebody would do that with
a decent low-noise analogue bipolar process (say 0.5 um) I\'d be all over it.
Cheers
Phil Hobbs
--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC / Hobbs ElectroOptics
Optics, Electro-optics, Photonics, Analog Electronics
Briarcliff Manor NY 10510
http://electrooptical.net
http://hobbs-eo.com
On 24/07/2020 09:14, Phil Hobbs wrote:
On 2020-07-23 16:25, Ricketty C wrote:
On Thursday, July 23, 2020 at 7:39:36 AM UTC-4, pcdh...@gmail.com
wrote:
I guess I\'m not following what this gains? You get lots more
steps, but >you don\'t know any more about where they are. What
am I missing?
What it gets me is a combination of settability and bandwidth that
I can\'t get in any single part at any price. I\'ll dump in a bit of
pseudorandom DNL and see if that causes any issues. I don\'t expect
it to--it\'ll get homogenized much like the regular steps.
For an iterative adjustment (think LC filter tuning) I can get
close by setting the fine pot to 0, adjusting the coarse pot, then
walking the two together to find the optimum. Near full scale the
possible search range is wider, but I don\'t think it\'ll take too
long provided that I\'m willing to settle for \"good enough\" rather
than a global optimum.
There are two mildly-interacting adjustments, but the response
surface is simple--no local minima.
It\'s for taking out the effect of extrinsic emitter resistance in
the BJT diff pair that\'s the heart of the circuit. It works by
applying a signal to one of the bases that cancels out the
effective emitter degeneration and so restores the desired
Ebers-Moll behaviour at higher photocurrents.
If I feel like getting fancy, once I\'ve found the right
neighbourhood I can give the turd a final polish to get a bit
closer.
There are non-negligible effects such as the tempco of wiper
resistance that limit how good this approach can be. Sure beats a
trimpot on a motor though!
Ok, so this circuit is not a real time control loop as much as it is
like a successive approximation. You don\'t mind the value varying
unpredictably as long as it eventually reaches a setting.
Right. It\'ll be done only occasionally, since R_E of a BJT is a weak
function of everything. In a diff pair, R_E produces degeneration,
which tends to make the current split by the ratios of the R_E values,
whereas we want it to do the Ebers-Moll thing and split strictly as
exp(delta V_BE/kT):1. R_E degeneration generally dominates the error
budget at higher photocurrents.
If transistors Q1 and Q2 have resistances R_E1 and R_E2, then the
required voltage is
dV_BEcor = I_E2 * R_E2Â - I_E1 * R_E1.
Since V_B1 is controlled by a feedback loop trying to make the total
DC current from two or more photodiodes cancel out, the correction
voltage gets applied to the base of Q2. Since the resistances are
nearly constant, rapid adjustment of the correction law is not required.
However, the unwanted degeneration applies at AC as well as DC, and
the attainable benefit is limited by phase shift and amplitude error
in the correction voltage. Thus I do need to form the correction in
analogue with as high a bandwidth as reasonably possible.
There\'ll be a cal table in flash, which will probably rely on the
AD5273\'s decent DNL to interpolate relatively coarsely between
steps--aiming for, say, 8-bit accuracy. That\'s potentially enough to
reduce the degeneration effect by 50 dB in the spherical cow universe.
Then there\'ll be a magic pushbutton on the box so that users in lab
settings can tell it that their experiment is all set up, so please
optimize the noise cancellation for these exact conditions. Nobody
will mind if that takes 5 seconds or so. (The command will be
available electronically as well--USB serial or maybe a dedicated
control line.)
The magic BFP640, with its ~1-kV Early voltage, excellent saturation
behaviour, and ultralow C_CB, allows all sorts of cute tricks. I\'m
dorking V_CE on one side of the diff pair in real time to force the
power dissipation of Q1 and Q2 to be equal irrespective of the
splitting ratio (within limits).
With some routed slots to control local temperature gradients, it
looks like I can get performance equivalent to a 40-GHz monolithic
dual. (We\'ll see how spherical the cows are in real life--I\'ve seen
some pretty fat ones.)
Fun.
Cheers
Phil Hobbs
(Who\'s stocking up on BFP640s as he did on BF862s)
By the way, I don\'t know if you\'ve seen this, but google and skywater
fab are open-sourcing the PDK for a 0.13um CMOS process, and google is
paying for some free shuttle runs, subject to certain rules including
that all designs be open-sourced too.
If you can think of anything that you really wish you could get on a
chip, and that can be made in CMOS, and that is useful to you but not
secret enough to not want to publish the design, now is the time!
Shuttle run in November and you get hundreds of parts back, so maybe
enough for a low-volume product. Lots of people are playing with the
tools so quite likely someone else would lay it out for fun if you
didn\'t have time.
There is a link to the slack workspace here, with many more details:
https://groups.google.com/forum/#!topic/skywater-pdk-announce/zijPNEsqsx4
Sounds like a good opportunity for sure. If somebody would do that with
a decent low-noise analogue bipolar process (say 0.5 um) I\'d be all over it.
Cheers
Phil Hobbs
--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC / Hobbs ElectroOptics
Optics, Electro-optics, Photonics, Analog Electronics
Briarcliff Manor NY 10510
http://electrooptical.net
http://hobbs-eo.com
P
Phil Hobbs
Guest
On 2020-07-23 22:16, Chris Jones wrote:
Sounds like a good opportunity for sure. If somebody would do that with
a decent low-noise analogue bipolar process (say 0.5 um) I\'d be all over it.
Cheers
Phil Hobbs
--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC / Hobbs ElectroOptics
Optics, Electro-optics, Photonics, Analog Electronics
Briarcliff Manor NY 10510
http://electrooptical.net
http://hobbs-eo.com
On 24/07/2020 09:14, Phil Hobbs wrote:
On 2020-07-23 16:25, Ricketty C wrote:
On Thursday, July 23, 2020 at 7:39:36 AM UTC-4, pcdh...@gmail.com
wrote:
I guess I\'m not following what this gains? You get lots more
steps, but >you don\'t know any more about where they are. What
am I missing?
What it gets me is a combination of settability and bandwidth that
I can\'t get in any single part at any price. I\'ll dump in a bit of
pseudorandom DNL and see if that causes any issues. I don\'t expect
it to--it\'ll get homogenized much like the regular steps.
For an iterative adjustment (think LC filter tuning) I can get
close by setting the fine pot to 0, adjusting the coarse pot, then
walking the two together to find the optimum. Near full scale the
possible search range is wider, but I don\'t think it\'ll take too
long provided that I\'m willing to settle for \"good enough\" rather
than a global optimum.
There are two mildly-interacting adjustments, but the response
surface is simple--no local minima.
It\'s for taking out the effect of extrinsic emitter resistance in
the BJT diff pair that\'s the heart of the circuit. It works by
applying a signal to one of the bases that cancels out the
effective emitter degeneration and so restores the desired
Ebers-Moll behaviour at higher photocurrents.
If I feel like getting fancy, once I\'ve found the right
neighbourhood I can give the turd a final polish to get a bit
closer.
There are non-negligible effects such as the tempco of wiper
resistance that limit how good this approach can be. Sure beats a
trimpot on a motor though!
Ok, so this circuit is not a real time control loop as much as it is
like a successive approximation. You don\'t mind the value varying
unpredictably as long as it eventually reaches a setting.
Right. It\'ll be done only occasionally, since R_E of a BJT is a weak
function of everything. In a diff pair, R_E produces degeneration,
which tends to make the current split by the ratios of the R_E values,
whereas we want it to do the Ebers-Moll thing and split strictly as
exp(delta V_BE/kT):1. R_E degeneration generally dominates the error
budget at higher photocurrents.
If transistors Q1 and Q2 have resistances R_E1 and R_E2, then the
required voltage is
dV_BEcor = I_E2 * R_E2Â - I_E1 * R_E1.
Since V_B1 is controlled by a feedback loop trying to make the total
DC current from two or more photodiodes cancel out, the correction
voltage gets applied to the base of Q2. Since the resistances are
nearly constant, rapid adjustment of the correction law is not required.
However, the unwanted degeneration applies at AC as well as DC, and
the attainable benefit is limited by phase shift and amplitude error
in the correction voltage. Thus I do need to form the correction in
analogue with as high a bandwidth as reasonably possible.
There\'ll be a cal table in flash, which will probably rely on the
AD5273\'s decent DNL to interpolate relatively coarsely between
steps--aiming for, say, 8-bit accuracy. That\'s potentially enough to
reduce the degeneration effect by 50 dB in the spherical cow universe.
Then there\'ll be a magic pushbutton on the box so that users in lab
settings can tell it that their experiment is all set up, so please
optimize the noise cancellation for these exact conditions. Nobody
will mind if that takes 5 seconds or so. (The command will be
available electronically as well--USB serial or maybe a dedicated
control line.)
The magic BFP640, with its ~1-kV Early voltage, excellent saturation
behaviour, and ultralow C_CB, allows all sorts of cute tricks. I\'m
dorking V_CE on one side of the diff pair in real time to force the
power dissipation of Q1 and Q2 to be equal irrespective of the
splitting ratio (within limits).
With some routed slots to control local temperature gradients, it
looks like I can get performance equivalent to a 40-GHz monolithic
dual. (We\'ll see how spherical the cows are in real life--I\'ve seen
some pretty fat ones.)
Fun.
Cheers
Phil Hobbs
(Who\'s stocking up on BFP640s as he did on BF862s)
By the way, I don\'t know if you\'ve seen this, but google and skywater
fab are open-sourcing the PDK for a 0.13um CMOS process, and google is
paying for some free shuttle runs, subject to certain rules including
that all designs be open-sourced too.
If you can think of anything that you really wish you could get on a
chip, and that can be made in CMOS, and that is useful to you but not
secret enough to not want to publish the design, now is the time!
Shuttle run in November and you get hundreds of parts back, so maybe
enough for a low-volume product. Lots of people are playing with the
tools so quite likely someone else would lay it out for fun if you
didn\'t have time.
There is a link to the slack workspace here, with many more details:
https://groups.google.com/forum/#!topic/skywater-pdk-announce/zijPNEsqsx4
Sounds like a good opportunity for sure. If somebody would do that with
a decent low-noise analogue bipolar process (say 0.5 um) I\'d be all over it.
Cheers
Phil Hobbs
--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC / Hobbs ElectroOptics
Optics, Electro-optics, Photonics, Analog Electronics
Briarcliff Manor NY 10510
http://electrooptical.net
http://hobbs-eo.com
P
Phil Hobbs
Guest
On 2020-07-23 22:16, Chris Jones wrote:
Sounds like a good opportunity for sure. If somebody would do that with
a decent low-noise analogue bipolar process (say 0.5 um) I\'d be all over it.
Cheers
Phil Hobbs
--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC / Hobbs ElectroOptics
Optics, Electro-optics, Photonics, Analog Electronics
Briarcliff Manor NY 10510
http://electrooptical.net
http://hobbs-eo.com
On 24/07/2020 09:14, Phil Hobbs wrote:
On 2020-07-23 16:25, Ricketty C wrote:
On Thursday, July 23, 2020 at 7:39:36 AM UTC-4, pcdh...@gmail.com
wrote:
I guess I\'m not following what this gains? You get lots more
steps, but >you don\'t know any more about where they are. What
am I missing?
What it gets me is a combination of settability and bandwidth that
I can\'t get in any single part at any price. I\'ll dump in a bit of
pseudorandom DNL and see if that causes any issues. I don\'t expect
it to--it\'ll get homogenized much like the regular steps.
For an iterative adjustment (think LC filter tuning) I can get
close by setting the fine pot to 0, adjusting the coarse pot, then
walking the two together to find the optimum. Near full scale the
possible search range is wider, but I don\'t think it\'ll take too
long provided that I\'m willing to settle for \"good enough\" rather
than a global optimum.
There are two mildly-interacting adjustments, but the response
surface is simple--no local minima.
It\'s for taking out the effect of extrinsic emitter resistance in
the BJT diff pair that\'s the heart of the circuit. It works by
applying a signal to one of the bases that cancels out the
effective emitter degeneration and so restores the desired
Ebers-Moll behaviour at higher photocurrents.
If I feel like getting fancy, once I\'ve found the right
neighbourhood I can give the turd a final polish to get a bit
closer.
There are non-negligible effects such as the tempco of wiper
resistance that limit how good this approach can be. Sure beats a
trimpot on a motor though!
Ok, so this circuit is not a real time control loop as much as it is
like a successive approximation. You don\'t mind the value varying
unpredictably as long as it eventually reaches a setting.
Right. It\'ll be done only occasionally, since R_E of a BJT is a weak
function of everything. In a diff pair, R_E produces degeneration,
which tends to make the current split by the ratios of the R_E values,
whereas we want it to do the Ebers-Moll thing and split strictly as
exp(delta V_BE/kT):1. R_E degeneration generally dominates the error
budget at higher photocurrents.
If transistors Q1 and Q2 have resistances R_E1 and R_E2, then the
required voltage is
dV_BEcor = I_E2 * R_E2Â - I_E1 * R_E1.
Since V_B1 is controlled by a feedback loop trying to make the total
DC current from two or more photodiodes cancel out, the correction
voltage gets applied to the base of Q2. Since the resistances are
nearly constant, rapid adjustment of the correction law is not required.
However, the unwanted degeneration applies at AC as well as DC, and
the attainable benefit is limited by phase shift and amplitude error
in the correction voltage. Thus I do need to form the correction in
analogue with as high a bandwidth as reasonably possible.
There\'ll be a cal table in flash, which will probably rely on the
AD5273\'s decent DNL to interpolate relatively coarsely between
steps--aiming for, say, 8-bit accuracy. That\'s potentially enough to
reduce the degeneration effect by 50 dB in the spherical cow universe.
Then there\'ll be a magic pushbutton on the box so that users in lab
settings can tell it that their experiment is all set up, so please
optimize the noise cancellation for these exact conditions. Nobody
will mind if that takes 5 seconds or so. (The command will be
available electronically as well--USB serial or maybe a dedicated
control line.)
The magic BFP640, with its ~1-kV Early voltage, excellent saturation
behaviour, and ultralow C_CB, allows all sorts of cute tricks. I\'m
dorking V_CE on one side of the diff pair in real time to force the
power dissipation of Q1 and Q2 to be equal irrespective of the
splitting ratio (within limits).
With some routed slots to control local temperature gradients, it
looks like I can get performance equivalent to a 40-GHz monolithic
dual. (We\'ll see how spherical the cows are in real life--I\'ve seen
some pretty fat ones.)
Fun.
Cheers
Phil Hobbs
(Who\'s stocking up on BFP640s as he did on BF862s)
By the way, I don\'t know if you\'ve seen this, but google and skywater
fab are open-sourcing the PDK for a 0.13um CMOS process, and google is
paying for some free shuttle runs, subject to certain rules including
that all designs be open-sourced too.
If you can think of anything that you really wish you could get on a
chip, and that can be made in CMOS, and that is useful to you but not
secret enough to not want to publish the design, now is the time!
Shuttle run in November and you get hundreds of parts back, so maybe
enough for a low-volume product. Lots of people are playing with the
tools so quite likely someone else would lay it out for fun if you
didn\'t have time.
There is a link to the slack workspace here, with many more details:
https://groups.google.com/forum/#!topic/skywater-pdk-announce/zijPNEsqsx4
Sounds like a good opportunity for sure. If somebody would do that with
a decent low-noise analogue bipolar process (say 0.5 um) I\'d be all over it.
Cheers
Phil Hobbs
--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC / Hobbs ElectroOptics
Optics, Electro-optics, Photonics, Analog Electronics
Briarcliff Manor NY 10510
http://electrooptical.net
http://hobbs-eo.com
B
Bill Sloman
Guest
On Friday, July 24, 2020 at 4:33:04 PM UTC+10, Phil Hobbs wrote:
<snip>
Analog Devices has a gorgeous 20-stage process which even delivers good quality PNP bipolar transistors. The chances of getting open-source access to that can\'t be good, but I suppose we could dream.
--
Bill Sloman, Sydney
<snip>
Analog Devices has a gorgeous 20-stage process which even delivers good quality PNP bipolar transistors. The chances of getting open-source access to that can\'t be good, but I suppose we could dream.
--
Bill Sloman, Sydney
B
Bill Sloman
Guest
On Friday, July 24, 2020 at 4:33:04 PM UTC+10, Phil Hobbs wrote:
<snip>
Analog Devices has a gorgeous 20-stage process which even delivers good quality PNP bipolar transistors. The chances of getting open-source access to that can\'t be good, but I suppose we could dream.
--
Bill Sloman, Sydney
<snip>
Analog Devices has a gorgeous 20-stage process which even delivers good quality PNP bipolar transistors. The chances of getting open-source access to that can\'t be good, but I suppose we could dream.
--
Bill Sloman, Sydney
B
Bill Sloman
Guest
On Friday, July 24, 2020 at 4:33:04 PM UTC+10, Phil Hobbs wrote:
<snip>
Analog Devices has a gorgeous 20-stage process which even delivers good quality PNP bipolar transistors. The chances of getting open-source access to that can\'t be good, but I suppose we could dream.
--
Bill Sloman, Sydney
<snip>
Analog Devices has a gorgeous 20-stage process which even delivers good quality PNP bipolar transistors. The chances of getting open-source access to that can\'t be good, but I suppose we could dream.
--
Bill Sloman, Sydney
C
Chris Jones
Guest
On 24/07/2020 16:48, Bill Sloman wrote:
It also has low tempco metal film resistors iirc, whereas polysilicon
resistors are nothing like that.
When I worked for them I never got to use it because the stuff I did had
to be cheap to make so was on more common processes. But, it is
surprising what can be achieved in bog standard CMOS with sufficient effort.
It also has low tempco metal film resistors iirc, whereas polysilicon
resistors are nothing like that.
When I worked for them I never got to use it because the stuff I did had
to be cheap to make so was on more common processes. But, it is
surprising what can be achieved in bog standard CMOS with sufficient effort.
C
Chris Jones
Guest
On 24/07/2020 16:48, Bill Sloman wrote:
It also has low tempco metal film resistors iirc, whereas polysilicon
resistors are nothing like that.
When I worked for them I never got to use it because the stuff I did had
to be cheap to make so was on more common processes. But, it is
surprising what can be achieved in bog standard CMOS with sufficient effort.
It also has low tempco metal film resistors iirc, whereas polysilicon
resistors are nothing like that.
When I worked for them I never got to use it because the stuff I did had
to be cheap to make so was on more common processes. But, it is
surprising what can be achieved in bog standard CMOS with sufficient effort.
C
Chris Jones
Guest
On 24/07/2020 16:48, Bill Sloman wrote:
It also has low tempco metal film resistors iirc, whereas polysilicon
resistors are nothing like that.
When I worked for them I never got to use it because the stuff I did had
to be cheap to make so was on more common processes. But, it is
surprising what can be achieved in bog standard CMOS with sufficient effort.
It also has low tempco metal film resistors iirc, whereas polysilicon
resistors are nothing like that.
When I worked for them I never got to use it because the stuff I did had
to be cheap to make so was on more common processes. But, it is
surprising what can be achieved in bog standard CMOS with sufficient effort.
C
Chris Jones
Guest
On 24/07/2020 16:32, Phil Hobbs wrote:
I\'d welcome ideas anyway. Even if there is only a small chance of it
working in CMOS, it might be worth trying, maybe even just on the corner
of someone else\'s chip.
I\'m mostly interested in trying something that takes little effort but
that could not be replicated easily using off-the-shelf parts. Maybe a
trigger comparator + adjustable delay + sampler with several channels,
for a sampling scope frontend. Even just a beefy inverter in 0.13um
might make a nice fast edge generator for testing scope risetime,
especially as it\'ll be a flipchip chipscale package thing so no
bondwires. If there is a usable bipolar then I might do a bandgap
reference / LDO and see what noise performance I can get from burning a
few mA rather than the few uA that they usually allow themselves. I
quite likely won\'t have time though.
On 2020-07-23 22:16, Chris Jones wrote:
On 24/07/2020 09:14, Phil Hobbs wrote:
On 2020-07-23 16:25, Ricketty C wrote:
On Thursday, July 23, 2020 at 7:39:36 AM UTC-4, pcdh...@gmail.com
wrote:
I guess I\'m not following what this gains? You get lots more
steps, but >you don\'t know any more about where they are. What
am I missing?
What it gets me is a combination of settability and bandwidth that
I can\'t get in any single part at any price. I\'ll dump in a bit of
pseudorandom DNL and see if that causes any issues. I don\'t expect
it to--it\'ll get homogenized much like the regular steps.
For an iterative adjustment (think LC filter tuning) I can get
close by setting the fine pot to 0, adjusting the coarse pot, then
walking the two together to find the optimum. Near full scale the
possible search range is wider, but I don\'t think it\'ll take too
long provided that I\'m willing to settle for \"good enough\" rather
than a global optimum.
There are two mildly-interacting adjustments, but the response
surface is simple--no local minima.
It\'s for taking out the effect of extrinsic emitter resistance in
the BJT diff pair that\'s the heart of the circuit. It works by
applying a signal to one of the bases that cancels out the
effective emitter degeneration and so restores the desired
Ebers-Moll behaviour at higher photocurrents.
If I feel like getting fancy, once I\'ve found the right
neighbourhood I can give the turd a final polish to get a bit
closer.
There are non-negligible effects such as the tempco of wiper
resistance that limit how good this approach can be. Sure beats a
trimpot on a motor though!
Ok, so this circuit is not a real time control loop as much as it is
like a successive approximation. You don\'t mind the value varying
unpredictably as long as it eventually reaches a setting.
Right. It\'ll be done only occasionally, since R_E of a BJT is a weak
function of everything. In a diff pair, R_E produces degeneration,
which tends to make the current split by the ratios of the R_E
values, whereas we want it to do the Ebers-Moll thing and split
strictly as exp(delta V_BE/kT):1. R_E degeneration generally
dominates the error budget at higher photocurrents.
If transistors Q1 and Q2 have resistances R_E1 and R_E2, then the
required voltage is
dV_BEcor = I_E2 * R_E2Â - I_E1 * R_E1.
Since V_B1 is controlled by a feedback loop trying to make the total
DC current from two or more photodiodes cancel out, the correction
voltage gets applied to the base of Q2. Since the resistances are
nearly constant, rapid adjustment of the correction law is not required.
However, the unwanted degeneration applies at AC as well as DC, and
the attainable benefit is limited by phase shift and amplitude error
in the correction voltage. Thus I do need to form the correction in
analogue with as high a bandwidth as reasonably possible.
There\'ll be a cal table in flash, which will probably rely on the
AD5273\'s decent DNL to interpolate relatively coarsely between
steps--aiming for, say, 8-bit accuracy. That\'s potentially enough to
reduce the degeneration effect by 50 dB in the spherical cow universe.
Then there\'ll be a magic pushbutton on the box so that users in lab
settings can tell it that their experiment is all set up, so please
optimize the noise cancellation for these exact conditions. Nobody
will mind if that takes 5 seconds or so. (The command will be
available electronically as well--USB serial or maybe a dedicated
control line.)
The magic BFP640, with its ~1-kV Early voltage, excellent saturation
behaviour, and ultralow C_CB, allows all sorts of cute tricks. I\'m
dorking V_CE on one side of the diff pair in real time to force the
power dissipation of Q1 and Q2 to be equal irrespective of the
splitting ratio (within limits).
With some routed slots to control local temperature gradients, it
looks like I can get performance equivalent to a 40-GHz monolithic
dual. (We\'ll see how spherical the cows are in real life--I\'ve seen
some pretty fat ones.)
Fun.
Cheers
Phil Hobbs
(Who\'s stocking up on BFP640s as he did on BF862s)
By the way, I don\'t know if you\'ve seen this, but google and skywater
fab are open-sourcing the PDK for a 0.13um CMOS process, and google is
paying for some free shuttle runs, subject to certain rules including
that all designs be open-sourced too.
If you can think of anything that you really wish you could get on a
chip, and that can be made in CMOS, and that is useful to you but not
secret enough to not want to publish the design, now is the time!
Shuttle run in November and you get hundreds of parts back, so maybe
enough for a low-volume product. Lots of people are playing with the
tools so quite likely someone else would lay it out for fun if you
didn\'t have time.
There is a link to the slack workspace here, with many more details:
https://groups.google.com/forum/#!topic/skywater-pdk-announce/zijPNEsqsx4
Sounds like a good opportunity for sure. If somebody would do that with
a decent low-noise analogue bipolar process (say 0.5 um) I\'d be all over
it.
Cheers
Phil Hobbs
I\'d welcome ideas anyway. Even if there is only a small chance of it
working in CMOS, it might be worth trying, maybe even just on the corner
of someone else\'s chip.
I\'m mostly interested in trying something that takes little effort but
that could not be replicated easily using off-the-shelf parts. Maybe a
trigger comparator + adjustable delay + sampler with several channels,
for a sampling scope frontend. Even just a beefy inverter in 0.13um
might make a nice fast edge generator for testing scope risetime,
especially as it\'ll be a flipchip chipscale package thing so no
bondwires. If there is a usable bipolar then I might do a bandgap
reference / LDO and see what noise performance I can get from burning a
few mA rather than the few uA that they usually allow themselves. I
quite likely won\'t have time though.
C
Chris Jones
Guest
On 24/07/2020 16:32, Phil Hobbs wrote:
I\'d welcome ideas anyway. Even if there is only a small chance of it
working in CMOS, it might be worth trying, maybe even just on the corner
of someone else\'s chip.
I\'m mostly interested in trying something that takes little effort but
that could not be replicated easily using off-the-shelf parts. Maybe a
trigger comparator + adjustable delay + sampler with several channels,
for a sampling scope frontend. Even just a beefy inverter in 0.13um
might make a nice fast edge generator for testing scope risetime,
especially as it\'ll be a flipchip chipscale package thing so no
bondwires. If there is a usable bipolar then I might do a bandgap
reference / LDO and see what noise performance I can get from burning a
few mA rather than the few uA that they usually allow themselves. I
quite likely won\'t have time though.
On 2020-07-23 22:16, Chris Jones wrote:
On 24/07/2020 09:14, Phil Hobbs wrote:
On 2020-07-23 16:25, Ricketty C wrote:
On Thursday, July 23, 2020 at 7:39:36 AM UTC-4, pcdh...@gmail.com
wrote:
I guess I\'m not following what this gains? You get lots more
steps, but >you don\'t know any more about where they are. What
am I missing?
What it gets me is a combination of settability and bandwidth that
I can\'t get in any single part at any price. I\'ll dump in a bit of
pseudorandom DNL and see if that causes any issues. I don\'t expect
it to--it\'ll get homogenized much like the regular steps.
For an iterative adjustment (think LC filter tuning) I can get
close by setting the fine pot to 0, adjusting the coarse pot, then
walking the two together to find the optimum. Near full scale the
possible search range is wider, but I don\'t think it\'ll take too
long provided that I\'m willing to settle for \"good enough\" rather
than a global optimum.
There are two mildly-interacting adjustments, but the response
surface is simple--no local minima.
It\'s for taking out the effect of extrinsic emitter resistance in
the BJT diff pair that\'s the heart of the circuit. It works by
applying a signal to one of the bases that cancels out the
effective emitter degeneration and so restores the desired
Ebers-Moll behaviour at higher photocurrents.
If I feel like getting fancy, once I\'ve found the right
neighbourhood I can give the turd a final polish to get a bit
closer.
There are non-negligible effects such as the tempco of wiper
resistance that limit how good this approach can be. Sure beats a
trimpot on a motor though!
Ok, so this circuit is not a real time control loop as much as it is
like a successive approximation. You don\'t mind the value varying
unpredictably as long as it eventually reaches a setting.
Right. It\'ll be done only occasionally, since R_E of a BJT is a weak
function of everything. In a diff pair, R_E produces degeneration,
which tends to make the current split by the ratios of the R_E
values, whereas we want it to do the Ebers-Moll thing and split
strictly as exp(delta V_BE/kT):1. R_E degeneration generally
dominates the error budget at higher photocurrents.
If transistors Q1 and Q2 have resistances R_E1 and R_E2, then the
required voltage is
dV_BEcor = I_E2 * R_E2Â - I_E1 * R_E1.
Since V_B1 is controlled by a feedback loop trying to make the total
DC current from two or more photodiodes cancel out, the correction
voltage gets applied to the base of Q2. Since the resistances are
nearly constant, rapid adjustment of the correction law is not required.
However, the unwanted degeneration applies at AC as well as DC, and
the attainable benefit is limited by phase shift and amplitude error
in the correction voltage. Thus I do need to form the correction in
analogue with as high a bandwidth as reasonably possible.
There\'ll be a cal table in flash, which will probably rely on the
AD5273\'s decent DNL to interpolate relatively coarsely between
steps--aiming for, say, 8-bit accuracy. That\'s potentially enough to
reduce the degeneration effect by 50 dB in the spherical cow universe.
Then there\'ll be a magic pushbutton on the box so that users in lab
settings can tell it that their experiment is all set up, so please
optimize the noise cancellation for these exact conditions. Nobody
will mind if that takes 5 seconds or so. (The command will be
available electronically as well--USB serial or maybe a dedicated
control line.)
The magic BFP640, with its ~1-kV Early voltage, excellent saturation
behaviour, and ultralow C_CB, allows all sorts of cute tricks. I\'m
dorking V_CE on one side of the diff pair in real time to force the
power dissipation of Q1 and Q2 to be equal irrespective of the
splitting ratio (within limits).
With some routed slots to control local temperature gradients, it
looks like I can get performance equivalent to a 40-GHz monolithic
dual. (We\'ll see how spherical the cows are in real life--I\'ve seen
some pretty fat ones.)
Fun.
Cheers
Phil Hobbs
(Who\'s stocking up on BFP640s as he did on BF862s)
By the way, I don\'t know if you\'ve seen this, but google and skywater
fab are open-sourcing the PDK for a 0.13um CMOS process, and google is
paying for some free shuttle runs, subject to certain rules including
that all designs be open-sourced too.
If you can think of anything that you really wish you could get on a
chip, and that can be made in CMOS, and that is useful to you but not
secret enough to not want to publish the design, now is the time!
Shuttle run in November and you get hundreds of parts back, so maybe
enough for a low-volume product. Lots of people are playing with the
tools so quite likely someone else would lay it out for fun if you
didn\'t have time.
There is a link to the slack workspace here, with many more details:
https://groups.google.com/forum/#!topic/skywater-pdk-announce/zijPNEsqsx4
Sounds like a good opportunity for sure. If somebody would do that with
a decent low-noise analogue bipolar process (say 0.5 um) I\'d be all over
it.
Cheers
Phil Hobbs
I\'d welcome ideas anyway. Even if there is only a small chance of it
working in CMOS, it might be worth trying, maybe even just on the corner
of someone else\'s chip.
I\'m mostly interested in trying something that takes little effort but
that could not be replicated easily using off-the-shelf parts. Maybe a
trigger comparator + adjustable delay + sampler with several channels,
for a sampling scope frontend. Even just a beefy inverter in 0.13um
might make a nice fast edge generator for testing scope risetime,
especially as it\'ll be a flipchip chipscale package thing so no
bondwires. If there is a usable bipolar then I might do a bandgap
reference / LDO and see what noise performance I can get from burning a
few mA rather than the few uA that they usually allow themselves. I
quite likely won\'t have time though.
C
Chris Jones
Guest
On 24/07/2020 16:32, Phil Hobbs wrote:
I\'d welcome ideas anyway. Even if there is only a small chance of it
working in CMOS, it might be worth trying, maybe even just on the corner
of someone else\'s chip.
I\'m mostly interested in trying something that takes little effort but
that could not be replicated easily using off-the-shelf parts. Maybe a
trigger comparator + adjustable delay + sampler with several channels,
for a sampling scope frontend. Even just a beefy inverter in 0.13um
might make a nice fast edge generator for testing scope risetime,
especially as it\'ll be a flipchip chipscale package thing so no
bondwires. If there is a usable bipolar then I might do a bandgap
reference / LDO and see what noise performance I can get from burning a
few mA rather than the few uA that they usually allow themselves. I
quite likely won\'t have time though.
On 2020-07-23 22:16, Chris Jones wrote:
On 24/07/2020 09:14, Phil Hobbs wrote:
On 2020-07-23 16:25, Ricketty C wrote:
On Thursday, July 23, 2020 at 7:39:36 AM UTC-4, pcdh...@gmail.com
wrote:
I guess I\'m not following what this gains? You get lots more
steps, but >you don\'t know any more about where they are. What
am I missing?
What it gets me is a combination of settability and bandwidth that
I can\'t get in any single part at any price. I\'ll dump in a bit of
pseudorandom DNL and see if that causes any issues. I don\'t expect
it to--it\'ll get homogenized much like the regular steps.
For an iterative adjustment (think LC filter tuning) I can get
close by setting the fine pot to 0, adjusting the coarse pot, then
walking the two together to find the optimum. Near full scale the
possible search range is wider, but I don\'t think it\'ll take too
long provided that I\'m willing to settle for \"good enough\" rather
than a global optimum.
There are two mildly-interacting adjustments, but the response
surface is simple--no local minima.
It\'s for taking out the effect of extrinsic emitter resistance in
the BJT diff pair that\'s the heart of the circuit. It works by
applying a signal to one of the bases that cancels out the
effective emitter degeneration and so restores the desired
Ebers-Moll behaviour at higher photocurrents.
If I feel like getting fancy, once I\'ve found the right
neighbourhood I can give the turd a final polish to get a bit
closer.
There are non-negligible effects such as the tempco of wiper
resistance that limit how good this approach can be. Sure beats a
trimpot on a motor though!
Ok, so this circuit is not a real time control loop as much as it is
like a successive approximation. You don\'t mind the value varying
unpredictably as long as it eventually reaches a setting.
Right. It\'ll be done only occasionally, since R_E of a BJT is a weak
function of everything. In a diff pair, R_E produces degeneration,
which tends to make the current split by the ratios of the R_E
values, whereas we want it to do the Ebers-Moll thing and split
strictly as exp(delta V_BE/kT):1. R_E degeneration generally
dominates the error budget at higher photocurrents.
If transistors Q1 and Q2 have resistances R_E1 and R_E2, then the
required voltage is
dV_BEcor = I_E2 * R_E2Â - I_E1 * R_E1.
Since V_B1 is controlled by a feedback loop trying to make the total
DC current from two or more photodiodes cancel out, the correction
voltage gets applied to the base of Q2. Since the resistances are
nearly constant, rapid adjustment of the correction law is not required.
However, the unwanted degeneration applies at AC as well as DC, and
the attainable benefit is limited by phase shift and amplitude error
in the correction voltage. Thus I do need to form the correction in
analogue with as high a bandwidth as reasonably possible.
There\'ll be a cal table in flash, which will probably rely on the
AD5273\'s decent DNL to interpolate relatively coarsely between
steps--aiming for, say, 8-bit accuracy. That\'s potentially enough to
reduce the degeneration effect by 50 dB in the spherical cow universe.
Then there\'ll be a magic pushbutton on the box so that users in lab
settings can tell it that their experiment is all set up, so please
optimize the noise cancellation for these exact conditions. Nobody
will mind if that takes 5 seconds or so. (The command will be
available electronically as well--USB serial or maybe a dedicated
control line.)
The magic BFP640, with its ~1-kV Early voltage, excellent saturation
behaviour, and ultralow C_CB, allows all sorts of cute tricks. I\'m
dorking V_CE on one side of the diff pair in real time to force the
power dissipation of Q1 and Q2 to be equal irrespective of the
splitting ratio (within limits).
With some routed slots to control local temperature gradients, it
looks like I can get performance equivalent to a 40-GHz monolithic
dual. (We\'ll see how spherical the cows are in real life--I\'ve seen
some pretty fat ones.)
Fun.
Cheers
Phil Hobbs
(Who\'s stocking up on BFP640s as he did on BF862s)
By the way, I don\'t know if you\'ve seen this, but google and skywater
fab are open-sourcing the PDK for a 0.13um CMOS process, and google is
paying for some free shuttle runs, subject to certain rules including
that all designs be open-sourced too.
If you can think of anything that you really wish you could get on a
chip, and that can be made in CMOS, and that is useful to you but not
secret enough to not want to publish the design, now is the time!
Shuttle run in November and you get hundreds of parts back, so maybe
enough for a low-volume product. Lots of people are playing with the
tools so quite likely someone else would lay it out for fun if you
didn\'t have time.
There is a link to the slack workspace here, with many more details:
https://groups.google.com/forum/#!topic/skywater-pdk-announce/zijPNEsqsx4
Sounds like a good opportunity for sure. If somebody would do that with
a decent low-noise analogue bipolar process (say 0.5 um) I\'d be all over
it.
Cheers
Phil Hobbs
I\'d welcome ideas anyway. Even if there is only a small chance of it
working in CMOS, it might be worth trying, maybe even just on the corner
of someone else\'s chip.
I\'m mostly interested in trying something that takes little effort but
that could not be replicated easily using off-the-shelf parts. Maybe a
trigger comparator + adjustable delay + sampler with several channels,
for a sampling scope frontend. Even just a beefy inverter in 0.13um
might make a nice fast edge generator for testing scope risetime,
especially as it\'ll be a flipchip chipscale package thing so no
bondwires. If there is a usable bipolar then I might do a bandgap
reference / LDO and see what noise performance I can get from burning a
few mA rather than the few uA that they usually allow themselves. I
quite likely won\'t have time though.