Creating new operators

[Paul Taylor]

On Wed, 30 Jul 2008 21:06:42 +0200, Antonio Pasini wrote:

(even for FSMs, I found good and clean code even easier to read than an
huge bubble diagram...)

I guess someone must find state-machine diagram software useful, that will
auto-generate code from a diagram for you.

Especially for long chains of pipelined stages... keeping
track of how
many delays I need to put for that long forgotten control signal..

That's why FPGA design is really harder than writing C programs,
because all your signals have to come out at the right time in relation to
each other. Even if your had a perfect HDL, FPGA design would still be
difficult compared to software. VHDL's verbose, but on a file by file
basis, the verbosity I don't think obscures the intention of the code - the
verbosity is just tedious.

The other thing that makes FPGA design hard is that the tools implement
different parts of the VHDL standard. Like recently when I had to take
variables out of a process, and convert them to signals, because XST
didn't like them, but the simulator did - pain in the arse.

Paul.

 

[Andy]

On Jul 30, 10:25 am, rickman <gnu...@gmail.com> wrote:

One other point. I don't write code for beginners to understand. I
write for a typical programmer or sometimes just for myself. I do
want the code to be readable, but I don't feel a need to "dumb" it
down for others.

Rick

I think that's one of the points some of us are trying to get at. The
verilog syntax you seek is not well understood by a vhdl audience..
Write your code where only you can read it, and you will have to
maintain it, because no one else can (that may be a goal, but not for
me). Many of us work in environments which require peer reviews, where
making the code more easily readable by others (programmers, but maybe
not experts) pays dividends.

I prefer to write code that expresses the behavior more clearly, if
not necessarily the implemented structure. Different synthesis tools,
target architectures or optimization goals may result in different
implementations, which is fine as long as they meet timing/resource
requirements and match the RTL behavior. When they do not meet timing
or resource requirements, then (and only then) I revert to trying to
coax the implementation I have in mind out of the synthesis tool, by
modifying the code structure to get the implementation I want.

Andy

 

[rickman]

On Jul 30, 5:57 pm, Andy <jonesa...@comcast.net> wrote:

On Jul 30, 10:25 am, rickman <gnu...@gmail.com> wrote:



One other point. I don't write code for beginners to understand. I
write for a typical programmer or sometimes just for myself. I do
want the code to be readable, but I don't feel a need to "dumb" it
down for others.

Rick

I think that's one of the points some of us are trying to get at.

I understand the point, very well. I just don't agree. No one has
made any significant argument to support that point. I just see a lot
of hand waving and overstatement.

The
verilog syntax you seek is not well understood by a vhdl audience..

Duh! It is not part of VHDL. I am suggesting that it become part of
VHDL. Then no one would have the excuse that it is not VHDL so I
don't know it.

Write your code where only you can read it, and you will have to
maintain it, because no one else can (that may be a goal, but not for
me). Many of us work in environments which require peer reviews, where
making the code more easily readable by others (programmers, but maybe
not experts) pays dividends.

Here is an example of overstatement. Are you really suggesting that
the code we are discussing would be so obtuse that "only you can read
it"??? I think that is overstated to the point of absurdity. Yes, it
may take someone a few seconds or possibly even minutes the first time
to look up the command. But if they have to look it up more than once
or can't remember it, then the problem is not due to my use of the
command...

I prefer to write code that expresses the behavior more clearly, if
not necessarily the implemented structure. Different synthesis tools,
target architectures or optimization goals may result in different
implementations, which is fine as long as they meet timing/resource
requirements and match the RTL behavior. When they do not meet timing
or resource requirements, then (and only then) I revert to trying to
coax the implementation I have in mind out of the synthesis tool, by
modifying the code structure to get the implementation I want.

I agree. The behavior I wanted to describe was a mux feeding an AND
gate. Obviously this was not an implementation since these constructs
don't exist in the FPGA. I just want the simplest and concise
description that is easy to read and I think that the sel?a:b
construct fits that need.

Rick

 

[Rob Gaddi]

rickman wrote:

other things in addition to...

I agree. The behavior I wanted to describe was a mux feeding an AND
gate. Obviously this was not an implementation since these constructs
don't exist in the FPGA. I just want the simplest and concise
description that is easy to read and I think that the sel?a:b
construct fits that need.

Rick

I think my main problem with the ?: operator is the same as my problem
with goto statements and implicit type casting. It's not an inherently
problematic device, and can at times be the clearest way of getting the
point across, but it lends itself to abuse. I've certainly seen 10x as
much C code obfuscated by some "clever" use of ?: than I've seen code
clarified by it.

It's like a driver notification device that warns you you're going over
70 mph by crescendoing "Ride of the Valkyries". Theoretically it's a
fine tool, but practically it's just begging you floor it for maximum
effect.

--
Rob Gaddi, Highland Technology
Email address is currently out of order

 

[Paul Taylor]

On Thu, 31 Jul 2008 09:26:10 -0700, Rob Gaddi wrote:

I think my main problem with the ?: operator is the same as my problem
with goto statements and implicit type casting. It's not an inherently
problematic device, and can at times be the clearest way of getting the
point across, but it lends itself to abuse. I've certainly seen 10x as
much C code obfuscated by some "clever" use of ?: than I've seen code
clarified by it.

I've only seen the ?: badly used once. It was in C code, coded by a guy
who used to have all his C code in one file, and who when designed his
FPGAs had loads of clocks everywhere resulting in asynchronous problems.
I don't think people like that should be the reason why abusable
constructs shouldn't find there way into a language, expecially if there
are just a few of them - if there were loads of abusable fetaures then
that's different.

In a work environment, if you have coding standards and reviews as part of
the design process, then problems shouldn't occur. Maybe lint could also
help?

Most recently, my use of the ?: operator has been when writing some
Tcl programs, and I wouldn't want to give it up there.

Paul

 

[Paul Taylor]

On Thu, 31 Jul 2008 11:44:58 -0700, rickman wrote:

Can you give a reasonable example of how the ?: operator has been
misused in a way that can't be done with other operators?

They can be chained, it can make a right mess. Do a google search for
chained ternary operator.

Paul.

 

[Paul Taylor]

On Thu, 31 Jul 2008 20:07:41 +0100, Paul Taylor wrote:

They can be chained, it can make a right mess. Do a google search for
chained ternary operator.

From searching the net, other use of ?: that can cause confusion is when it
spans more than one line

 

[rickman]

On Jul 31, 12:26 pm, Rob Gaddi <rga...@technologyhighland.com> wrote:

I think my main problem with the ?: operator is the same as my problem
with goto statements and implicit type casting. It's not an inherently
problematic device, and can at times be the clearest way of getting the
point across, but it lends itself to abuse. I've certainly seen 10x as
much C code obfuscated by some "clever" use of ?: than I've seen code
clarified by it.

It's like a driver notification device that warns you you're going over
70 mph by crescendoing "Ride of the Valkyries". Theoretically it's a
fine tool, but practically it's just begging you floor it for maximum
effect.

Nice illustration. But I don't see how it applies??? What construct
in VHDL or Verilog can't be misused??? The reason that I prefer
the ?: operator is because the resulting use of the conditional
assignment or the required IF ELSE THEN construct can be "misused" in
that it can obscure the purpose of what you are doing.

Can you give a reasonable example of how the ?: operator has been
misused in a way that can't be done with other operators?

Rick

 

[rickman]

On Jul 31, 3:40 pm, Paul Taylor <pt@false_email.co.uk> wrote:

On Thu, 31 Jul 2008 20:07:41 +0100, Paul Taylor wrote:
They can be chained, it can make a right mess. Do a google search for
chained ternary operator.

From searching the net, other use of ?: that can cause confusion is when it
spans more than one line

I can't say that I give either of these examples much importance.
Both examples of poor usage can create messes of logic no matter what
operator is being used. This just seems to me to be a specious
argument.

a <= alongvariablename or blongvariablename and
clongvariablename xor dlongvariablename and elongvariablename
or flongvariablename;

Rick