cpu 8051 dalton vhdl translated to verilog

[beky4kr@gmail.com]

http://bknpk.no-ip.biz/cpu_8051_ver/top.html
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Stable Design: The design is translated from a VHDL dalton
project http://www.cs.ucr.edu/~dalton/i8051/i8051syn.
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Small Design: Consumes only 324 Flip-Flops: map report
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Fast Design: 50MHz for a xc4vlx25-10 XILINX device: timing
report
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Synthesized to XILINX: synthesis scripts
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Memories suited for XILINX device for small code (ROM256X1 and
RAM128X1S_1).
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Set of scripts to convert between assembly to XILINX defparam
u_rom0.INIT=256'h000000...
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Script to compile and simulated with free icarus verilog
simulator.verilog compilation script
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verilog code verilog code