Counter clocks on both edges sometimes, but not when differe

[Mr.CRC]

Pete Fraser wrote:

Brian Drummond wrote:
On Tue, 17 May 2011 06:40:07 -0700, rickman wrote:

this is working well for my kayaking schedule. :^)

Heh, you too, huh?

Is there some requirement that FPGA coders
are also kayakers?

Pete Fraser
Looksha IV HV

No, only that you can only ever use one clock. ;-)



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_____________________
Mr.CRC
crobcBOGUS@REMOVETHISsbcglobal.net
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[KJ]

On May 18, 11:21 pm, "Mr.CRC" <crobcBO...@REMOVETHISsbcglobal.net>
wrote:

Pete Fraser wrote:
Is there some requirement that FPGA coders
are also kayakers?

Pete Fraser
Looksha IV HV

No, only that you can only ever use one clock. ;-)

Not true. FPGAs implement dual clock FIFOs and memories just fine.

Kevin Jennings