Correct VHDL?

Hello,
I want to implement the following C++ code in VHDL

double t1 = u1 * ip1[i1] - u2 * op1[i1];
double t2 = u1 * op1[i1] + u2 * ip1[i1];
ip1[i1] = ip3 - t1;
op1[i1] = ip4 - t2;
ip3 += t1;
ip4 += t2;

i am not sure if this is correct but i have tried and came up with the
following VHDL

entity test is
port( clk : in std_logic;
ip1 : in std_logic_vector(7 downto 0);
op1 : in std_logic_vector(7 downto 0);
ip3 : in std_logic_vector(7 downto 0);
ip4 : in std_logic_vector(7 downto 0);
U1 : in std_logic_vector(7 downto 0);
U2 : in std_logic_vector(7 downto 0);
ip1o : out std_logic_vector(15 downto 0);
op1o : out std_logic_vector(15 downto 0);
ip3o : out std_logic_vector(15 downto 0);
ip4o : out std_logic_vector(15 downto 0));
end test;

architecture Behavioral of test is
signal T1 : std_logic_vector(15 downto 0);
signal T2 : std_logic_vector(15 downto 0);
begin

process(clk)
begin
T1 <= (U1 * ip1) - (U2 * op1);
T2 <= (U1 * op1) + (U2 * ip1);
ip1o <= ip3 - T1;
op1o <= ip4 - T2;
ip3o <= ip3 + T1;
ip4o <= ip4 + T2;
end process;

end Behavioral;

i would really appreciate if some one can tell me is it correct, if
not how can it be implemented correctly in VHDL?

further i want to implement this code in a sort of variable loop, i.e.
depending on the values of the output the length of the loop will
change. For example consider the following c++ code

for (int a=0; a<=100; a++)
{
i1 = i2;
i2 *= 2;
for (int i=i1; i<=k; i++)
{
//some code here;
}
}

could this be implemented in VHDL?

Thanks

 

[Rob Gaddi]

On Fri, 27 Mar 2009 06:12:24 -0700 (PDT)
mightycatniyander@gmail.com wrote:

Hello,
I want to implement the following C++ code in VHDL

double t1 = u1 * ip1[i1] - u2 * op1[i1];
double t2 = u1 * op1[i1] + u2 * ip1[i1];
ip1[i1] = ip3 - t1;
op1[i1] = ip4 - t2;
ip3 += t1;
ip4 += t2;

i am not sure if this is correct but i have tried and came up with the
following VHDL

entity test is
port( clk : in std_logic;
ip1 : in std_logic_vector(7 downto 0);
op1 : in std_logic_vector(7 downto 0);
ip3 : in std_logic_vector(7 downto 0);
ip4 : in std_logic_vector(7 downto 0);
U1 : in std_logic_vector(7 downto 0);
U2 : in std_logic_vector(7 downto 0);
ip1o : out std_logic_vector(15 downto 0);
op1o : out std_logic_vector(15 downto 0);
ip3o : out std_logic_vector(15 downto 0);
ip4o : out std_logic_vector(15 downto 0));
end test;

architecture Behavioral of test is
signal T1 : std_logic_vector(15 downto 0);
signal T2 : std_logic_vector(15 downto 0);
begin

process(clk)
begin
T1 <= (U1 * ip1) - (U2 * op1);
T2 <= (U1 * op1) + (U2 * ip1);
ip1o <= ip3 - T1;
op1o <= ip4 - T2;
ip3o <= ip3 + T1;
ip4o <= ip4 + T2;
end process;

end Behavioral;

i would really appreciate if some one can tell me is it correct, if
not how can it be implemented correctly in VHDL?

No, it's not correct.

First of all, you're trying to perform arithmatic on std_logic_vectors,
with no libraries linked in. The std_logic_arith library will allow
you to do that, but shouldn't, as it completely throws away any concept
of typing. The numeric_std library lets you do things properly, but
you'll need to explicitly cast your std_logic_vectors to signed or
unsigned accordingly.

Secondly you've missed the concept of signal assignments in a clocked
process, which is that all signal assignment happens all at once, on
the clock edge. In the code you've written, T1 is modified on one
clock edge, and then ip1o is updated with the current value of ip3, but
the previously calculated value of T1. If you really want to define
intermediate values that are updated immediately, you want to use
variables instead.

Also, of course, is the issue that your C defines T1 and T2 as doubles,
implying floating point math. While floating point is possible in
hardware, generally the belief that you need it is an indication that
you don't understand your problem. God only knows what types you think
the intermediate values are.

Stop thinking of this as code. It's not. It's a hardware description
language, it describes hardware. Get a quad pad, or preferably D size
vellum. Draw out the hardware schematic. Be SPECIFIC as to what each
piece of hardware is, and how it would be implemented on the target
fabric. Then start writing the HDL to appropriately describe what's
supposed to happen. Writing higher level, more abstract code, is a
time-saving convenience that should be reserved for people who fully
and completely understand the lower level situation.

--
Rob Gaddi, Highland Technology
Email address is currently out of order

 

[Mike Treseler]

Rob Gaddi wrote:

No, it's not correct.

you're trying to perform arithmetic on std_logic_vectors,
with no libraries linked in. The std_logic_arith library will allow
you to do that, but shouldn't, as it completely throws away any concept
of typing.

Actually it's the the synopsys
std_logic_unsigned and
std_logic_signed packages
that attempt math on std_logic_vectors.
These packages do not play nice with each other
or with the standard comparison operators.

The std_logic_arith package causes less havoc because
it requires the use signed and unsigned types.
Users of the synopsys "verilog subset" rarely employ these.

-- Mike Treseler