P
Phil Hobbs
Guest
John Larkin <jlarkin@highlandSNIPMEtechnology.com> wrote:
Trouble is, thermal conduction is proportional to the temperature gradient,
and thereâs no way for a spreader to make the heat flow preferentially into
the cooler die.
They really need to be interleaved on a single chip for good matching
above, say, 50 uW dissipation.
Thatâs not at all hard to do, but virtually no one does it anymore.
There are various semicustom array offerings, but the devices available
arenât exactly cutting edge, unfortunately.
Cheers
Phil Hobbs
--
Dr Philip C D Hobbs Principal Consultant ElectroOptical Innovations LLC /
Hobbs ElectroOptics Optics, Electro-optics, Photonics, Analog Electronics
On Tue, 20 Jun 2023 09:13:14 -0700 (PDT), whit3rd <whit3rd@gmail.com
wrote:
On Tuesday, June 20, 2023 at 7:31:09?AM UTC-7, Phil Hobbs wrote:
On 2023-06-19 23:18, Gerhard Hoffmann wrote:
Am 19.06.23 um 23:30 schrieb Phil Hobbs:
John Larkin <jla...@highlandSNIPMEtechnology.com> wrote:
On Mon, 19 Jun 2023 17:08:58 +0100, Brian Gregory
void-invalid...@email.invalid> wrote:
On 19/06/2023 11:25, John Larkin wrote:
If someone suggests a current mirror, it\'s probably a bad idea.
Yes. AIUI they\'re more something that gets built in to integrated
circuits since they don\'t work well when built from discrete components
because they\'re not exactly matched, and not thermally linked together.
Exact is a relative term; thermally linked is also a relative term, you can glue
two TO92\'s together and they ARE linked, thermally and physically: it
works better with C1841 NPN transistors than with PN2222\'s, because
the Japanese case has its metal tab oriented differently.
Most dual transistors are really two die, not thermally coupled.
That\'s a packaging issue.
Discrete transistor designs have the collector as the substrate, so
you can\'t easily electrically separate collectors of two transistors mounted
to the same metal plate. To make a good-quality dual, epitaxial
silicon grown over oxide can be electrically isolated, OR you need
a seven-pin package, so you can bias the substrate (as an IC would
do) to create a depletion region. Things like LM13700 have the
specified bias on that most-negative pin in order to work,
as did the (hard-to-find) transistor multiples of yesteryear (CA3046, anyone?).
A pure-silicon current mirror runs one transistor at 0.6ish volts and
low dissipation, and the other at whatever Vce and higher dissipation,
so tight thermal coupling is mandatory.
Really good monolithic pairs have many equivalent transistors
interleaved in a tricky pattern.
I guess you could bolt two TO-220s or TO-247s metal-to-metal with a
thin AlN insulator.
Trouble is, thermal conduction is proportional to the temperature gradient,
and thereâs no way for a spreader to make the heat flow preferentially into
the cooler die.
They really need to be interleaved on a single chip for good matching
above, say, 50 uW dissipation.
Thatâs not at all hard to do, but virtually no one does it anymore.
There are various semicustom array offerings, but the devices available
arenât exactly cutting edge, unfortunately.
Cheers
Phil Hobbs
--
Dr Philip C D Hobbs Principal Consultant ElectroOptical Innovations LLC /
Hobbs ElectroOptics Optics, Electro-optics, Photonics, Analog Electronics