Conditional Compile Generate statements

[Cory Shol]

I have a project that Two FPGA's use the same VHDL code.
I have a Global constant that if:
SIDE_DEFINE = '0' it will compile FPGA one logic.
SIDE_DEFINE = '1' it will compile FPGA two logic.

Can I instantiate multiple components in a single generate?
i.e.

generate_FPGA1 : if(SIDE_DEFINE='0') generate

comp1 : component_one
port map(
clk => clk1,
input => input1,
output => output1
);

comp2 : component_2
port map(
clk => clk2,
input => input2,
output => output2
);

end generate generate_FPGA1;

generate_FPGA1 : if(SIDE_DEFINE='1') generate

comp1 : component_one
port map(
clk => clk2,
input => input2,
output => output2
);

comp2 : component_2
port map(
clk => clk1,
input => input1,
output => output1
);

end generate generate_FPGA1;

or do i have to:

generate_FPGA1_comp1 : if(SIDE_DEFINE='0') generate

comp1 : component_one
port map(
clk => clk1,
input => input1,
output => output1
);

end generate generate_FPGA1_comp1;

generate_FPGA1_comp2 : if(SIDE_DEFINE='0') generate
comp2 : component_2
port map(
clk => clk2,
input => input2,
output => output2
);

end generate generate_FPGA1_comp2;

Thanks

 

[Andy]

A generate statement may contain any number of concurrent statements: component/entity instantiations, concurrent signal assignment statements, process statements, etc.

BTW, the VHDL generate statement does not accomplish "conditional compilation". The contained statements are always compiled, but if the conditional is false, they are not elaborated (in SW terms, they are not "linked"). Any statements must be legal VHDL, and all referenced objects must exist.

If your tools support vhdl-2008, enhanced generate statements are available:

You can now include "else generate" and "elsif <condition> generate" in if-generate statements.

"Case <expr> generate ... end generate;" is also available.

Consult your tools' reference guides to see what vhdl-2008 features are supported. If a 2008 feature you want to use is not supported, then let your vendor(s) know you want it!

Andy

 

[Cory Shol]

On Wednesday, July 24, 2013 12:23:33 PM UTC-5, Andy wrote:

A generate statement may contain any number of concurrent statements: component/entity instantiations, concurrent signal assignment statements, process statements, etc.



BTW, the VHDL generate statement does not accomplish "conditional compilation". The contained statements are always compiled, but if the conditional is false, they are not elaborated (in SW terms, they are not "linked"). Any statements must be legal VHDL, and all referenced objects must exist.



If your tools support vhdl-2008, enhanced generate statements are available:



You can now include "else generate" and "elsif <condition> generate" in if-generate statements.



"Case <expr> generate ... end generate;" is also available.



Consult your tools' reference guides to see what vhdl-2008 features are supported. If a 2008 feature you want to use is not supported, then let your vendor(s) know you want it!



Andy

If SIDE_DEFINE is a constant, will the tools compile out the unused logic??

If you have two generate and one will never be true since the constant is initialized, the tools should never include the logic in the final design therefore isn't it a conditional compile??

 

[Cory Shol]

On Wednesday, July 24, 2013 12:37:28 PM UTC-5, Cory Shol wrote:

On Wednesday, July 24, 2013 12:23:33 PM UTC-5, Andy wrote:

A generate statement may contain any number of concurrent statements: component/entity instantiations, concurrent signal assignment statements, process statements, etc.







BTW, the VHDL generate statement does not accomplish "conditional compilation". The contained statements are always compiled, but if the conditional is false, they are not elaborated (in SW terms, they are not "linked"). Any statements must be legal VHDL, and all referenced objects must exist.







If your tools support vhdl-2008, enhanced generate statements are available:







You can now include "else generate" and "elsif <condition> generate" in if-generate statements.







"Case <expr> generate ... end generate;" is also available.







Consult your tools' reference guides to see what vhdl-2008 features are supported. If a 2008 feature you want to use is not supported, then let your vendor(s) know you want it!







Andy



If SIDE_DEFINE is a constant, will the tools compile out the unused logic??



If you have two generate and one will never be true since the constant is initialized, the tools should never include the logic in the final design therefore isn't it a conditional compile??

How else do you do a conditional compile in VHDL?

 

[Andy]

Cory,

All generics are elaboration-time constants, and therefore their effects are optimized. Any circuit description that is dependent upon a generic-based condition is not implemented by the synthesis tool if the condition is not true.

Andy

 

[Andy]

Cory,

Conditional compilation for most languages is accomplished through a text preprocessor that alters the source code before it gets to the compiler. Therefore the pre-altered source code need not even be legal syntax for the compiler, so long as the pre-processor makes it legal (or removes it). This is how C and Verilog do conditional compilation, using 'define macros, etc.

Do not confuse synthesis with compilation. Compilation is only the first synthesis step, fallowed by one or more mapping and optimization stages. All VHDL code is compiled, but some of the compiled code may be optimized or mapped to nothing, depending on static (known at synthesis time) values.

For Synplify Pro, if you have if-generate statements, their effects (e.g. multiplexers and controlling ciruitry) are shown in the RTL-level view of the design, but they are optimized out during mapping, and are not present in the Technology (gate-level) view, nor in the gate level netlist. So at Synplify performs the elaboration phase during mapping. This may not be true for other synthesis tools, which may combine elaboration with compilation.

A good example of the difference between a "static" value in VHDL simulation(usually a constant, generic, literal, etc.) and a "static" value in synthesis is in the index of a for-loop. For VHDL simulation, the loop index is a dynamic value that takes on different values at different times. For synthesis, loops are always automatically unrolled, and therefore each reference to the loop index after unrolling is a static value which is then optimized.

Andy