J
Jim Lewis
Guest
Eli
The following paper gives some background on the approach (towards
the end) as well as some ideas how to apply the approach to a chip
level as well as a function level test environment.
http://www.synthworks.com/papers/VHDL_Subblock_Verification_DesignCon_2003_P.pdf
There are a number of things I have refined quite a bit. I have added
resolved types for integers, real, and time (so they can also be used in
the record). I have added some verification data structures for
scoreboards, memories, and for simplifying randomization. The use of uniform
can get some simple things done, but it is much simpler when you add
layers on top. I am working on a book, but it is progressing slower
than I would like (as I wanted it done already). So for the mean time
if you are interested in the materials, you would have to take our
VHDL Testbenches and Verification class.
Best,
Jim
record with resolved elements.
The following paper gives some background on the approach (towards
the end) as well as some ideas how to apply the approach to a chip
level as well as a function level test environment.
http://www.synthworks.com/papers/VHDL_Subblock_Verification_DesignCon_2003_P.pdf
There are a number of things I have refined quite a bit. I have added
resolved types for integers, real, and time (so they can also be used in
the record). I have added some verification data structures for
scoreboards, memories, and for simplifying randomization. The use of uniform
can get some simple things done, but it is much simpler when you add
layers on top. I am working on a book, but it is progressing slower
than I would like (as I wanted it done already). So for the mean time
if you are interested in the materials, you would have to take our
VHDL Testbenches and Verification class.
Best,
Jim