J
Jonathan Bromley
Guest
On Tue, 22 Jan 2008 06:19:46 -0800 (PST),
Andy <jonesandy@comcast.net> wrote:
imagine (!) why I might want that difference.
What I *can* easily imagine, though, is wanting to use
fixed-point for both real and imaginary components,
although presumably with the same scaling for both.
That's another reason why I still see some value in
the vactor-of-bit-pairs representation, despite the
simulation performance hit.
Very interesting ideas, though. Thanks to all.
Postscript: In Verilog, and even in SystemVerilog,
this discussion could never have taken place.....
although I suppose that synthesis tools might one
day get around to synthesising SystemVerilog classes
with appropriate restrictions, and then things would
become much more fun.
--
Jonathan Bromley, Consultant
DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services
Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com
The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
Andy <jonesandy@comcast.net> wrote:
Maybe I'm being dense, but I can't for the life of meTaking that approach,
[a single vector of concatenated real and imaginary parts]
and borrowing a page from the fixed point
package, you could define the single vector such that natural indices
indicated the real portion, and negative indices indicated the
imaginary portion, in case you wanted different widths for real and
imaginary.
imagine (!) why I might want that difference.
What I *can* easily imagine, though, is wanting to use
fixed-point for both real and imaginary components,
although presumably with the same scaling for both.
That's another reason why I still see some value in
the vactor-of-bit-pairs representation, despite the
simulation performance hit.
Very interesting ideas, though. Thanks to all.
Postscript: In Verilog, and even in SystemVerilog,
this discussion could never have taken place.....
although I suppose that synthesis tools might one
day get around to synthesising SystemVerilog classes
with appropriate restrictions, and then things would
become much more fun.
--
Jonathan Bromley, Consultant
DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services
Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com
The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.