Completely puzzled: Strange shift register behaviour

[glen herrmannsfeldt]

Jon Elson <jmelson@wustl.edu> wrote:

(snip)

However, I still have some questions on this. If I built my design from,
lets say, discrete components, I might have problems with setup and hold
times at the shift register (SR) input, but I would NEVER EVER get the
results that showed up in the simulation:

I am not so sure about that.

(snip)

In FPGA hardware, easily! Xilinx guarantees their LUTs to be glitch-free
by themselves, but as has been pointed out here before, when multiple
LUTs are strung together with routing delays between them, all bets are
off. Can't say about glitch behavior on Altera, but I suspect similar
things. Then, the tools pack logic into the LUTs as they fit best,
without any attention to making sure glitches can't propagate.

If they want to work like gates, then they shouldn't glitch in the
case where individual gates won't glitch. I suppose if you use
only synchronous design techniques then maybe there are no cases
where it matters. As far as I know, FPGAs don't require that.

Now, why this behavior showed up in simulation is not clear.
But, again, if you do things that are really wrong in the HDL,
it is possible the simulator just fouls up.

Without seeing it in verilog, I don't see it either.

Reasonably likely it would be too fast for an actual FF, which
I think means it violates setup and/or hold.

-- glen