common emitter configuration- voltage divider biasing.

[Fred Stevens]

Ian Bell <ruffrecords@yahoo.com> wrote in message news:<2mlerrFn7ftqU1@uni-berlin.de>...

Jenny wrote:

I think I kind of SEE the equations, but the concepts behind the
voltage divider biasing does not quite enter my head. I am muddled
hopelessly i think.
V1= R1(R1+R2) Vb= R2(R1+R2) this correct ?

Why is the base current to be negligible ? I read this everywhere. Is
the base emitter junction like a high resistance that current that
comes down the R1 resistor (the first resistor in the voltage diver)
goes almost all through R2 ?

No, that's the way it needs to be designed for dc stability. As a rule you
would aim for about 10 times the base current to flow thru the voltage
divider.

Also why should I chose R1 to make the current through it at least 10
times base current ?

Like I said for dc stability.


Please try to explain if you could, with scenarios that show WHY. If
you can show what will happen if it is NOt the case that would
probably sink in easier. I have looked though som many posts and
we-sites, I think I am missing something very simple and obvious like
an elephant in the living room.

You really need the math to appreciate it but as a beginning the design aim
is a stable collector current. This is related to base current by the hfe
parameter which unfortunately varies over a very large range between
different samples of transistor of the same part number. So whatever we do
to set the collector current has to be essentially independeant of the base
current. With a voltage divider the way to do this is to make the base
current small compared to the divider current.

Ok?

Ian

The best way to analyse the base circuit is to use the Thevenin
equivalent circuit of the potential divider - then you will have a
voltage source, a series resistor, the base emitter junction and a
series emitter resistor if present. A simple application of KCL can
then be used on the resulting loop. Additional equations are Ic =
hFE*Ib, hfe = alpha/(1-alpha)
and Ic = alpha*Ie. (with alpha < 1)

Fred.
Fred.

 

[andy]

On Mon, 26 Jul 2004 21:26:55 -0700, Jenny wrote:

comments/ques inline

Vcc +
|
|_
| | Rc with Ic that we want
|_|
|
|
|
/C ------------o Vout
_____Ib___|
| \E-
| .7v | hfe=say 100
| |
=== Vb Re
= |
| |
______________________GND___o

In the above circuit, if I assume decide Ic to be X, Ib required will
be Ic/100. Ok. Now how to make Ib what we want it to be ? Attach a
voltage source to it.

You know the current through 'Re', because it is almost the same (99%) of the
collector current, so from that you can work out the voltage across it. Add just
0.7V and you then have the bias voltage required.

If I ignore Ib in calculating the drop across Re, and Vb=.7+Ve, and
use this Vb as basis for finding R2 bias resistor, then how can I
ensure that Ib will be Ic/hfe. I mean if its is not used in the
calculation, how can I be working backwards ?

ZAP - transistors won't stand that kind of voltage across the base/emitter
junction. Remember that current through a diode junction increases exponentially
with voltage and so it would be quickly destroyed.

Ok. let me assume that I add an R2 which is way greater than the Vb
required to forward bias the junction and have Ve to drop across Re,
then ok the transistor will heat up BECAUSE the current is really
high. Before all things get fried, wont Ic be REALLY huge for a few
instants when this Ib is large ?

but because Ic is increasing, and all of Ic ends up as part of Ie, then
the current through Re will increase. V=IR, so the voltage across Re will
increase, bringing the emitter voltage closer to the base voltage, and
reducing the current. so it will bring itself back to a new stable
operating point, just with a higher value of Ie and Ve.




--
http://www.niftybits.ukfsn.org/

remove 'n-u-l-l' to email me. html mail or attachments will go in the spam
bin unless notified with

 or [attachment] in the subject line.

 

[Rich Grise]

Jenny wrote:

comments/ques inline

You know the current through 'Re', because it is almost the same (99%)
of the
collector current, so from that you can work out the voltage across it.
Add just 0.7V and you then have the bias voltage required.

If I ignore Ib in calculating the drop across Re, and Vb=.7+Ve, and
use this Vb as basis for finding R2 bias resistor, then how can I
ensure that Ib will be Ic/hfe. I mean if its is not used in the
calculation, how can I be working backwards ?

Ib == Ic/hfe almost by definition. Although I thought it was actually
Ie, which of course is == Ic + Ib.

HTH!
Rich

 

[Jonathan Kirwan]

On Tue, 27 Jul 2004 10:42:07 GMT, "Kevin Aylward" <salesEXTRACT@anasoft.co.uk>
wrote:

Jonathan Kirwan wrote:
On 26 Jul 2004 21:39:18 -0700, jennygero1@yahoo.com (Jenny) wrote:

Can you recommend a few ? I would like an intuitive treatment along
with the math. The problem is that while I realize that Ib NEEDs to
be something by design, I dont see how that is achieved,
mathematically. Especailly because they ignore the Ib in calculating
the voltage Vb=Ve+.7.

You got a lot of information in this thread -- take some time and go
through it. But here's my own hobbyist viewpoint for DC operation of
a typical common emitter design...

I(C):
-----
First off, you need to select the collector current for the
transistor. I'd love to hear sophisticated views about this, but one
way I do that is to just look at the data sheet -- some of its
specifications will specify an I(C) to give it the appearance of
being a "good" part. It's a good bet that you want to operate your
transistor around this area, without more meaningful reasoning to
pick another value.

Yes, but this is a bit of reverse thinking.

Agreed, but the OP is kind of coming at this, not as a designer might, but as
someone just trying to understand, broadly. I decided that backing into this,
this way, might communicate the process at one level without needing to then
also know a level above it.

For example, in the Motorola data sheet for the
2N2222A, they specify a number of the characteristics at 10mA, 15mA,
and 20mA. That's your first clue about what you want. (It's
probably on the high end of what you want, actually, unless you
really need the performance.)

Decide what your spec is *first*. *Then* *chose* a transistor that will
meet the spec. For example, if you are after low noise, you might
consider that the optimum noise (approx) is setting
re=Rsource/sqrt(hfe), to set Ic. Looking at the data sheet for the
transistor to *chose* the current in the first place makes little sense.

Hehe. Agreed!But then, I'm just imagining that the OP has a particular data
sheet or transistor and is then seeing about what might be various
considerations, given that. It's a concrete thing to imagine a single
device/datasheet.

The whole discussion would have been just that more complex and raised to yet
another level, had I folded in what you are suggesting. As a designer already,
I'm sure that's easy for you -- a "been there, done that," kind of thing. But I
imagined starting short of that broader view.

You are designing for the *application*, not the device.

hehe. Yes.

You might want to be able to drive a large capacitive load at a given
frequency. You would then need to chose a highish current.

Yup. Good addition. Actually, I think all this is good, by way of expanding on
ideas. And it really helps me as a hobbyist, to see your point of view, too.

For high speed amplifier design you might want to select a transistor
with low Ccb.

There are many factors in BJTs that can become important, depending on the
application, as I'm sure you know far better than I do. Over time, anyone just
getting started on understanding will develop an 'eye' for more of these as
applications they try teach them.

Or where the simpler mental models basically fail you. One example of this is
where you don't have a little r(e) model in your mind and you simply ground the
emitter of the NPN, for example. What's the gain? You might have previously
figured it as R(C)/R(E), but what does this mean when R(E) is zero??

But it did help me some to start easier and roughly correct for a smaller range
of things and then, gradually to fold in additional concepts (I'm at the
fortunate state where I still have much more to learn, too.)

Later in the sheet, there are some nice curves (you want to find
these, often) for DC current gain versus I(C) and also V(CE) versus
I(B) with several I(C) curves (it's the collector saturation chart.)
The 2N2222A from Motorola shows the DC current gain dropping off
starting around 30-40mA -- that's a broad suggestion that you
probably don't want to go a lot higher.

But if *want* to use a high current, chose a different transistor.

Yup.

Again, its the application that should be driving the choice of
operating current and device, not the other way round.

Agreed. But I chose this route because that's the way I'd want it explained to
me, had I no skills designing for applications but still wanted some idea about
how to calculate things given some particular part. (And more, as a hobbyist, I
don't always want to order a transistor for a project. I will grab my little
box of the few I have (and in my earlier days of being a hobbyist, this was
nothing more than sorted by NPN or PNP and otherwise all together in a place)
and select one that seems "big enough." If I were doing a light bulb switch,
I'd probably pick a "bigger one" and if it were a simple audio amplifier I might
pick a smaller one but where I still may have several (so that I can consider
doing several stages, for example.) That was about my level of thinking, then.

One can take it in either direction. For just understanding the calculations
though, I thought it was helpful to take it in the direction I did. But I like
the additions you've made!

Other curves to look at might be the turn-on and turn-off times
versus I(C) [higher I(C) generally means 'faster'], but that usually
isn't your problem for audio amplifiers, for example.

Often they are. Audio amplifies usually use feedback. The game plan here
is to have the amplifier as fast as possible so that one can apply
lashings of feedback in order to reduce distortion. To keep things
stable with lashings of feedback, one needs to minimise phase shift from
the transistors. This means very fast transisters.

I wanted to avoid the bigger picture, while at least giving negative feedback
some mention so that the OP would at least trigger on the phrase in later
reading. There is a world of beauty in understanding negative feedback from a
variety of dimensions and eventually it becomes a good friend. Your point here
is neatly and tersely put, yet entirely understandable from my point of view. I
love the clear, full, yet economical of use of words. But the OP isn't even at
my modest level of understanding, I fear, and the idea of phase shift (or even
group delay) is probably way past the point of meaning.

Even the idea of exactly what 'distortion' means is probably not quite there to
the OP, yet. I tried to imply that having a gain that fluctuates as your signal
voltage does causes it, but the OP may yet need to actually *visualize* this in
mind before it becomes clearer. Working an NPN amplifier example with an R(E)
that is very tiny, but taking r(e) into account for gain calculations and
figuring the V(C) as V(B) wavers, would probably help the OP see what happens to
the original sine shape. But this takes getting out a graph paper and plotting
it by hand. Getting a spice program to do it for you might let you see the
result, for example, but it's really in the calculations themselves and doing
them by hand that really makes this clear. At least, I think so.

These numbers
are often in nanoseconds. Another curve is the noise figure versus
source resistance for various I(C). Depending on your source, it
might push you one way or another. Though for hobby work, I don't
use this much, either.

As a guide, I tend to imagine that higher I(C) is for "higher
operating frequency

Yes.

Okay.

and/or gain (up to a point.)"

Not really.

Agreed, but the gain is gently sloping upwards on I(C) up to a point.

Lower I(C) is
better for lower dissipation.

Well... yes!!!

hehe. Sometimes, it's important to state it, though. Yes?

R(E):
-----
For setting the DC operating point of your basic common emitter
design, before even considering an RC in the emitter leg, it's the
general idea to figure the voltage across R(E) at about 1V to add
some temperature stability in the circuit against V(BE) variations
with I(C) over temperature, to help reduce the impact of variations
in the internal NPN's r(e) on gain,

It does vary a bit, but is often not a major issue.

and to reduce distortion caused
by the Early effect.

Not usually a dominate distortion effect, but can be.

Just trying to list what I could off the top of my head.

-- through the use of negative feedback.

I generally use 1V as a reasonable guideline. I try not to go lower,
but higher is fine. With this and knowing that I(C) is 1mA and that
I(E) is roughly equal to I(C) [when operating normally, anyway], you
can figure that R(E) should be 1V/1mA = 1k ohm.

Probably the "best" reason for an emitter resister is to reduce
distortion.

Yup. And if the OP works out the math on what happens to a sine going from base
voltage to collector voltage, when R(E) is in the ballpark range of, say 10
Ohms, and while taking into account r(e), then I think the point will become
very much clearer.

Once you see the hand-plotted results and have the calculations fresh in mind
that you used to generate it, it sticks with you.

A simple transistor amplifier has around vi(mv)% distortion.
That is 1mv will give 1% distortion. This is a *huge* amount for such a
small signal. An emitter resister will reduce this by around (re/Re)^2.

http://www.anasoft.co.uk/EE/index.html

I think the OP will need to start with just understanding what this distortion
is and viscerally why it arises before getting this newer picture. The OP needs
to hand plot this.

(Sometimes, I make modest adjustments above 1V, though.)

V(B):
-----

{snip tedious calculations}

Ok.... This can in fact be done automatically in SuperSpice

http://www.anasoft.co.uk/DeviceDesigner.html

Simply chose node voltages and device currents, and press the button, it
will calculate out all the resister values for you.

Of course! I actually have a basic degenerative amp design, with the series RC
leg (and some other topologies) parallel to R(E) and with bootstrapping, where I
can simply set a few design parameters and let it compute the results and plot
gain and phase over frequency, etc. I also have the basic DC amp and the
non-bootstrapped AC amp, for comparisons.

Natually, being a cheap-minded hobbyist, it's in LTSpice, though. Since I
managed to scarf up a bunch of ORCAD model libraries, I've filled in for some of
the really big lack of LTSpice, which is it's relative lack of complete,
non-"Linear Corp" model sets.

And again, I'm only a hobbyist type and have absolutely no
professional design experience.

You seem to have done pretty well, all things considered.

Thanks. I tried. But I'm also just learning, too, and have much more yet to
gather.

Jon

 

[Jonathan Kirwan]

On Tue, 27 Jul 2004 10:42:07 GMT, "Kevin Aylward" <salesEXTRACT@anasoft.co.uk>
wrote:

Ok.... This can in fact be done automatically in SuperSpice

http://www.anasoft.co.uk/DeviceDesigner.html

Simply chose node voltages and device currents, and press the button, it
will calculate out all the resister values for you.

Ah. Just looked at the page! Nice. How do you settle on the values? Is this
a software process of simulated annealing or the slightly less complex simplex
methods?

Jon

 

[Kevin Aylward]

Jonathan Kirwan wrote:

On Tue, 27 Jul 2004 10:42:07 GMT, "Kevin Aylward"
salesEXTRACT@anasoft.co.uk> wrote:

Ok.... This can in fact be done automatically in SuperSpice

http://www.anasoft.co.uk/DeviceDesigner.html

Simply chose node voltages and device currents, and press the
button, it will calculate out all the resister values for you.

Ah. Just looked at the page! Nice. How do you settle on the
values? Is this a software process of simulated annealing or the
slightly less complex simplex methods?

Neither. Its my own unique method. I invented it. However, its trivially
simple, so simple that *everyone's* missed it. It *directly* calculates
the values, essentially exactly, using the full model equations, in
*one* spice run. It doesn't do any searching or iteration at all, other
than the normal iterations in any spice run. However, for calculating
BSim3 mosfet lengths and widths, there is a small error due to the
difficulty in inverting the BSim3 equations.

I'll probably write a little paper on the method, when I get round to
it.

Kevin Aylward
salesEXTRACT@anasoft.co.uk
http://www.anasoft.co.uk
SuperSpice, a very affordable Mixed-Mode
Windows Simulator with Schematic Capture,
Waveform Display, FFT's and Filter Design.

 

[Jonathan Kirwan]

On Tue, 27 Jul 2004 19:12:32 GMT, "Kevin Aylward" <salesEXTRACT@anasoft.co.uk>
wrote:

However, for calculating
BSim3 mosfet lengths and widths, there is a small error due to the
difficulty in inverting the BSim3 equations.

So here, at least, you might consider using an iterative approach? Or do you
plan on struggling further to construct a closed equation?

I'll probably write a little paper on the method, when I get round to
it.

Jon

 

[Jonathan Kirwan]

On Tue, 27 Jul 2004 07:59:03 GMT, Jonathan Kirwan <jkirwan@easystreet.com>
wrote:

Because V(BE) (the difference between V(B) and
V(E)) is fairly constant in normal situations, lifting V(B) by a slight amount
will also lift V(E) by the same slight amount.

I should add that V(BE) does vary slightly based on I(C). It's something like
18mV for a doubling of I(C) or 60mV for a factor of 10X. This is why you can
usually take V(BE) as a rough constant for estimating the DC operating points,
even when using different I(C) to start out.

JG, you might also try taking a look at the basic Ebers-Moll model for the
transistor. I don't know of a very good web reference for this, but the book I
use is: Modeling the Bipolar Transistor, by Ian Getreu. I've no idea why these
books are so hard to find, but I believe they are. I got mine free within a few
days of its publication because I was a software engineer at Tektronix at the
time when he worked there and wrote it and they were handing them out like
popcorn to employees who asked for it. One of the really GREAT things about
this book is that it not only talks about the models in detail, but it also
documents the details about where certain parameters arise and how to make
relatively accurate measurements to derive them from a real device you might
have in hand and where you don't want to rely only on the datasheet. I don't
know of another book that puts all these excellent details into one place.

The Ebers-Moll model was first described in, I think, 1954 or so and comes in
"three flavors": injection model, transport model, and the non-linear hybrid-PI
model. These are like different viewpoints of the same thing. For example, the
injection model highlights the two diode currents from base to collector and
from base to emitter while the transport model highlights the two related
current sources between base and collector and base and emitter. The equations
are adjusted to emphasize one preferred view or the other. There are two key
math templates used to model each of the two junctions -- the standard equation
you see in most texts that follows something like:

I(C) = I(S) * exp( q*V(BE) / (k * T) - 1 )

it's here that you see the (k*T/q) behavior I mentioned for the voltage part of
the r(e) equation.

But there is another, and important part, that describes the behavior of I(S)
over temperature, and which actually winds up dominating the temperature
behavior that might be implied by the earlier equation above:

I(S)[T] = I(S)[nominal] * ( T / Tnominal )^3*exp( (-Eg/k)*(1/T - 1/Tnominal) )

The EM model is only the first step. But it's a good one. Then there are
modifications made to handle other factors that become important in some
application areas and tend to either dominate or else materially impact the
results in those cases. As the models grow more complex, they become usually
more broadly applicable -- but also, often, more complex than needed for a given
application.

Jon

 

[Joe]

"Jenny" <jennygero1@yahoo.com> wrote in message
news:def337ab.0407261534.3595c1f@posting.google.com...

So you start with the
expected collector current and the minimum current gain spec of the
transistor, and work backwards to the maximum expected base current.
Its clear till this point.

Then you calculate the divider pair so that this worst case base
current will not upset the divider voltage by more than a little.

How do I do that ? By worst case base current do you mean that for a
given beta, Ic and Rc, Ibmax or Ibworst-case is Ic/beta ? and Ib can
never go above that ? What decides Ib ? If it is the voltage applied
to base, then wont higher voltage mean higher base current ?

And
voila, the assumption that the base current is negligible is met.

I see the dots bUT not the connection. Sorry if I am being very duh-
can you explain like to a child ? :-\ now I am beginning to thik may
not understand how the voltage divider works.


the base emitter junction like a high resistance that current that
comes down the R1 resistor (the first resistor in the voltage diver)
goes almost all through R2 ?

If the resistors a are the result of design and not chance, yes.

So what is the resistance which decides Ib ? how total current in the
voltage divider circuit can be calculated and how do I know how much
will go through Ib ?


Also why should I chose R1 to make the current through it at least 10
times base current ?
(snip)

Because otherwise, the design assumption that the divider produces a
specified voltage, regardless of gain variations in the transistor
(with different transistors and with changes in temperature) is not a
safe assumption.

If you have a source of transistors that have a very narrow range of
current gains (or are willing to live with more bias point variation),
you can take the range of expected base currents into specific account
and use much higher base divider resistances, saving power and raising
the amplifier input resistance, increasing effective gain. But you
can not then make the simplifying assumption that the voltage divider
output is unaffected by the base current, but have to calculate the
range of effect that the expected range of base currents will have on
the divider voltage. The ultimate extreme if this case is to
eliminate the lower half of the divider and feed base current through
a single resistor. This gives the most efficient form of the divider
(highest possible resistance for R1 and infinite resistance for R2),
but also the least stable.

Designers analyze alternatives.

Hi Jenny,

A few months ago, I was trying to figure out the math behind common emitter
amps and I found this site:

http://hyperphysics.phy-astr.gsu.edu/hbase/electronic/npnce.html

If you take your time and go thru each step of the design, you will
understand everything from the biasing to the reason for the emitter
capacitor. They have equations that you can just into a spreadsheet and then
enter supply voltage, collector current, frequency, beta, etc. and see the
values that you need for your application. They also have the same info for
common collector and common base amplifiers using NPN transistors. It's a
good start.

hth,
Joe

 

[Kevin Aylward]

Jonathan Kirwan wrote:

On Tue, 27 Jul 2004 19:12:32 GMT, "Kevin Aylward"
salesEXTRACT@anasoft.co.uk> wrote:

However, for calculating
BSim3 mosfet lengths and widths, there is a small error due to the
difficulty in inverting the BSim3 equations.

So here, at least, you might consider using an iterative approach?

Not really. I can't be bothered. The error as it stands is typically
much less than that of process variations.

Or do you plan on struggling further to construct a closed equation?

Nope

A true closed loop is probably not possible, and its a law of
diminishing returns. Most people doing i.c design are using those
extortionately priced Cadence stuff anyway. As I noted, for calculating
resister values, its as accurate as any normal spice run, irrespective
of what devices are in the circuit.


Kevin Aylward
salesEXTRACT@anasoft.co.uk
http://www.anasoft.co.uk
SuperSpice, a very affordable Mixed-Mode
Windows Simulator with Schematic Capture,
Waveform Display, FFT's and Filter Design.

 

[Jonathan Kirwan]

On Tue, 27 Jul 2004 20:29:20 GMT, "Joe" <nuisancewildlife@nospamearthlink.net>
wrote:

A few months ago, I was trying to figure out the math behind common emitter
amps and I found this site:

http://hyperphysics.phy-astr.gsu.edu/hbase/electronic/npnce.html

If you take your time and go thru each step of the design, you will
understand everything from the biasing to the reason for the emitter
capacitor. They have equations that you can just into a spreadsheet and then
enter supply voltage, collector current, frequency, beta, etc. and see the
values that you need for your application. They also have the same info for
common collector and common base amplifiers using NPN transistors. It's a
good start.

I just looked at the site. I didn't like the way they handled the emitter
resistor bypass. I'm no expert, of course, but I believe it's just wrong-minded
in their topology and text. Do you see what I mean?

Jon

 

[Kevin Aylward]

Jonathan Kirwan wrote:

On Tue, 27 Jul 2004 20:29:20 GMT, "Joe"
nuisancewildlife@nospamearthlink.net> wrote:

A few months ago, I was trying to figure out the math behind common
emitter amps and I found this site:

http://hyperphysics.phy-astr.gsu.edu/hbase/electronic/npnce.html

If you take your time and go thru each step of the design, you will
understand everything from the biasing to the reason for the emitter
capacitor. They have equations that you can just into a spreadsheet
and then enter supply voltage, collector current, frequency, beta,
etc. and see the values that you need for your application. They
also have the same info for common collector and common base
amplifiers using NPN transistors. It's a good start.

I just looked at the site. I didn't like the way they handled the
emitter resistor bypass. I'm no expert, of course, but I believe
it's just wrong-minded in their topology and text. Do you see what I
mean?

Probably.

The argument of making Ce small in comparison to Re is false. If one is
going for a maximum flat gain over a set frequency range, then Ce must
be small in comparison to re, the internal dynamic impedance, not Re the
external resistance. If this is not done, the low frequencies will be
attenuated compared to the mid band gain.

In the example given, midband gain LF rolloff (-3db) is around 275hz,
which is way to high for typical audio.

Again, if one wants info that is going to be reasonable sound, I would
refer to http://www.anasoft.co.uk/EE/index.html.

Kevin Aylward
salesEXTRACT@anasoft.co.uk
http://www.anasoft.co.uk
SuperSpice, a very affordable Mixed-Mode
Windows Simulator with Schematic Capture,
Waveform Display, FFT's and Filter Design.

 

[Jonathan Kirwan]

On Wed, 28 Jul 2004 09:36:41 GMT, "Kevin Aylward" <salesEXTRACT@anasoft.co.uk>
wrote:

Probably.

The argument of making Ce small in comparison to Re is false. If one is
going for a maximum flat gain over a set frequency range, then Ce must
be small in comparison to re, the internal dynamic impedance, not Re the
external resistance. If this is not done, the low frequencies will be
attenuated compared to the mid band gain.

Not quite the way I'd put it. Its simply that using a C with an impedance that
is "<<" (very much less) than R(E) at some frequency simply means it 'shorts'
R(E). But an effectively grounded emitter means the gain is based on R(C)/r(e),
in this case, which is not good news. The gain will be varying widely, since
r(e) is a function of I(C). Yuk.

And even if the impedance of C is more modest than that, such that it is
comparable to R(E) rather than very much less and thus reduces the impact of
r(e) to tiny proportions, it only then makes the gain highly variable on the
frequency. Again, probably not a reasonable design.

Two common topologies are:

emitter emitter
\ \
| |
| |
\ +----,
/ R1 | |
\ | |
| | \
| | / R4
+----, \ \
| | R3 / |
| | \ |
\ --- C1 | |
R2 / --- | --- C2
\ | | ---
| | | |
| | | |
gnd gnd gnd gnd

In the left case, C1 is large enough to effectively bypass R2 at some minimum
frequency. Above that frequency (and until other parameters otherwise limit
it), R(C)/(R1+r(e)) sets the AC gain. However, R1+R2 is what participates in
setting the DC operating point.

In the right case, C2 is large enough to effectively tie R4 to ground at some
minimum frequency (just as in the left case.) Above that frequency,
R(C)/(R3||R4+r(e)) sets the AC gain. R3 participates in setting the DC
operating point.

Two ways of doing the same thing. But in either case, the AC gain is roughly
flat over a reasonable range of frequencies and, given reasonable R1 or else
R3||R4 values, also over I(C) values.

What I didn't like about the web site is that the C they used simply bypassed
their emitter R, so that the transistor's emitter then went straight to ground.

It's not a typical arrangement for audio. I'm not even sure what it would be a
good approach for.

Jon

 

[Ian Bell]

Jenny wrote:

So you start with the
expected collector current and the minimum current gain spec of the
transistor, and work backwards to the maximum expected base current.
Its clear till this point.

Then you calculate the divider pair so that this worst case base
current will not upset the divider voltage by more than a little.

How do I do that ? By worst case base current do you mean that for a
given beta, Ic and Rc, Ibmax or Ibworst-case is Ic/beta ?

You have a design Ic, divide it by the lowest hfe for the transistor to get
the worst case base current.

and Ib can
never go above that ? What decides Ib ? If it is the voltage applied
to base, then wont higher voltage mean higher base current ?

The important thing to remember is that with an emitter resistor there is a
dc negative feedback loop operating. Assuming the current thru the divider
is large compared to the base current we can assume the base voltage is
fixed. If the emitter current increases (say because of a temperature
change) the voltage across Re will increase. As the base is held constant
this means vbe will decrease which means Ib decreases (this is what
determines Ib), so the emitter current will reduce.


Ian

 

[Ian Bell]

Kevin Aylward wrote:

Jonathan Kirwan wrote:
On Tue, 27 Jul 2004 20:29:20 GMT, "Joe"
nuisancewildlife@nospamearthlink.net> wrote:

A few months ago, I was trying to figure out the math behind common
emitter amps and I found this site:

http://hyperphysics.phy-astr.gsu.edu/hbase/electronic/npnce.html

If you take your time and go thru each step of the design, you will
understand everything from the biasing to the reason for the emitter
capacitor. They have equations that you can just into a spreadsheet
and then enter supply voltage, collector current, frequency, beta,
etc. and see the values that you need for your application. They
also have the same info for common collector and common base
amplifiers using NPN transistors. It's a good start.

I just looked at the site. I didn't like the way they handled the
emitter resistor bypass. I'm no expert, of course, but I believe
it's just wrong-minded in their topology and text. Do you see what I
mean?


Probably.

The argument of making Ce small in comparison to Re is false. If one is
going for a maximum flat gain over a set frequency range, then Ce must
be small in comparison to re, the internal dynamic impedance, not Re the
external resistance. If this is not done, the low frequencies will be
attenuated compared to the mid band gain.

In the example given, midband gain LF rolloff (-3db) is around 275hz,
which is way to high for typical audio.

Again, if one wants info that is going to be reasonable sound, I would
refer to http://www.anasoft.co.uk/EE/index.html.

I must admit I was not as impressed as I expected to be by this site.
Talking about currents 'flapping in the wind' is hardly helpfull to
beginners. Also stating that a transistor is a voltage operated device
closely followed by the first transistor equation of:

Ic = hfe * Ib

is likely to confuse beginners.

Ian

 

[Ian Bell]

Jenny wrote:

How about if
there was no re and a direction connection to the ground.

As before, probably a saturated transistor.

IAn

PS. There ar eplenty of elementary texts on this. you should read one.

Can you recommend a few ?

Alley and Atwood is the classic Electronics text.

I would like an intuitive treatment along
with the math. The problem is that while I realize that Ib NEEDs to be
something by design, I dont see how that is achieved, mathematically.
Especailly because they ignore the Ib in calculating the voltage
Vb=Ve+.7.

Ib does not need to be something by design. The actual value of Ib in this
circuit will vary. If you made 10 copies of this circuit then the
variation in hfe between transistors would mean Ib would be different in
each one. The problem with transistor design is that hfe varies over a
wide range so the task boils down to making the circuit parameters largely
independent of hfe. As you normally want to set a collector current this
means making the circuit parameters largely independent of Ib. A divider
provides a way to provide a bias voltage to the transistor but if it is not
to be affected by Ib its current must be large compared to Ib.

Ian

 

[Ian Bell]

Jonathan Kirwan wrote:

You got a lot of information in this thread -- take some time and go
through it. But here's my own hobbyist viewpoint for DC operation of a
typical common emitter design...

I(C):
-----
First off, you need to select the collector current for the transistor.
I'd love to hear sophisticated views about this,

Depends on what you are trying to achieve. For a small signal amplifier you
might want to choose a value that gives low noise for example. However, in
all cases you need to think about the load this circuit will drive into.
To a very simple first approximation, the output impedance of the CE
circuit is its collector resistance. Not much good choosing a 1K collector
resistance if you want to drive a 100R load.

Ian

 

[Joe]

"Jonathan Kirwan" <jkirwan@easystreet.com> wrote in message
news:gfmdg0dsvtt7837sgkgn7nve6m5hfev1ja@4ax.com...

On Tue, 27 Jul 2004 20:29:20 GMT, "Joe"
nuisancewildlife@nospamearthlink.net
wrote:

A few months ago, I was trying to figure out the math behind common
emitter
amps and I found this site:

http://hyperphysics.phy-astr.gsu.edu/hbase/electronic/npnce.html

If you take your time and go thru each step of the design, you will
understand everything from the biasing to the reason for the emitter
capacitor. They have equations that you can just into a spreadsheet and
then
enter supply voltage, collector current, frequency, beta, etc. and see
the
values that you need for your application. They also have the same info
for
common collector and common base amplifiers using NPN transistors. It's a
good start.

I just looked at the site. I didn't like the way they handled the emitter
resistor bypass. I'm no expert, of course, but I believe it's just
wrong-minded
in their topology and text. Do you see what I mean?

Jon

Hi Jon,

Well, not really, but then I am no expert either. I understand the need for
an emitter bypass cap, and, having a background in physics, I like using
equations to design these amplifiers with. It makes it much simpler for me.
When I put the right values together on the breadboard, I know the design
will work. I have problems figuring out what the load is going to be if it
is another transistor (ie 2nd stage) to determine the output cap. Can you
elaborate a little more on what you are not comfortable with?

Joe

 

[Jonathan Kirwan]

On Wed, 28 Jul 2004 22:29:50 +0100, Ian Bell <ruffrecords@yahoo.com> wrote:

Depends on what you are trying to achieve. For a small signal amplifier you
might want to choose a value that gives low noise for example.

I mentioned this, after a fashion.

However, in
all cases you need to think about the load this circuit will drive into.

Yup. But then you are getting into another area. There is a whole other thing
to learn in understanding input and output impedances and their whys and
wherefores. I thought I'd hold short of getting into that.

To a very simple first approximation, the output impedance of the CE
circuit is its collector resistance. Not much good choosing a 1K collector
resistance if you want to drive a 100R load.

Hehe.

Jon

 

[Jonathan Kirwan]

On Wed, 28 Jul 2004 23:56:15 GMT, "Joe" <nuisancewildlife@nospamearthlink.net>
wrote:

Can you
elaborate a little more on what you are not comfortable with?

Yes, I already did in my response to Kevin. Did I make sense?

Jon