code question

I want to implement a bitsplit entity but can't figure out how to get it to work. Basically I get some input of NB_BITS_PER_CLK length and I want to be able to select any possible rotation of the bits.

Example:

Input : 010

Possible outputs depending on tap_sel:

010
100
001

Can also work if tap_sel is std_logic and every time it gets pulsed you get a different bit arrangement. But this is streaming so it is about selecting the appropriate arrangement not doing x rotations. Below is what I came up with but sort of stuck. Help would be greatly appreciated



entity capture_bitslip is
generic (
NB_BITS_PER_CLK : integer := 4
);
port(
clk : in std_logic;
rst : in std_logic;
tap_sel : in std_logic_vector(3 downto 0); -- 2**4 = 16
bits_in : in std_logic_vector(NB_BITS-1 downto 0); -- bit unaligned comming in
bits_out : out std_logic_vector(NB_BITS-1 downto 0) -- bit aligned going out

);
end capture_bitslip;


-------------------------------------------------------------------------------------
-- Architecture declaration
-------------------------------------------------------------------------------------
architecture Behavioral of capture_bitslip is

-------------------------------------------------------------------------------------
-- CONSTANTS
-------------------------------------------------------------------------------------
type register_tbl_type is array (0 to 15) of unsigned(NB_BITS_PER_CLK-1 downto 0);

-------------------------------------------------------------------------------------
-- SIGNALS
-------------------------------------------------------------------------------------
signal delay_registers : register_tbl_type;
signal data_out : std_logic_vector(NB_BITS_PER_CLK-1 downto 0);

signal mux_ctrl : std_logic_vector(NB_BITS_PER_CLK-1 downto 0); --2**5 = 32

--***********************************************************************************
begin
--***********************************************************************************


--generate_pattern_table:
for X in 0 to NB_BITS_PER_CLK-1 generate
pattern_table(X) <= unsigned(bit_in) ror X;
end generate;

bit_out <= pattern_table(tap_sel);

 

-------------------------------------------------------------------------------------
-- Specified libraries
-------------------------------------------------------------------------------------
library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

-------------------------------------------------------------------------------------
-- Entity declaration
-------------------------------------------------------------------------------------
entity capture_bitslip is
generic (
NB_BITS_PER_CLK : integer := 4
);
port(
clk : in std_logic;
rst : in std_logic;
delay_sel : in std_logic_vector(3 downto 0); -- 2**4 = 16
bits_in : in std_logic_vector(NB_BITS_PER_CLK-1 downto 0); -- bit unaligned comming in
bits_out : out std_logic_vector(NB_BITS_PER_CLK-1 downto 0) -- bit aligned going out

);
end capture_bitslip;


-------------------------------------------------------------------------------------
-- Architecture declaration
-------------------------------------------------------------------------------------
architecture Behavioral of capture_bitslip is

-------------------------------------------------------------------------------------
-- CONSTANTS
-------------------------------------------------------------------------------------
type register_tbl_type is array (0 to 15) of unsigned(NB_BITS_PER_CLK-1 downto 0);

-------------------------------------------------------------------------------------
-- SIGNALS
-------------------------------------------------------------------------------------
signal delay_registers : register_tbl_type;


--***********************************************************************************
begin
--***********************************************************************************


generate_pattern_table:
for X in 0 to NB_BITS_PER_CLK-1 generate
delay_registers(X) <= unsigned(bits_in) ror X;
end generate;

bits_out <= delay_registers(delay_sel);

 

Finally came up with this. Is this synthesizable and can anyone think of a better way to do it?



generate_pattern_table:
for X in 0 to NB_BITS_PER_CLK-1 generate
delay_registers(X) <= unsigned(bits_in) ror X;
end generate;

data <= delay_registers(to_integer(unsigned(delay_sel)));


bits_out <= std_logic_vector(data);