Clock Edge notation

[Phil Hays]

Jeremy Pyle wrote:

Ok, I got a problem. I have two processes inside an architecture writing
the same signal. One process runs at startup and initializes the signal
while the other one runs after that, it's guaranteed that they never run at
the same time. However, when I simulate it the signal, which is local to
the architecture, never leaves the U value. If I comment out the write in
the second process(not the initialization one), then the signal changes like
it's supposed to. I know if two modules both write to one data bus then
when one is writing the other must write all Z's, is this also true for
signals in an architecture?

Yes. STD_LOGIC Signals driven between processes are multi-state buses
driven by multiple drivers.

If this is a test bench, you might be able to make good use of "H" and
"L" (weak 1 and 0). I wouldn't count on a synthesiser mapping these
correctly. And you may need the function TO_X01 to avoid having to
write:

If name = '1' or name ='H' then


--
Phil Hays

 

[Jeremy Pyle]

Well, or writing all Z's while the other process is updating will work too
right?


"Phil Hays" <SpamPostmaster@attbi.com> wrote in message
news:3EFFAF08.2F1A5355@attbi.com...

Jeremy Pyle wrote:

Ok, I got a problem. I have two processes inside an architecture
writing
the same signal. One process runs at startup and initializes the signal
while the other one runs after that, it's guaranteed that they never run
at
the same time. However, when I simulate it the signal, which is local
to
the architecture, never leaves the U value. If I comment out the write
in
the second process(not the initialization one), then the signal changes
like
it's supposed to. I know if two modules both write to one data bus then
when one is writing the other must write all Z's, is this also true for
signals in an architecture?

Yes. STD_LOGIC Signals driven between processes are multi-state buses
driven by multiple drivers.

If this is a test bench, you might be able to make good use of "H" and
"L" (weak 1 and 0). I wouldn't count on a synthesiser mapping these
correctly. And you may need the function TO_X01 to avoid having to
write:

If name = '1' or name ='H' then


--
Phil Hays

 

[Troels Smit]

PROCESS
BEGIN
WAIT UNTIL sclk = '1';
lr_1d <= lr;
lr_2d <= lr_1d;
lr_3d <= lr_2d;
END PROCESS;

Now you can use lr_2d and lr_3d within a process to detect an event:

PROCESS
BEGIN
WAIT UNTIL sclk = '1';
IF lr_2d /= lr_3d THEN
-- do your things
END IF;
END PROCESS;

Using a process similar to the one above I'd set a statemachine to start
counting to 20, send its bits, and then return to state0 where it's waiting
for your change on lr (IF lr_2d /= lr_3d THEN).
Regards,
Pieter Hulshoff

That is a quite interesting way to look for an event, I will defenetly
remember that. The only problem I see it that the clocks are defined
as follows:

input clk --this is fast
counter = counter + 1 -- at clock'event clock='1'

lr <= counter(8);
sclk <= counter(2);
mclk <= counter(0);

and therefore sclk can't really define lr as they are both dependent
on clk.
What I how done for now is to remember what lr was last time, and then
listen for the opposite in a state machine. This has some time-skew
but it works IRL.

Thanks!

/Troels

 

[Jonathan Bromley]

"Jeremy Pyle" <jeremyp@rochester.rr.com> wrote
in message news:mSNLa.6780$4J6.5280@twister.nyroc.rr.com...

Ok, I got a problem. I have two processes inside an architecture writing
the same signal. One process runs at startup and initializes the signal
while the other one runs after that, it's guaranteed that they never run
at
the same time. However, when I simulate it the signal, which is local to
the architecture, never leaves the U value. If I comment out the write in
the second process(not the initialization one), then the signal changes
like
it's supposed to. I know if two modules both write to one data bus then
when one is writing the other must write all Z's, is this also true for
signals in an architecture?
I realize a way to fix this is to just have them both write from the same
process, but I want to make sure I understand it, because I'm sure it's in
other places too.

A signal is not the same as a Verilog register! Each process that drives
a VHDL signal represents a driver on that signal. Each driver has its
own copy of the value that its process is trying to drive. So, your
"initialisation" process is trying to drive (let's say) '0'. But the
other process starts by trying to drive 'U', because that's the default
initial value for any STD_LOGIC driver. The 'U' wins the conflict.
I guess that your "working" process was expecting to see your
desired initialisation value, not 'U', so it gets confused. In
any case this wouldn't work because whatever the second process
does, the "init" process is permanently trying to drive '0'
on to the signal.

The bottom line is that code in one process cannot influence the
values that are driven from within another process.

Since this is presumably a test bench, it's completely reasonable
to get rid of the "initialisation" process altogether, and
give the signal an initial value as part of its declaration:

architecture foo of bar is
...
signal S: std_logic := '0';
...
begin
...
process begin
loop
wait for 5 ns;
S <= not S; --- OK because S is initially '0'

This has the added advantage that the signal initialisation
is guaranteed to take effect BEFORE any process starts to
run, whereas your "two process" initialisation will suffer
from the problem that the initialisation would not take
effect until one delta time after the start of simulation.

So, you are right: the correct fix is to do everything in
one process.

If you're worried about this, you could consider declaring
your signals as STD_ULOGIC. This is an unresolved type,
and you'll get an explicit error message from the simulator
if more than one process drives a signal of such type.

HTH
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK
Tel: +44 (0)1425 471223 mail: jonathan.bromley@doulos.com
Fax: +44 (0)1425 471573 Web: http://www.doulos.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

[Ed Stevens]

If you have a slow Internet connection you can ask XILINX to send you the
WebPack on CD. It takes about 2 weeks to arrive though.

www.BurchEd.com also sell an FPGA board.


"sunil" <sunilsreenivas2001@yahoo.com> wrote in message
news:d924fa71.0306282123.55cd302c@posting.google.com...

Hi All,
I am newbie to FPGA. Could some one please suggest me a good
book on FPGA that deals with important FPGA concepts like Floor
Planning, Place and Route, Timing Analysis. I would also like to know
where I can get a FPGA tool kit. I have Orcad Aldec simulation
software but don't have any synthesizer software. Do anyone know how
to obtain Xilinx (4.2i)synthesizer? I mean what are some of the
synthesizer softwares and where do I download/get them?
Thanks,
Regards,
Sunil.

 

[Powermos]

"Ed Stevens" <ed@stevens8436.fslife.co.uk> ha scritto nel messaggio
news:bdp691$dvj$1@newsg3.svr.pol.co.uk...

If you have a slow Internet connection you can ask XILINX to send you the
WebPack on CD. It takes about 2 weeks to arrive though.

www.BurchEd.com also sell an FPGA board.

very great tool but only for WinXp, 2000 not for WinMe (old Foundation
Series suite is able to work with WinMe).

Best regards
Pow

--
----------------------------------------------------
Ama il tuo mestiere con passione
E' il significato della tua vita
Auguste Rodin (1840-1917)

"Not everything that counts can be
counted, and not everything that can
be counted counts".
Albert Einstein

"Hunt for the Engineer and the Engineer will hunt you."
Hellraiser5 Pinhead

 

[Jim Lewis]

Jeremy,
See the packages at: http://www.eda.org/fphdl/

Cheers,
Jim

Jeremy Pyle wrote:

Hey all,

I'm trying to find out how I would get a hold of the representation of a
real number. I know it's represented at a sign bit, exponent, mantissa, but
I'm trying to store this real number in RAM, meaning I have to pass it in as
a STD_LOGIC_VECTOR, so somehow I need to convert a real to a
STD_LOGIC_VECTOR. Is there any way to do this?

Also, I have to divide the real numbers so I'm trying to figure out the best
way to do it. Here are my two choices:
1. just use the division operator provided for real numbers
2. use the XiLinx dividor module provided in XiLinxCoreLib.

If anyone could tell me the pros and cons of using one over the other that
would be fantastic.

Thanks all,

Jeremy

--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis
Director of Training mailto:Jim@SynthWorks.com
SynthWorks Design Inc. http://www.SynthWorks.com
1-503-590-4787

Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

 

[Ajeetha Kumari]

Hi Chen,
Please visit http://www.stefanvhdl.com/

HTH,
Ajeetha

http://www.noveldv.com

c.chen@gmx.de (Chao) wrote in message news:<8228a344.0307011314.50ab0df7@posting.google.com>...

Hello, there.

I want to study some tutorial examples dealing with advanced VHDL testbench,
for example, FILE operation to simplify the simulation procedure.

Does anybody have some links for these information? Thanks in advance!

C. Chen.

 

[Allan Herriman]

On Wed, 2 Jul 2003 07:30:46 +0200, "John T." <john@dat.com> wrote:

What does it mean when I declare values in the entity, for example:

ENTITY test IS
PORT(
dummy_1: IN std_logic := '1';
dummy_2: IN std_logic := '0';

dummy_3: OUT std_logic := '1';
dummy_4: OUT std_logic := '1';
dummy_5: OUT std_logic := '0'

);
END ENTITY test;

Is this some sort of starting values? Are they only used in simulation
or......?

1. For the input ports, this is the value that the signal will take
if the port is left open (either by being mapped to 'open' in the port
map, or by being left out of the port map altogether).
This works perfectly well in both simulation and synthesis, as long as
you aren't using tools supplied by Synopsys (in which case the default
value will be 0 regardless of the value you specified).

2. For the output ports, this is the value that the drivers will have
at elaboration time. If there are no drivers within the architecture
(i.e. you haven't made an assignment to the port of the form
dummy_1 <= something; ) this is the value of (the driver of) the
output port forever. Otherwise it is the value the port has until the
first signal assignment to the port runs, typically 1 delta cycle into
the simulation.


I don't usually see default values used for output ports in
synthesisable code. It can be useful to eliminate glitches in
simulation though, e.g. if the architecture is driving (say) '1', and
there's no initial value on the port, the output will be 'U' for 1
delta cycle before changing to '1'. With the initial value, it will
simply be '1'.

Another way of stating that is:
If you don't provide a value, the language provides an implicit
initialiser of 'U', e.g.

dummy_3: OUT std_logic := 'U';


Regards,
Allan.

 

[Ralf Hildebrandt]

Hi Aaron!

pair_arrayC : FOR col IN 0 TO row_length GENERATE
CONSTANT pair_inc : INTEGER := pair_inc + 1; --This, of course,
is wrong
--but the type of
thing I'd
--like to do.

If "pair_inc" only depends on the iteration of the for-loop, the
for-variable "col" ist nearly the same like "pair_inc". -> You can use a
(linear) derivative X*col+Y instead:

Ao(X*col+Y) <= A(row);

where X, Y are constants.

Ralf

 

[Egbert Molenkamp]

I think the 'distance' between the rows is not a constant.
The distance between the same column positions of row 0
and row 1 is 7, between row 1 and row 2 is 6, etc.

Maybe the following function handles the problem.
My synthesis tool has no problem with it.

FUNCTION index(row,col : IN integer) RETURN integer IS
TYPE int_arr_tp IS ARRAY (0 TO 6) OF integer;
CONSTANT lut : int_arr_tp := (0,7,13,18,22,25,27);
BEGIN
RETURN lut(row)+col;
END index;
BEGIN
pair_arrayR : FOR row IN 0 TO 6 GENERATE
CONSTANT row_length : NATURAL := 6 - row;
BEGIN
pair_arrayC : FOR col IN 0 TO row_length GENERATE
BEGIN
AB_Cells : IF (row<4) AND (col<4) GENERATE
Ao(index(row,col)) <= A(row);
Bo(index(row,col)) <= B(3-col);
END GENERATE AB_Cells;
etc.

Egbert Molenkamp


"Ralf Hildebrandt" <Ralf-Hildebrandt@gmx.de> wrote in message
news:bdurgt$10vlhh$4@ID-8609.news.dfncis.de...

Hi Aaron!


pair_arrayC : FOR col IN 0 TO row_length GENERATE
CONSTANT pair_inc : INTEGER := pair_inc + 1; --This, of course,
is wrong
--but the type of
thing I'd
--like to do.


If "pair_inc" only depends on the iteration of the for-loop, the
for-variable "col" ist nearly the same like "pair_inc". -> You can use a
(linear) derivative X*col+Y instead:

Ao(X*col+Y) <= A(row);

where X, Y are constants.

Ralf

 

[Thomas Kurth]

Hi Allan,

1. For the input ports, this is the value that the signal will take
if the port is left open (either by being mapped to 'open' in the port
map, or by being left out of the port map altogether).
This works perfectly well in both simulation and synthesis, as long as
you aren't using tools supplied by Synopsys (in which case the default
value will be 0 regardless of the value you specified).

Really? Which logic element is it in hardware that ties the pin to this
value?

2. For the output ports, this is the value that the drivers will have
at elaboration time. If there are no drivers within the architecture
(i.e. you haven't made an assignment to the port of the form
dummy_1 <= something; ) this is the value of (the driver of) the
output port forever. Otherwise it is the value the port has until the
first signal assignment to the port runs, typically 1 delta cycle into
the simulation.

When are these initial values executed? Do I have to use the reset pin
of the device? Or how does it know that there has not yet been an
operation on this pin (in HW)? For simulation I agree, that there might
be some logic which uses these defaults, but in synthesised code?

Greetz,

Thomas

--

No matter if you are going on-piste or off-piste, just hit the slope and
stay healthy!

For mail reply replace "nospam" with "kurth".

 

[Aaron McFarland]

If "pair_inc" only depends on the iteration of the for-loop, the
for-variable "col" ist nearly the same like "pair_inc". -> You can use a
(linear) derivative X*col+Y instead:

Ao(X*col+Y) <= A(row);

Ralf,
Thanks for the reply. It is true that pair_inc can be calculated from
only "row" and "col", but I think the equations are an iterative
summation (or subtraction) looking something like this for each row:

col + 7*row <-- Row 0
col + 7*row – 0 <-- Row 1
col + 7*row – 1 <-- Row 2
col + 7*row - 2 – 1 <-- Row 3
col + 7*row – 3 - 2 – 1 <-- Row 4
col + 7*row – 4 – 3 – 2 – 1 <-- Row 5
col + 7*row – 5 - 4 – 3 – 2 – 1 <-- Row 6

This would create the following values for pair_inc that correspond to
the combinations in the first post.

Col
0 1 2 3 4 5 6
Row --------------------
0 | 0 1 2 3 4 5 6
1 | 7 8 9 10 11 12
2 |13 14 15 16 17
3 |18 19 20 21
4 |22 23 24
5 |25 26
6 |27

Actually, they do not even really need to be in that order, but just
cover 0 to 27 with no bits missing. I need pair_inc to increment for
each iteration of Row *and* Col, not just Col.

--Aaron

 

[Aaron McFarland]

I think the 'distance' between the rows is not a constant.
The distance between the same column positions of row 0
and row 1 is 7, between row 1 and row 2 is 6, etc.

Yes, that is the problem better explained ;-)

Maybe the following function handles the problem.
My synthesis tool has no problem with it.

FUNCTION index(row,col : IN integer) RETURN integer IS
TYPE int_arr_tp IS ARRAY (0 TO 6) OF integer;
CONSTANT lut : int_arr_tp := (0,7,13,18,22,25,27);
BEGIN
RETURN lut(row)+col;
END index;

Egbert Molenkamp

Ah, I hadn't thought of a look up table. I think this should work,
I'll try it as soon as I get a chance tomorrow.

Thanks,
Aaron

 

[rajan]

Sorry, I forgot to define 'one' here, which is:
CONSTANT one : unsigned (15 DOWNTO 0) := (0 => '1', OTHERS => '0');

"rajan" <v.kakkar@chello.nl> wrote in message
news:CE%Ma.139291$gs1.8607331@amsnews03.chello.com...

Hello colleagues,

I have a demux as below. Is there any other way to write it better in
vhdl.

-- 4to16 demux with shift_left operation --
wire_sig <= STD_LOGIC_VECTOR (shift_left(one, to_integer(unsigned
(wire_w))));

regards,
rajan

 

[Tim Hubberstey]

rajan wrote:

Hello colleagues,

I have a demux as below. Is there any other way to write it better in vhdl.

-- 4to16 demux with shift_left operation --
wire_sig <= STD_LOGIC_VECTOR (shift_left(one, to_integer(unsigned
(wire_w))));

I seem to recall that I usually use something like:

demux : process( wire_w )
begin
wire_sig <= (others => '0');
wire_sig(to_integer(unsigned(wire_w)) <= '1';
end process demux;
--
Tim Hubberstey, P.Eng. . . . . . Hardware/Software Consulting Engineer
Marmot Engineering . . . . . . . VHDL, ASICs, FPGAs, embedded systems
Vancouver, BC, Canada . . . . . . . . . . . http://www.marmot-eng.com

 

[Ajeetha Kumari]

Hi,
The skeleton that you have show should do the job, did you find any problem?

Ajeetha
http://www.noveldv.com

"Ronny Hengst" <ballu_baer@gmx.de> wrote in message news:<be3cn8$p16p$1@ID-163925.news.dfncis.de>...

Good morning

In my testbench I want to read in a file synchronous to the desginclock.
Every rising edge reading one line.
For example

....
BEGIN
WHILE (endfile(stimulus) = false) LOOP

IF clk'event AND clk = '1' THEN

READLINE(stimulus, lin);
READ(lin,str_var,boo);
.....

Does anybody have some information? Thanks in advance!

 

[Willem Oosthuizen]

I can put the types in a PACKAGE, but how do I pass the generics to the
PACKAGE?

"Willem Oosthuizen" <willy@asic.co.za> wrote in message
news:begood$1u5$1@ctb-nnrp2.saix.net...

How do I do multi-dimentional arrays in components using generics

I tried the following. This does not work. I need to define the type
array(Depth -1 downto 0) of std_logic_vector(Width-1 downto 0) and
type array(Depth -2 downto 0) of std_logic_vector(Width-2 downto 0)
somewhere. But where?

COMPONENT Reduce is
generic
( Width : integer;
Depth : integer
);
port
( D_IN : IN array(Depth -1 downto 0) of std_logic_vector(Width-1 downto
0);
Q : OUT array(Depth -2 downto 0) of std_logic_vector(Width-2
downto
0);
);
end COMPONENT;

 

[Jonathan Bromley]

Hi Willem,

"Willem Oosthuizen" <willy@asic.co.za> wrote in message
news:begood$1u5$1@ctb-nnrp2.saix.net...
How do I do multi-dimentional arrays in components using generics

I tried the following. This does not work. I need to define the type
array(Depth -1 downto 0) of std_logic_vector(Width-1 downto 0) and
type array(Depth -2 downto 0) of std_logic_vector(Width-2 downto 0)
somewhere. But where?
[and then...]
I can put the types in a PACKAGE, but how do I pass the generics to the
PACKAGE?

This is all a bit horrible in VHDL. When you make an array of something,
the full details of that "something" must be known. Your need for a
parameterisable 2-dimensional array is usually solved in one of the
following ways:

(1) Use a true 2-dimensional array
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

type Arr2D is array (Depth-1 downto 0, Width-1 downto 0) of std_logic;

This is legal VHDL, and you can then create arrays and subscript them:

signal S: Arr2D;
....
S(3,4) <= '0';

But unfortunately it doesn't play well with std_logic_vector
because there is no easy way to copy a row or column of this 2-d
array to/from a 1-D vector - you have to use a FOR loop.

(2) Put the subtype in a package
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

as you suggested...

package MyTypes is
constant Width: integer; --- deferred constant, no value
subtype Row_T is std_logic_vector(Width-1 downto 0);
end;

....
type Vec2D is array(Depth-1 downto 0) of Row_T;

But then, as you say, you need "to pass a generic
into the package". You can't do that. There is only
one "instance" of a package in any given VHDL simulation,
so the package can't have a generic. I've got close to
what you need by using a deferred constant; you set
up the deferred constant's value in the package body:

package body MyTypes is
constant Width: integer := 5;
end;

This package body can be compiled separately, just before
you elaborate the design, but the same Width value will apply
throughout the simulation.

(3) Fake it up with a big 1-D array
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

No help at all, because you can't take a slice
that has non-static bounds.

~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

Sorry I can't help more. It's a somewhat messy problem.

 

[Mike Treseler]

Ken McElvain wrote:

Jon wrote:

If you declare a signal in a package and you include the package
then the signal can be globally used by all architectures that
reference that package. This is for simulation only and will not
work for synthesis.

This will work for synthesis in Synplify Pro 7.3.

Cool. Never seen that in synthesis before.
How did you get test cases?

-- Mike Treseler