J
John Popelish
Guest
Saran wrote:
the drain conductance is as high as the maker can make it. We are
stuck with what is available based on physics and the state of
technology at the time the device was made. If they make the
transistor larger, to raise the drain current, the gate capacitance
goes up. If they make the transistor smaller to shrink the gate
capacitance, the drain current goes down. So the details of gate
insulation thickness, channel doping profiles, and lots of other
details are the difference between the best combination and average
(or below average) performance. This is what keeps chip designers
working overtime and forever.
just a common source amplifier) never holds the gate biased half way
on, but is always either saturated full on, full off, or is
transitioning between those saturation values as fast as it can charge
the gate capacitance.
For analog circuits (like opamps) there are usually two current
mirrors battling it out, one trying to charge the gate up and one
trying to dump the charge out of it, and in the steady state case, one
current mirror is pouring current into the other one, and the gate
charge is sitting unchanging somewhere at a middle voltage. Then the
two mirrors unbalance from a change in the signal and the gate swings
to another voltage, till the feedback rebalances the mirrors to a
standstill.
For instance, in this simple opamp:
http://www.arky.ru/audio/sprav/datasheets/ca3130.pdf
Q3 and Q5 are a pull up current mirror (that supplies a constant pull
up current) and Q11 is a variable pull down current source dependent
on the balance of the two input voltages. The output of the opamp
(the drains of Q8 and Q12) depends on what voltage there is on the
gates of Q8 and Q12 when the pull up and pull down current sources on
their gates become equal and stop supplying either pull up or pull
down current to charge them. If those two currents are not equal, the
remainder will go into changing the gate voltage and the output
voltage will be in slew.
The gate capacitance is as low as the maker knows how to make it, andThanks a ton, John. It is conceptually clear now.
I have one question, how do we know how much current we have to
generate from a current mirror to bias a transistor. I know this is a
vague question, what I mean is, the gate capacitance determines the
rate at which the gate will be charged, right? So, are the gate
capacitances values standard for different transistors? Where are they
available from?
the drain conductance is as high as the maker can make it. We are
stuck with what is available based on physics and the state of
technology at the time the device was made. If they make the
transistor larger, to raise the drain current, the gate capacitance
goes up. If they make the transistor smaller to shrink the gate
capacitance, the drain current goes down. So the details of gate
insulation thickness, channel doping profiles, and lots of other
details are the difference between the best combination and average
(or below average) performance. This is what keeps chip designers
working overtime and forever.
If the circuit is logic, the current source (not usually a mirror, butFor instance, in an example, if the author says that a current mirror
outputs constantly 200nA to the input of the gate of some transistor
M1, he means that the gate voltage is being maintained constant
(unchaged) with this small current. The exact values, I assume, can be
obtained from the specific data sheets are manuals.
just a common source amplifier) never holds the gate biased half way
on, but is always either saturated full on, full off, or is
transitioning between those saturation values as fast as it can charge
the gate capacitance.
For analog circuits (like opamps) there are usually two current
mirrors battling it out, one trying to charge the gate up and one
trying to dump the charge out of it, and in the steady state case, one
current mirror is pouring current into the other one, and the gate
charge is sitting unchanging somewhere at a middle voltage. Then the
two mirrors unbalance from a change in the signal and the gate swings
to another voltage, till the feedback rebalances the mirrors to a
standstill.
For instance, in this simple opamp:
http://www.arky.ru/audio/sprav/datasheets/ca3130.pdf
Q3 and Q5 are a pull up current mirror (that supplies a constant pull
up current) and Q11 is a variable pull down current source dependent
on the balance of the two input voltages. The output of the opamp
(the drains of Q8 and Q12) depends on what voltage there is on the
gates of Q8 and Q12 when the pull up and pull down current sources on
their gates become equal and stop supplying either pull up or pull
down current to charge them. If those two currents are not equal, the
remainder will go into changing the gate voltage and the output
voltage will be in slew.