M
matt
Guest
On Wed, 22 Feb 2006 16:37:33 +0100, "petrus bitbyter"
<pieterkraltlaatditweg@enditookhccnet.nl> wrote:
as he's not replying to his emails.
"All ROM and RAM on this Memory Board is initially decoded by the
82s153 FPLA at location U10. The FPLA enables address decoders based
on the upper 3 address bits of the address bus. Additionally, the FPLA
prevents ROM and RAM access during certain system processes including:
refresh cycles, active resets, I/O requests and a architecture
specific signal called /BUZOFF. The FPLA contains 5 address inputs and
7 status line inputs. Outputs of the FPLA are 4 decoder enable lines
and 1 transceiver direction select line. The enable line for ROMs X1
through X4 (74LS139 at U8, pin 1) is selected on addresses x0000-x3fff
( !a15, !a14). The 4 ROMs are then selected off of a13 and a 12 by the
lower half of the 139 decoder at U8. All the other selects work
similarly. The second half of U8 (pin 15, enable) selects ROMs X5-X8
(a15, !a14), the lower half of U9 (pin 1, enable) selects the ROMs at
X9 and X10 (a15, a14, !a13)and the upper half of U9 (pin 15 enable)
selects one of the 4 RAMs (a15, a14, a13) based on address lines a11
and a12).
The FPLA also selects the direction of the 74ls245 transceiver at U17.
On a write, pin 1 of U17 is held high to allow data to flow from the
processor data bus to the RAM/ROM board data bus, on a read the line
is held low and the data flows in the opposite direction. Most of the
additional circuitry on the ROM board deals with selecting the RAM at
X21 for high score and setup information. The three 74ls244s at U16,
U15 and U 11 are all used as line drivers with all of their select
lines tied low permanently.
The original FPLA used is a Signetics 82s153, which is now obsolete, a
modern replacement is a Signetics pls153, however I have not been able
to get a good copy of one so I had to write a replacement using a PLD
(GAL16V8D)."
http://web.archive.org/web/20020331203553/http://my.erinet.com/~jamesm/tech/roto/roto.jed
manual (12 MBytes! with schems at the end) can be found in this file:
http://arcarc.xmission.com/PDF%20Arcade%20Manuals%20and%20Schematics/Robby%20Roto.pdf
you'll need to look at the for the 'Memory Board'. The device in
question is the PLS at location U10
BTW, the quality of the schems is poor in places, but just about
readable.
Many thanks.
<pieterkraltlaatditweg@enditookhccnet.nl> wrote:
Really? Ugh - confusing!So the equations would then be converted back to a JEDEC file?
Sure, but JEDECs differ widely for different components. They often even
differ for the same component type but other manufacturer.
:-((As for the speed itself I shouldn't expect problems. According to the
Philips datasheet the standard N82S153 is rated for 40ns, the N82S153A is
rated for 30ns. So your 25ns GAL may be too fast rather then too slow. But
in that case I consider it either a poor design or the use of some special
trick. Which will not help you, I'm afraid.
Same board, yup (well, same design, same manufacturer, etc).BTW It worked for someone else. Do you mean same board,
Same GAL type: GAL16V8D - not sure what speed or brand he used thoughsame 82S153 content
and same object GAL? (So same type and brand?)
as he's not replying to his emails.
I'll quote from the chap who came up with the JEDEC:Any idea what the GAL is
supposed to do?
"All ROM and RAM on this Memory Board is initially decoded by the
82s153 FPLA at location U10. The FPLA enables address decoders based
on the upper 3 address bits of the address bus. Additionally, the FPLA
prevents ROM and RAM access during certain system processes including:
refresh cycles, active resets, I/O requests and a architecture
specific signal called /BUZOFF. The FPLA contains 5 address inputs and
7 status line inputs. Outputs of the FPLA are 4 decoder enable lines
and 1 transceiver direction select line. The enable line for ROMs X1
through X4 (74LS139 at U8, pin 1) is selected on addresses x0000-x3fff
( !a15, !a14). The 4 ROMs are then selected off of a13 and a 12 by the
lower half of the 139 decoder at U8. All the other selects work
similarly. The second half of U8 (pin 15, enable) selects ROMs X5-X8
(a15, !a14), the lower half of U9 (pin 1, enable) selects the ROMs at
X9 and X10 (a15, a14, !a13)and the upper half of U9 (pin 15 enable)
selects one of the 4 RAMs (a15, a14, a13) based on address lines a11
and a12).
The FPLA also selects the direction of the 74ls245 transceiver at U17.
On a write, pin 1 of U17 is held high to allow data to flow from the
processor data bus to the RAM/ROM board data bus, on a read the line
is held low and the data flows in the opposite direction. Most of the
additional circuitry on the ROM board deals with selecting the RAM at
X21 for high score and setup information. The three 74ls244s at U16,
U15 and U 11 are all used as line drivers with all of their select
lines tied low permanently.
The original FPLA used is a Signetics 82s153, which is now obsolete, a
modern replacement is a Signetics pls153, however I have not been able
to get a good copy of one so I had to write a replacement using a PLD
(GAL16V8D)."
Here it is from the guy's site:Any problem posting the JEDEC(s) you have?
http://web.archive.org/web/20020331203553/http://my.erinet.com/~jamesm/tech/roto/roto.jed
I don't know how to extract a page or two from a PDF, but the whole(Part of) the
schematic?
manual (12 MBytes! with schems at the end) can be found in this file:
http://arcarc.xmission.com/PDF%20Arcade%20Manuals%20and%20Schematics/Robby%20Roto.pdf
you'll need to look at the for the 'Memory Board'. The device in
question is the PLS at location U10
BTW, the quality of the schems is poor in places, but just about
readable.
Many thanks.