checking if a register is undefined

[rekz]

Is there a way to check if the value of a register in verilog is
undefined? If there is then how?

 

[Muzaffer Kal]

On Wed, 24 Mar 2010 10:02:55 -0700 (PDT), rekz <aditya15417@gmail.com>
wrote:

Is there a way to check if the value of a register in verilog is
undefined? If there is then how?

Yes; "if (fooreg === X)"

--
Muzaffer Kal

DSPIA INC.
ASIC/FPGA Design Services

http://www.dspia.com

 

[Dave Rich]

On Mar 24, 10:02 am, rekz <aditya15...@gmail.com> wrote:

Is there a way to check if the value of a register in verilog is
undefined? If there is then how?

In Verilog, use the exclusive xor reduction operator to produce a
single bit. If the result is 1'bx, at least one bit of the register
was X

if (^myreg === 1'bx) ...


In SystemVerilog, you can use

if ($isunkown(myreg)) ...

 

[johnp]

On Mar 24, 10:02 am, rekz <aditya15...@gmail.com> wrote:

Is there a way to check if the value of a register in verilog is
undefined? If there is then how?

If you mean in simulation, then yes, you can check for X, see other
replies. If you mean in actual h/w, ie, synthesized design, then the
answer is no.

John Providenza