Guest
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
signal WRaddr : unsigned(11 downto 0);
if rising_edge(CLK) then
if WRaddr/="111111111111" then
WRaddr <= WRaddr +1;
end if;
end if;
How do I write this so I can easily
change the length of WRaddr?
TIA
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
signal WRaddr : unsigned(11 downto 0);
if rising_edge(CLK) then
if WRaddr/="111111111111" then
WRaddr <= WRaddr +1;
end if;
end if;
How do I write this so I can easily
change the length of WRaddr?
TIA