change variable in case statement

[vtb]

Hello,

I have a problem with logic of case statement in vhdl. I wonder is the variable that selects the case condition can be changed within the statement. To clarify:

process(clk)

variable aaa: std_logic_vector(2 downto 0):="000";

case aaa is

when "000" =>
if () then
something
end if;
aaa := aaa+1;

when "001" =>
something
aaa := aaa+1;

when others =>
-- sequential statements

when others =>
-- sequential statements

end case ;

end process;

When I tried to synthesize a code with that algorithm, it displays an error. What is the problem here? Can't I change the variable within the case? Or the problem is about the if statement in the case?

If anyone can help, I'll appreciate it.

 

[rickman]

On 9/11/2012 1:57 PM, vtb wrote:

Hello,

I have a problem with logic of case statement in vhdl. I wonder is the variable that selects the case condition can be changed within the statement. To clarify:

process(clk)

variable aaa: std_logic_vector(2 downto 0):="000";

case aaa is

when "000" =
if () then
something
end if;
aaa := aaa+1;

when "001" =
something
aaa := aaa+1;

when others =
-- sequential statements

when others =
-- sequential statements

end case ;

end process;

When I tried to synthesize a code with that algorithm, it displays an error. What is the problem here? Can't I change the variable within the case? Or the problem is about the if statement in the case?

If anyone can help, I'll appreciate it.

Like Andy said, what was the error message? I don't see anything wrong
with modifying the variable you are examining because the cases are all
mutually exclusive and once you are in a when clause, the part of the
case statement that examines the variable is done.

Maybe your synthesizer is unique in that regard. Is it one of the main
stream tools?

Rick

 

[Andy]

I've used variables for the state in finite state machines for a long time now. Never had a problem with it, including assigning the state register inside the case statement. I think you need to look elsewhere for the source of your error.

What did the error message actually say?

If your included code is a faithful copy of the code you synthesized, it is not a recognized, synthesizable, synchronous process. Read up on how to code synthesizable synchronous (clocked) processes. Hint: you need a clock edge detection statement, like "if rising_edge(clk) then".

Depending on the target architecture and the synthesis tool, variable initialization in the declaration may not be implemented in HW, and the state machine would not reliably start in the correct state.

Andy

 

I'm using ISE 12.4 and it is a video maker code. I'll post my code here but it is too long, I'm sorry for the inconvenience. Now I got rid of the error and the code is implemented on fpga but does not work in the way it is intended. What I'm trying to do is displaying a counter on the screen. "cnt" should count from 0 to 2 where "decimalcnt" should stay 0. (next, I'll also update it but not yet) The only output I get now is a "0" on pixels where decimalcnt shopuld appear(it's correct) but I see nothing for "cnt", not even a "0". So, the first case statemnt is not working.

[code:1:ee76d14c6b]
PROCESS (h_position, v_position)
variable cnt : std_logic_vector(3 downto 0 ):="0000";
variable decimalcnt: std_logic_vector(3 downto 0):="0000";
BEGIN
IF ((hareketsiz_hedef > "000") AND (h_position >= YK4) AND (h_position < YK4+YB4) AND (v_position >= DK4) AND (v_position < DK4+DB4)) THEN
y <= GS4 & "00";
cr <= CR4 & "00";
cb <= CB4 & "00";
ELSIF ((hareketsiz_hedef > "001") AND (h_position >= YK5) AND (h_position < YK5+YB5) AND (v_position >= DK5) AND (v_position < DK5+DB5)) THEN
y <= GS5 & "00";
cr <= CR5 & "00";
cb <= CB5 & "00";
ELSE
if ( f='1') then
case1: CASE cnt IS
WHEN "0000" =>
IF ((hareketsiz_hedef > "000") AND (h_position >= "1010001010") AND (h_position < "1010010100") AND (v_position >= "0110100100") AND (v_position < "0110100110")) OR
((hareketsiz_hedef > "000")AND (h_position >= "1010001010") AND (h_position < "1010001100") AND (v_position >= "0110100110") AND (v_position < "0110101110")) OR
((hareketsiz_hedef > "000")AND (h_position >= "1010001010") AND (h_position < "1010010100") AND (v_position >= "0110101100") AND (v_position < "0110101110")) OR
((hareketsiz_hedef > "000") AND (h_position >= "1010010010") AND (h_position < "1010010100") AND (v_position >= "0110100110") AND (v_position < "0110101110"))THEN
y <= "0001000000";
cr <= "1000000000";
cb <= "1000000000";
ELSIF((hareketsiz_hedef > "000") AND(h_position >= "1010001100") AND (h_position < "1010010010") AND (v_position >= "0110100100") AND (v_position < "0110101100")) THEN
y <= "1110101100";
cr <= "1000000000";
cb <= "1000000000";
END IF;
cnt := cnt +1;
WHEN "0001" =>
IF((hareketsiz_hedef > "000") AND(h_position >= "1010010010") AND (h_position < "1010010100") AND (v_position >= "0110100110") AND (v_position < "0110101110"))THEN
y <= "0001000000";
cr <= "1000000000";
cb <= "1000000000";
END IF;
cnt := cnt +1;
WHEN "0010" =>
IF ( (hareketsiz_hedef > "000")AND (h_position >= "1010001010") AND (h_position < "1010010100") AND (v_position >= "0110100100") AND (v_position < "0110100110")) OR
((hareketsiz_hedef > "000") AND (h_position >= "1010001010") AND (h_position < "1010001100") AND (v_position >= "0110101010") AND (v_position < "0110101110")) OR
((hareketsiz_hedef > "000")AND(h_position >= "1010001010") AND (h_position < "1010010100") AND (v_position >= "0110101100") AND (v_position < "0110101110")) OR
((hareketsiz_hedef > "000")AND (h_position >= "1010010010") AND (h_position < "1010010100") AND (v_position >= "0110100110") AND (v_position < "0110101010")) OR
((hareketsiz_hedef > "000") AND(h_position >= "1010001010") AND (h_position < "1010010100") AND (v_position >= "0110101000") AND (v_position < "0110101010"))THEN
y <= "0001000000";
cr <= "1000000000";
cb <= "1000000000";
END IF;
cnt :=cnt+1;
WHEN others => null;
END CASE;
case2: CASE decimalcnt IS
WHEN "0000" =>
IF ((hareketsiz_hedef > "000") AND(h_position >= "1001111011") AND (h_position < "1010000101") AND (v_position >= "0110100100") AND (v_position < "0110100110")) OR
((hareketsiz_hedef > "000")AND (h_position >= "1001111011") AND (h_position < "1001111101") AND (v_position >= "0110100111") AND (v_position < "0110101110")) OR
((hareketsiz_hedef > "000")AND (h_position >= "1010000011") AND (h_position < "1010000101") AND (v_position >= "0110100111") AND (v_position < "0110101110")) OR
((hareketsiz_hedef > "000") AND (h_position >= "1001111011") AND (h_position < "1010000101") AND (v_position >= "0110101100") AND (v_position < "0110101110"))THEN
y <= "0001000000";
cr <= "1000000000";
cb <= "1000000000";
ELSIF((hareketsiz_hedef > "000")AND(h_position >= "1001111101") AND (h_position < "1010000011") AND (v_position >= "0110100100") AND (v_position < "0110101100")) THEN
y <= "1110101100";
cr <= "1000000000";
cb <= "1000000000";
END IF;
WHEN "0001" =>
IF ((hareketsiz_hedef > "000")AND(h_position >= "1010000011") AND (h_position < "1010000101") AND (v_position >= "0110100100") AND (v_position < "0110101110"))THEN
y <= "0001000000";
cr <= "1000000000";
cb <= "1000000000";
END IF;
WHEN "0010" =>
IF ( (hareketsiz_hedef > "000")AND (h_position >= "1001111011") AND (h_position < "1010000101") AND (v_position >= "0110100100") AND (v_position < "0110100110")) OR
((hareketsiz_hedef > "000") AND (h_position >= "1001111011") AND (h_position < "1010000101") AND (v_position >= "0110101010") AND (v_position < "0110101110")) OR
((hareketsiz_hedef > "000")AND(h_position >= "1001111011") AND (h_position < "1010000101") AND (v_position >= "0110101100") AND (v_position < "0110101110")) OR
((hareketsiz_hedef > "000")AND (h_position >= "1001111011") AND (h_position < "1010000101") AND (v_position >= "0110100110") AND (v_position < "0110101010")) OR
((hareketsiz_hedef > "000") AND(h_position >= "1001111011") AND (h_position < "1010000101") AND (v_position >= "0110101000") AND (v_position < "0110101010"))THEN
y <= "0001000000";
cr <= "1000000000";
cb <= "1000000000";
END IF;
WHEN "0011" =>
IF ((hareketsiz_hedef > "000")AND(h_position >= "1001111011") AND (h_position < "1010000101") AND (v_position >= "0110100100") AND (v_position < "0110100110")) OR
((hareketsiz_hedef > "000") AND(h_position >= "1001111011") AND (h_position < "1010000101") AND (v_position >= "0110101100") AND (v_position < "0110101110")) OR
((hareketsiz_hedef > "000") AND(h_position >= "1001111011") AND (h_position < "1010000101") AND (v_position >= "0110100110") AND (v_position < "0110101110")) OR
((hareketsiz_hedef > "000") AND(h_position >= "1001111011") AND (h_position < "1010000101") AND (v_position >= "0110101000") AND (v_position < "0110101010"))THEN
y <= "0001000000";
cr <= "1000000000";
cb <= "1000000000";
END IF;
WHEN others =>
null; END CASE; end if;
END IF;END PROCESS;
[/code:1:ee76d14c6b]

 

Andy, I do not have an edge detection statement(event) because I want my variables to change everytime h_position and v_position changes, not with respect to rising/falling edge. Is not it possible?

 

[rickman]

On 9/12/2012 4:24 AM, demiralhazal@gmail.com wrote:

Andy, I do not have an edge detection statement(event) because I want my variables to change everytime h_position and v_position changes, not with respect to rising/falling edge. Is not it possible?

If your assignments are to be combinatorial, then every input to any
assignments must be in the sensitivity list of the process. For
example, hareketsiz_hedef is in an IF statement containing an assignment
statement. That means it is an input to the assignment and must show up
in the sensitivity list. Without that the simulation won't match the
functioning of the circuit.

I can't say why your circuit won't work in the chip because you likely
haven't simulated it. If you simulate it you can watch all the internal
signals and be able to tell what is going wrong. On the chip it is much
harder to do that.

Try fixing your code to be proper VHDL and run simulations. For every
hour you spend in simulation you save a day on the workbench.

Rick

 

[Paul Uiterlinden]

rickman wrote:

On 9/12/2012 4:24 AM, demiralhazal@gmail.com wrote:
Andy, I do not have an edge detection statement(event) because I want my
variables to change everytime h_position and v_position changes, not with
respect to rising/falling edge. Is not it possible?

If your assignments are to be combinatorial, then every input to any
assignments must be in the sensitivity list of the process. For
example, hareketsiz_hedef is in an IF statement containing an assignment
statement. That means it is an input to the assignment and must show up
in the sensitivity list.

Unless of course hareketsiz_hedef is a constant. That however is unknown,
because only part of the code is shown.

 

Unless of course hareketsiz_hedef is a constant. That however is unknown,

I could'nt resist to google hareketsiz:

hareketsiz (adj.):
calm, frozen, immobile, immovable, inactive, inert, motionless, nonmoving, peaceful, quiet, rooted, serene, stagnant, static, statical (physics), stationary, still, stock-still, tranquil, unmoving

What a beautiful way to express a "constant"!

- Pontus

 

[Andy]

Variables can be used in combinatorial processes, but are subject to the same latch-inference issues as signals. Follow the simple rule: "write before read" for any signal or variable, and you won't get a latch. The simplest way to ensure this is to include a default assignment for every signal and variable right up front.

Signals that are used for intermediate results in combinatorial processes should be replaced with variables, but if not, the signal MUST be in the sensitivity list. Variables and constants cannot be added to the sensitivity list.

Andy

 

[rickman]

On 9/12/2012 5:01 PM, pontus.stenstrom@gmail.com wrote:

Unless of course hareketsiz_hedef is a constant. That however is unknown,

I could'nt resist to google hareketsiz:

hareketsiz (adj.):
calm, frozen, immobile, immovable, inactive, inert, motionless, nonmoving, peaceful, quiet, rooted, serene, stagnant, static, statical (physics), stationary, still, stock-still, tranquil, unmoving

What a beautiful way to express a "constant"!

- Pontus

It very well could be, but he has other symbols that appear to be
constants like, GS4, CS5, etc, which are formatted differently and
hareketsiz_hedef is compared to string constants that are unlikely to
compared to a constant unless it is controlling a mode of compiling the
program perhaps.

The definition you used was for the adjective hareketsiz. The noun
hareketsiz is defined as,

come to a halt, come to a standstill, come to a stop, halt, pull up,
rest, stand, stand still, stop

Hedef is defined as,

aim, butt, end, goal, object, objective, purpose, target

Combining the two it might be interpreted as "stop at the end" or "stop
target".

Perhaps the OP can elucidate us further?

Rick