Can PLL Freq Error be zero?

[Genome]

"John Larkin" <jjSNIPlarkin@highTHISlandPLEASEtechnology.XXX> wrote in
message news:eeeb3113laro81drftuqt337965hun13t4@4ax.com...

On Mon, 14 Mar 2005 13:53:32 GMT, "Genome" <ilike_spam@yahoo.co.uk
wrote:


"Erikk" <123@abc.com> wrote in message
news:fm5a31hbdedc9b7u54aqhst80b2bvlo46c@4ax.com...

All PLL chips specify phase noise and application notes talk about how
to measure it but I haven't seen anything that specifies the freq
error. If the reference frequency is 100.0000000MHz and the PLL is
designed to multiply the input frequency by integer 2, is the output
freq 200.0000000MHz with phase noise?

Not really knowing the details, I expected some finite error in the
output frequency, say 1ppm error or 200Hz in this case, which seemed
like a believable number. But then I was wondering, can a PLL be in
lock without input and output edges lined which I think means the freq
error is zero? I know the phase noise will be there. I just don't
understand how the lock happens with even 1ppm freq error.

If the freq error is a fact of life, how can it be reduced in a fixed
frequency PLL application?



FUCK YOU

I'd like to know the effect of the divider on the loop gain. If the VCO
changes its output frequency.... how does that propagate down the
divider.

DNA


Easy. Given an Umpteen mhz vco with a Whatever vco constant in
mhz/volt, and a Somethingorother divider in the loop, just black-box
replace that whole mess with a readily available Radio Shack vco
having

U' = U / S

not to mention

W' = W / S

and go about your business. These aren't the droids we want.

John

Looks like the sort of shit I'd write but it's a piss poor imitation. There
is no content.

Is there a delay between the VCO changing its output frequency and that
change becoming apparent out of the arse end of the divider?

Might there be a difference between a ripple counter and a synchronous
counter?

These are important questions that will affect the stability of the loop.

DNA

 

[Reg Edwards]

With a phase-locked loop the frequency error is always zero. There may
be superimposed phase drift or variation or noise.

Only with automatic frequency control can the frequency drift.

 

[John Larkin]

On Thu, 17 Mar 2005 18:44:31 GMT, "Genome" <ilike_spam@yahoo.co.uk>
wrote:

"John Larkin" <jjSNIPlarkin@highTHISlandPLEASEtechnology.XXX> wrote in
message news:eeeb3113laro81drftuqt337965hun13t4@4ax.com...
On Mon, 14 Mar 2005 13:53:32 GMT, "Genome" <ilike_spam@yahoo.co.uk
wrote:


"Erikk" <123@abc.com> wrote in message
news:fm5a31hbdedc9b7u54aqhst80b2bvlo46c@4ax.com...

All PLL chips specify phase noise and application notes talk about how
to measure it but I haven't seen anything that specifies the freq
error. If the reference frequency is 100.0000000MHz and the PLL is
designed to multiply the input frequency by integer 2, is the output
freq 200.0000000MHz with phase noise?

Not really knowing the details, I expected some finite error in the
output frequency, say 1ppm error or 200Hz in this case, which seemed
like a believable number. But then I was wondering, can a PLL be in
lock without input and output edges lined which I think means the freq
error is zero? I know the phase noise will be there. I just don't
understand how the lock happens with even 1ppm freq error.

If the freq error is a fact of life, how can it be reduced in a fixed
frequency PLL application?



FUCK YOU

I'd like to know the effect of the divider on the loop gain. If the VCO
changes its output frequency.... how does that propagate down the
divider.

DNA


Easy. Given an Umpteen mhz vco with a Whatever vco constant in
mhz/volt, and a Somethingorother divider in the loop, just black-box
replace that whole mess with a readily available Radio Shack vco
having

U' = U / S

not to mention

W' = W / S

and go about your business. These aren't the droids we want.

John


Looks like the sort of shit I'd write but it's a piss poor imitation.

Just trying to communicate with the locals in their native tongue.

There
is no content.

Well, it does cover the basic loop math to account for the divider. I
thought that was what you were asking about.

Is there a delay between the VCO changing its output frequency and that
change becoming apparent out of the arse end of the divider?

Sure, but it's the same as the black-box substitution case for which I
was so severely castigated.

Might there be a difference between a ripple counter and a synchronous
counter?

These are important questions that will affect the stability of the loop.

Most VCOs don't respond instantly to a change of control voltage. If
there's a varicap, the path of Vvco to the cap is usually
bypassed/lowpass filtered, usually very slow compared to the
oscillator period. And at least for RF-range loops, the opamps and
phase detector filter are relatively slow. So unless the loop is
outrageously fast and wideband, adding a little delay in the divide
path is inconsequential.

But sure, if the divider delay is significant, then it's significant.

Is that better?

John

 

[Genome]

"John Larkin" <jjlarkin@highNOTlandTHIStechnologyPART.com> wrote in message
news:rnmj3195n36dh5cqhcrgkimbmkjoef3m2p@4ax.com...

On Thu, 17 Mar 2005 18:44:31 GMT, "Genome" <ilike_spam@yahoo.co.uk
wrote:

But sure, if the divider delay is significant, then it's significant.

Is that better?

John

OK.

Being thick I miss the meaning of,

U' = U / S

and

W' = W / S

DNA

 

[John Larkin]

On Thu, 17 Mar 2005 20:03:50 GMT, "Genome" <ilike_spam@yahoo.co.uk>
wrote:

"John Larkin" <jjlarkin@highNOTlandTHIStechnologyPART.com> wrote in message
news:rnmj3195n36dh5cqhcrgkimbmkjoef3m2p@4ax.com...
On Thu, 17 Mar 2005 18:44:31 GMT, "Genome" <ilike_spam@yahoo.co.uk
wrote:

But sure, if the divider delay is significant, then it's significant.

Is that better?

John



OK.

Being thick I miss the meaning of,

U' = U / S

and

W' = W / S

DNA

Oh. I meant that the 'new' VCO frequency (after substituting the black
box) is the old one scaled by the divisor thing, and likewise W' is
the effective new VCO constant (Hz/volt or whatever) after the
substitution. It's just like wrapping a dotted line around the
VCO+divider and replacing the whole mess with a slower, scaled VCO.

I'm sort of used to a notation where

G' is the new/scaled/denormalized/fudged value of G

which is what the filter folks do. But maybe that's not an accepted
convention.


John

 

[John Larkin]

On Thu, 17 Mar 2005 22:44:33 GMT, "Genome" <ilike_spam@yahoo.co.uk>
wrote:

"John Larkin" <jjlarkin@highNOTlandTHIStechnologyPART.com> wrote in message
news:jkvj311eeujkg4gu2nqctaqdlems2nusmc@4ax.com...
On Thu, 17 Mar 2005 20:03:50 GMT, "Genome" <ilike_spam@yahoo.co.uk
wrote:


"John Larkin" <jjlarkin@highNOTlandTHIStechnologyPART.com> wrote in
message
news:rnmj3195n36dh5cqhcrgkimbmkjoef3m2p@4ax.com...
On Thu, 17 Mar 2005 18:44:31 GMT, "Genome" <ilike_spam@yahoo.co.uk
wrote:

But sure, if the divider delay is significant, then it's significant.

Is that better?

John



OK.

Being thick I miss the meaning of,

U' = U / S

and

W' = W / S

DNA



Oh. I meant that the 'new' VCO frequency (after substituting the black
box) is the old one scaled by the divisor thing, and likewise W' is
the effective new VCO constant (Hz/volt or whatever) after the
substitution. It's just like wrapping a dotted line around the
VCO+divider and replacing the whole mess with a slower, scaled VCO.

I'm sort of used to a notation where

G' is the new/scaled/denormalized/fudged value of G

which is what the filter folks do. But maybe that's not an accepted
convention.


John


Oh, so S is the number by which things are divided, the divisor, and has
nothing to do with that Laplace stuff?

DNA

Well, I did specify that Somethingorother was the divider in the loop,
so it was perfectly obvious to me that S = divider ratio. There's only
26 letters on my keyboard, and it's not my fault that some lunatic
Frenchman decided to use S for something else.

Actually, I never use that Laplace stuff. I must have learned it once
in ancient times, because I didn't flunk very many of my EE courses,
but nowadays a quickie Bode plot is enough to stabilize simple loops,
and if it gets more complicated, or gets nonlinear, I just simulate.

I had an engineer a while back who was a whiz at this stuff... pages
of equations, root locus, polynomials in s-domain, all neatly solved.
But the answers usually made no sense, and when I pointed it out to
him he got pissed off (ie, angry in American.) As soon as I finished
paying for the legal fees to get him a green card, he quit.

John

 

[Terry Given]

John Larkin wrote:

On Fri, 18 Mar 2005 14:49:03 +1300, Terry Given <my_name@ieee.org
wrote:


John Larkin wrote:

On Thu, 17 Mar 2005 22:44:33 GMT, "Genome" <ilike_spam@yahoo.co.uk
wrote:



"John Larkin" <jjlarkin@highNOTlandTHIStechnologyPART.com> wrote in message
news:jkvj311eeujkg4gu2nqctaqdlems2nusmc@4ax.com...


On Thu, 17 Mar 2005 20:03:50 GMT, "Genome" <ilike_spam@yahoo.co.uk
wrote:



"John Larkin" <jjlarkin@highNOTlandTHIStechnologyPART.com> wrote in

message


news:rnmj3195n36dh5cqhcrgkimbmkjoef3m2p@4ax.com...


On Thu, 17 Mar 2005 18:44:31 GMT, "Genome" <ilike_spam@yahoo.co.uk
wrote:

But sure, if the divider delay is significant, then it's significant.

Is that better?

John



OK.

Being thick I miss the meaning of,

U' = U / S

and

W' = W / S

DNA



Oh. I meant that the 'new' VCO frequency (after substituting the black
box) is the old one scaled by the divisor thing, and likewise W' is
the effective new VCO constant (Hz/volt or whatever) after the
substitution. It's just like wrapping a dotted line around the
VCO+divider and replacing the whole mess with a slower, scaled VCO.

I'm sort of used to a notation where

G' is the new/scaled/denormalized/fudged value of G

which is what the filter folks do. But maybe that's not an accepted
convention.


John


Oh, so S is the number by which things are divided, the divisor, and has
nothing to do with that Laplace stuff?

DNA



Well, I did specify that Somethingorother was the divider in the loop,
so it was perfectly obvious to me that S = divider ratio. There's only
26 letters on my keyboard, and it's not my fault that some lunatic
Frenchman decided to use S for something else.

Actually, I never use that Laplace stuff. I must have learned it once
in ancient times, because I didn't flunk very many of my EE courses,
but nowadays a quickie Bode plot is enough to stabilize simple loops,
and if it gets more complicated, or gets nonlinear, I just simulate.

I had an engineer a while back who was a whiz at this stuff... pages
of equations, root locus, polynomials in s-domain, all neatly solved.
But the answers usually made no sense, and when I pointed it out to
him he got pissed off (ie, angry in American.) As soon as I finished
paying for the legal fees to get him a green card, he quit.

John

I aint your brother, so I p all over my equations.

(perhaps too cryptic?)

Cheers
Terry



Absolutely too cryptic.

John

"He aint heavy, he's my brother," sunbg by The Hollies (among others).
Alluding to Oliver Heaviside, who used the operator 'p' for 'd/dt'
rather than 's'

Cheers
Terry

 

[Jim Thompson]

On Fri, 18 Mar 2005 16:05:41 +1300, Terry Given <my_name@ieee.org>
wrote:

John Larkin wrote:
On Fri, 18 Mar 2005 14:49:03 +1300, Terry Given <my_name@ieee.org
wrote:


John Larkin wrote:

On Thu, 17 Mar 2005 22:44:33 GMT, "Genome" <ilike_spam@yahoo.co.uk
wrote:



"John Larkin" <jjlarkin@highNOTlandTHIStechnologyPART.com> wrote in message
news:jkvj311eeujkg4gu2nqctaqdlems2nusmc@4ax.com...


On Thu, 17 Mar 2005 20:03:50 GMT, "Genome" <ilike_spam@yahoo.co.uk
wrote:



"John Larkin" <jjlarkin@highNOTlandTHIStechnologyPART.com> wrote in

message


news:rnmj3195n36dh5cqhcrgkimbmkjoef3m2p@4ax.com...


On Thu, 17 Mar 2005 18:44:31 GMT, "Genome" <ilike_spam@yahoo.co.uk
wrote:

But sure, if the divider delay is significant, then it's significant.

Is that better?

John



OK.

Being thick I miss the meaning of,

U' = U / S

and

W' = W / S

DNA



Oh. I meant that the 'new' VCO frequency (after substituting the black
box) is the old one scaled by the divisor thing, and likewise W' is
the effective new VCO constant (Hz/volt or whatever) after the
substitution. It's just like wrapping a dotted line around the
VCO+divider and replacing the whole mess with a slower, scaled VCO.

I'm sort of used to a notation where

G' is the new/scaled/denormalized/fudged value of G

which is what the filter folks do. But maybe that's not an accepted
convention.


John


Oh, so S is the number by which things are divided, the divisor, and has
nothing to do with that Laplace stuff?

DNA



Well, I did specify that Somethingorother was the divider in the loop,
so it was perfectly obvious to me that S = divider ratio. There's only
26 letters on my keyboard, and it's not my fault that some lunatic
Frenchman decided to use S for something else.

Actually, I never use that Laplace stuff. I must have learned it once
in ancient times, because I didn't flunk very many of my EE courses,
but nowadays a quickie Bode plot is enough to stabilize simple loops,
and if it gets more complicated, or gets nonlinear, I just simulate.

I had an engineer a while back who was a whiz at this stuff... pages
of equations, root locus, polynomials in s-domain, all neatly solved.
But the answers usually made no sense, and when I pointed it out to
him he got pissed off (ie, angry in American.) As soon as I finished
paying for the legal fees to get him a green card, he quit.

John

I aint your brother, so I p all over my equations.

(perhaps too cryptic?)

Cheers
Terry



Absolutely too cryptic.

John


"He aint heavy, he's my brother," sunbg by The Hollies (among others).
Alluding to Oliver Heaviside, who used the operator 'p' for 'd/dt'
rather than 's'

Cheers
Terry

'p' is normalized 's'

...Jim Thompson
--
| James E.Thompson, P.E. | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona Voice480)460-2350 | |
| E-mail Address at Website Fax480)460-2142 | Brass Rat |
| http://www.analog-innovations.com | 1962 |

I love to cook with wine. Sometimes I even put it in the food.

 

[Terry Given]

Jim Thompson wrote:
[snip]

I aint your brother, so I p all over my equations.

(perhaps too cryptic?)

Cheers
Terry



Absolutely too cryptic.

John


"He aint heavy, he's my brother," sunbg by The Hollies (among others).
Alluding to Oliver Heaviside, who used the operator 'p' for 'd/dt'
rather than 's'

Cheers
Terry


'p' is normalized 's'

...Jim Thompson

"and of d/dt, the operator of time-differentiation, which will in the
following be denoted by p simply", O. Heaviside, Electrical Papers vol.
2, 1887

motor control guys use p = s + jw to transform from the stationary to
synchronously rotating reference frames.

Cheers
Terry

 

[Terry Given]

John Larkin wrote:

On Mon, 14 Mar 2005 00:10:41 -0500, Erikk <123@abc.com> wrote:


All PLL chips specify phase noise and application notes talk about how
to measure it but I haven't seen anything that specifies the freq
error. If the reference frequency is 100.0000000MHz and the PLL is
designed to multiply the input frequency by integer 2, is the output
freq 200.0000000MHz with phase noise?



Yes.


Not really knowing the details, I expected some finite error in the
output frequency, say 1ppm error or 200Hz in this case, which seemed
like a believable number. But then I was wondering, can a PLL be in
lock without input and output edges lined which I think means the freq
error is zero? I know the phase noise will be there. I just don't
understand how the lock happens with even 1ppm freq error.

If the freq error is a fact of life, how can it be reduced in a fixed
frequency PLL application?




In lock, the frequency error is zero. Two cycles of output for each
cycle of input. It's like a set of gears, one gear with 5 teeth and
the other with 10.

Belts have errors but gears have zero error. Same idea.

John

what about instantaneous error? gears have hysterisis (aka backlash)

(admittedly I'm being pedantic)

Cheers
Terry

 

[budgie]

On Sun, 13 Mar 2005 21:42:53 -0800, John Larkin
<jjSNIPlarkin@highTHISlandPLEASEtechnology.XXX> wrote:

On Mon, 14 Mar 2005 00:10:41 -0500, Erikk <123@abc.com> wrote:


All PLL chips specify phase noise and application notes talk about how
to measure it but I haven't seen anything that specifies the freq
error. If the reference frequency is 100.0000000MHz and the PLL is
designed to multiply the input frequency by integer 2, is the output
freq 200.0000000MHz with phase noise?


Yes.

Not really knowing the details, I expected some finite error in the
output frequency, say 1ppm error or 200Hz in this case, which seemed
like a believable number. But then I was wondering, can a PLL be in
lock without input and output edges lined which I think means the freq
error is zero? I know the phase noise will be there. I just don't
understand how the lock happens with even 1ppm freq error.

If the freq error is a fact of life, how can it be reduced in a fixed
frequency PLL application?



In lock, the frequency error is zero. Two cycles of output for each
cycle of input. It's like a set of gears, one gear with 5 teeth and
the other with 10.

Belts have errors but gears have zero error. Same idea.

and consider the phase noise to be like backlash in the gears ....

 

[Tim Hubberstey]

Terry Given wrote:

John Larkin wrote:

On Mon, 14 Mar 2005 00:10:41 -0500, Erikk <123@abc.com> wrote:


All PLL chips specify phase noise and application notes talk about how
to measure it but I haven't seen anything that specifies the freq
error. If the reference frequency is 100.0000000MHz and the PLL is
designed to multiply the input frequency by integer 2, is the output
freq 200.0000000MHz with phase noise?


Yes.

Not really knowing the details, I expected some finite error in the
output frequency, say 1ppm error or 200Hz in this case, which seemed
like a believable number. But then I was wondering, can a PLL be in
lock without input and output edges lined which I think means the freq
error is zero? I know the phase noise will be there. I just don't
understand how the lock happens with even 1ppm freq error.

If the freq error is a fact of life, how can it be reduced in a fixed
frequency PLL application?

In lock, the frequency error is zero. Two cycles of output for each
cycle of input. It's like a set of gears, one gear with 5 teeth and
the other with 10.
Belts have errors but gears have zero error. Same idea.

John

what about instantaneous error? gears have hysterisis (aka backlash)

(admittedly I'm being pedantic)

Isn't that just the equivalent of the phase noise already allowed for
earlier in the thread? ;-)
--
Tim Hubberstey, P.Eng. . . . . . Hardware/Software Consulting Engineer
Marmot Engineering . . . . . . . VHDL, ASICs, FPGAs, embedded systems
Vancouver, BC, Canada . . . . . . . . . . . http://www.marmot-eng.com

 

Erikk wrote:

All PLL chips specify phase noise and application notes talk about
how
to measure it but I haven't seen anything that specifies the freq
error. If the reference frequency is 100.0000000MHz and the PLL is
designed to multiply the input frequency by integer 2, is the output
freq 200.0000000MHz with phase noise?

Not really knowing the details, I expected some finite error in the
output frequency, say 1ppm error or 200Hz in this case, which seemed
like a believable number. But then I was wondering, can a PLL be in
lock without input and output edges lined which I think means the
freq
error is zero? I know the phase noise will be there. I just don't
understand how the lock happens with even 1ppm freq error.

If the freq error is a fact of life, how can it be reduced in a fixed
frequency PLL application?

You need to get a decent textbook on phase locked loops. I use Floyd M.
Gardner's "Phaselock Techniques" ISBN 0-471-04294-3 but it was
published in 1979.

Gardner makes the point that second order phase-locked loops (the sort
used in most practical applications) integrate the phase error to zero,
so that there is no finite error in output frequency, unless you get
cycle slipping, which ought to be rare to non-existent with a
reasonably clean input signal.

He backs up this proposition with extensive references to the then
published literature on the subject. A more recent textbook will
probably have lots more scholarly publications to refer to.

-------
Bill Sloman, Nijmegen

 

[John Larkin]

On Fri, 18 Mar 2005 08:10:37 -0800, "Larry Brasfield"
<donotspam_larry_brasfield@hotmail.com> wrote:

I was interviewed by a fellow once who, noting
the phrase "root locus" in my resume, got a gleam
in his eye and pulled out a special question he had
worked up for such claims. After I ascertained that
he really wanted me to work out the solution, right
there in his office, (while he did other work for 15
minutes or so), I did the work and handed it over
to him. He went immediately to the bottom line
and informed me it was wrong. I acknowledged
that possibility, but invited him to go with me thru
the derivation to find the error, a challenge he took
up readily. After another 30 minutes scrutinizing
each step, getting to the bottom without finding any
identifiable error, he pulled out a little worksheet
that I imagine was his derivation. We found his
error in short order, leading to a reaction that I
considered carefully later. The reaction? A plain
and apparently sincere thank-you, accompanied by
a smile. Needless to say, he was not the reason I
turned down the company's generous offer.

But the answers usually made no sense, and when I pointed it out to
him he got pissed off (ie, angry in American.)

One reason to have a few different analytical tools at
hand is for checking. 'Making sense', (when carefully
done and not confused for bare supposition), is one
of the better ones for that purpose.

The thing about the big-equations approach (say, a single expression
for a transfer function, or a matrix solution to a complex resistive
circuit) is that at some point it just becomes a heap of math without
intuitive meaning. So when the voltage at a node becomes 4e-14 or you
wind up needing magahenry inductors, all you can do is accept the
result. I prefer breaking up complex problems into smaller blocks
(say, stepwise thevenin reduction as opposed to matrix solution) so
that the intermediate steps have physical meaning and can be checked
for sanity. Which means I do a lot more numerical solutions than
symbolic ones; it's easier to carry forward a single number than a
whole equation.

But when things get nonlinear - and all interesting systems are
nonlinear - the brute-force analytical stuff collapses anyhow, so you
are faced with linear analysis of regional cases or simulation or just
plain instinct.

It's lucky for me, I guess, that picosecond-speed systems are seldom
arranged into feedback loops. Everything tends to proceed from input
to output in one direction.

John

 

[Fred Bloggs]

HEY EVERYONE- READ ANOTHER LARRY BRASFIELD ABOUT HE SHOWED SOMEONE ELSE
HOW GREAT HE IS:

Larry Brasfield wrote:

I was interviewed by a fellow once who, noting
the phrase "root locus" in my resume, got a gleam
in his eye and pulled out a special question he had
worked up for such claims. After I ascertained that
he really wanted me to work out the solution, right
there in his office, (while he did other work for 15
minutes or so), I did the work and handed it over
to him. He went immediately to the bottom line
and informed me it was wrong. I acknowledged
that possibility, but invited him to go with me thru
the derivation to find the error, a challenge he took
up readily. After another 30 minutes scrutinizing
each step, getting to the bottom without finding any
identifiable error, he pulled out a little worksheet
that I imagine was his derivation. We found his
error in short order, leading to a reaction that I
considered carefully later. The reaction? A plain
and apparently sincere thank-you, accompanied by
a smile. Needless to say, he was not the reason I
turned down the company's generous offer.

Does the pretentious moron make anyone sick yet....

 

[Larry Brasfield]

The subject should be "Fred goes off the deep end"
and would be if not for my disdain for those who
like to put their stupid ad-hominem attacks there.

"Fred Bloggs" <nospam@nospam.com> wrote in message news:423C56B8.4020808@nospam.com...

HEY EVERYONE- READ ANOTHER LARRY BRASFIELD ABOUT HE SHOWED SOMEONE ELSE HOW GREAT HE IS:

Larry Brasfield wrote:

I was interviewed by a fellow once who, noting
the phrase "root locus" in my resume, got a gleam
in his eye and pulled out a special question he had
worked up for such claims. After I ascertained that
he really wanted me to work out the solution, right
there in his office, (while he did other work for 15
minutes or so), I did the work and handed it over
to him. He went immediately to the bottom line
and informed me it was wrong. I acknowledged
that possibility, but invited him to go with me thru
the derivation to find the error, a challenge he took
up readily. After another 30 minutes scrutinizing
each step, getting to the bottom without finding any
identifiable error, he pulled out a little worksheet
that I imagine was his derivation. We found his
error in short order, leading to a reaction that I
considered carefully later. The reaction? A plain
and apparently sincere thank-you, accompanied by
a smile. Needless to say, he was not the reason I
turned down the company's generous offer.

Does the pretentious moron make anyone sick yet....

Yes, he does. I assure you.

--
--Larry Brasfield
email: donotspam_larry_brasfield@hotmail.com
Above views may belong only to me.

 

[Larry Brasfield]

If anybody is willing to help me out here, I would appreciate it.

To begin, and get the issue off the table, I will stipulate
that one motivation behind the below quoted story was
to cast some doubt on certain baseless allegations
regarding my mathematical skills.

But there are several other, ultimately more interesting
virtues apparent there. I thought these were moderately
obvious and relevant in context, (which includes both
John's experience with somebody unlike the interviewer
and numerous recent interactions in this forum between
myself and a surprisingly noisy shadow I've acquired.)

So, enough preface, here are my questions:

Are there clearly evident virtues to be found in that story
other than "Larry does or may know some math"?

(and a harder one Were those virtues given enough
prominence to justify the notion that an inability to see
them represents a lack of familiarity with them? (For
obvious reasons, I will think no less of anybody who
decides not to touch that one.)

(easier Of the people you have done technical work
with, what fraction do you estimate would admire that
interviewer if they had seen the interview as related?

(P.S. to my shadow: The DERF transform will be
carefully and thoroughly applied to all replies.)

"Larry Brasfield" <donotspam_larry_brasfield@hotmail.com> wrote
in message news:AdZ_d.25$te2.421@news.uswest.net...
[comments re subject cut]

"Fred Bloggs" <nospam@nospam.com> wrote in message news:423C56B8.4020808@nospam.com...
[off-point material cut]
Larry Brasfield wrote:

I was interviewed by a fellow once who, noting
the phrase "root locus" in my resume, got a gleam
in his eye and pulled out a special question he had
worked up for such claims. After I ascertained that
he really wanted me to work out the solution, right
there in his office, (while he did other work for 15
minutes or so), I did the work and handed it over
to him. He went immediately to the bottom line
and informed me it was wrong. I acknowledged
that possibility, but invited him to go with me thru
the derivation to find the error, a challenge he took
up readily. After another 30 minutes scrutinizing
each step, getting to the bottom without finding any
identifiable error, he pulled out a little worksheet
that I imagine was his derivation. We found his
error in short order, leading to a reaction that I
considered carefully later. The reaction? A plain
and apparently sincere thank-you, accompanied by
a smile. Needless to say, he was not the reason I
turned down the company's generous offer.

[Fred-dreck and reply cut.]
--
--Larry Brasfield
email: donotspam_larry_brasfield@hotmail.com
Above views may belong only to me.

 

[Fred Bloggs]

Larry Brasfield wrote:
[...snip garbage...]

The only thing for sure is that you are a F-CKING reject. No one is
interested in your defective trash fantasy of a life- we have already
proven that most of your claims to engineering expertise are total
bullshit and lies....

 

[Fred Bloggs]

Larry Brasfield wrote:
[..snip trash...]

Like most worthless trolls, you've got a real smart-ass mouth there- it
is the only thing you have...The only thing for sure is that you are a
F-CKING reject. No one is interested in your defective trash fantasy of
a life- we have already proven that most of your claims to engineering
expertise are total bullshit and lies....

 

[Larry Brasfield]

This has been converted, via a process I will call the DERF transform [1].
This elision process conforms to accepted Usenet quoting practise with
the exception that elided text is replaced by "[DERF]" and, where needed
for grammaticality, short sequences with a '[]' pair are inserted.

[1. Application of a filter removing Dreck, Extraneousness, Redundancy, Foolishness.]

"Fred Bloggs" <nospam@nospam.com> wrote in
message news:423C90F0.5020008@nospam.com...

Larry Brasfield wrote:
[DERF]
we have already proven that most of your claims to engineering expertise
are total bullshit and lies....

That proof is a figment of your imagination only.
With your inability to formulate a rational argument,
your use of the term "proven" is a hoot.

--
--Larry Brasfield
email: donotspam_larry_brasfield@hotmail.com
Above views may belong only to me.