Can PLL Freq Error be zero?

[Erikk]

All PLL chips specify phase noise and application notes talk about how
to measure it but I haven't seen anything that specifies the freq
error. If the reference frequency is 100.0000000MHz and the PLL is
designed to multiply the input frequency by integer 2, is the output
freq 200.0000000MHz with phase noise?

Not really knowing the details, I expected some finite error in the
output frequency, say 1ppm error or 200Hz in this case, which seemed
like a believable number. But then I was wondering, can a PLL be in
lock without input and output edges lined which I think means the freq
error is zero? I know the phase noise will be there. I just don't
understand how the lock happens with even 1ppm freq error.

If the freq error is a fact of life, how can it be reduced in a fixed
frequency PLL application?

 

[John Larkin]

On Mon, 14 Mar 2005 00:10:41 -0500, Erikk <123@abc.com> wrote:

All PLL chips specify phase noise and application notes talk about how
to measure it but I haven't seen anything that specifies the freq
error. If the reference frequency is 100.0000000MHz and the PLL is
designed to multiply the input frequency by integer 2, is the output
freq 200.0000000MHz with phase noise?

Yes.

Not really knowing the details, I expected some finite error in the
output frequency, say 1ppm error or 200Hz in this case, which seemed
like a believable number. But then I was wondering, can a PLL be in
lock without input and output edges lined which I think means the freq
error is zero? I know the phase noise will be there. I just don't
understand how the lock happens with even 1ppm freq error.

If the freq error is a fact of life, how can it be reduced in a fixed
frequency PLL application?

In lock, the frequency error is zero. Two cycles of output for each
cycle of input. It's like a set of gears, one gear with 5 teeth and
the other with 10.

Belts have errors but gears have zero error. Same idea.

John

 

[Terry Given]

Tim Hubberstey wrote:

Terry Given wrote:

John Larkin wrote:

On Mon, 14 Mar 2005 00:10:41 -0500, Erikk <123@abc.com> wrote:


All PLL chips specify phase noise and application notes talk about how
to measure it but I haven't seen anything that specifies the freq
error. If the reference frequency is 100.0000000MHz and the PLL is
designed to multiply the input frequency by integer 2, is the output
freq 200.0000000MHz with phase noise?


Yes.

Not really knowing the details, I expected some finite error in the
output frequency, say 1ppm error or 200Hz in this case, which seemed
like a believable number. But then I was wondering, can a PLL be in
lock without input and output edges lined which I think means the freq
error is zero? I know the phase noise will be there. I just don't
understand how the lock happens with even 1ppm freq error.

If the freq error is a fact of life, how can it be reduced in a fixed
frequency PLL application?


In lock, the frequency error is zero. Two cycles of output for each
cycle of input. It's like a set of gears, one gear with 5 teeth and
the other with 10.
Belts have errors but gears have zero error. Same idea.

John


what about instantaneous error? gears have hysterisis (aka backlash)

(admittedly I'm being pedantic)


Isn't that just the equivalent of the phase noise already allowed for
earlier in the thread? ;-)

pretty much. Like I said, its pure pedanticism, viz.:

#define PLL_hunting phase_noise

IOW define any signal we dont want as "noise".

If the VCO was *perfect* then once the error amp (PD + loop filter) had
settled on the voltage required to give the exact frequency (and phase),
the frequency/phase error would be zero and stay that way forevermore
(assuming the tracked signal is likewise constant, and the error amp
contains an integrator). This needs a perfect EA too. Of course there is
no such thing as a perfect VCO or EA (or anything else, if we look close
enough) so the output F/phi drifts, the error amp wobbles appropriately
and all becomes well again. Said wobbling = phase noise (brutally
abridged description eh wot?)

A shitty PLL will have metric truckloads of phase noise - in the worst
case it will oscillate at its closed-loop bandwidth (a-la nyquist, thats
a whole lotta phase noise). So to build a good PLL, firstly make the
damn thing closed-loop stable. Then try and inject as little shit into
the loop as possible to reduce phase noise (good VCO, stable ref, good
PD, low noise EA etc). I've never built a stupendous PLL (only nice easy
ones), but odds on it gets pretty tricky as the phase noise spec gets
smaller (well duh).

Just like any other control loop, I betcha there are quite a few PLLs in
existence that *do* have nyquist oscillations.

Cheers
Terry

 

[Tim Wescott]

John Larkin wrote:

On Mon, 14 Mar 2005 00:10:41 -0500, Erikk <123@abc.com> wrote:


All PLL chips specify phase noise and application notes talk about how
to measure it but I haven't seen anything that specifies the freq
error. If the reference frequency is 100.0000000MHz and the PLL is
designed to multiply the input frequency by integer 2, is the output
freq 200.0000000MHz with phase noise?



Yes.


Not really knowing the details, I expected some finite error in the
output frequency, say 1ppm error or 200Hz in this case, which seemed
like a believable number. But then I was wondering, can a PLL be in
lock without input and output edges lined which I think means the freq
error is zero? I know the phase noise will be there. I just don't
understand how the lock happens with even 1ppm freq error.

If the freq error is a fact of life, how can it be reduced in a fixed
frequency PLL application?




In lock, the frequency error is zero. Two cycles of output for each
cycle of input. It's like a set of gears, one gear with 5 teeth and
the other with 10.

Belts have errors but gears have zero error. Same idea.

John

Or more precisely, the long-term frequency offset from the reference

will be zero -- otherwise it wouldn't be locked. There can be
short-term frequency offset errors due to the component of the output
phase noise that comes from within the PLL, and both long- and short-
term frequency (or phase, if you'd rather) errors from the reference's
phase noise.

--

Tim Wescott
Wescott Design Services
http://www.wescottdesign.com

 

[budgie]

On Sun, 13 Mar 2005 23:50:59 -0800, Tim Wescott <tim@wescottnospamdesign.com>
wrote:

John Larkin wrote:

On Mon, 14 Mar 2005 00:10:41 -0500, Erikk <123@abc.com> wrote:


All PLL chips specify phase noise and application notes talk about how
to measure it but I haven't seen anything that specifies the freq
error. If the reference frequency is 100.0000000MHz and the PLL is
designed to multiply the input frequency by integer 2, is the output
freq 200.0000000MHz with phase noise?



Yes.


Not really knowing the details, I expected some finite error in the
output frequency, say 1ppm error or 200Hz in this case, which seemed
like a believable number. But then I was wondering, can a PLL be in
lock without input and output edges lined which I think means the freq
error is zero? I know the phase noise will be there. I just don't
understand how the lock happens with even 1ppm freq error.

If the freq error is a fact of life, how can it be reduced in a fixed
frequency PLL application?




In lock, the frequency error is zero. Two cycles of output for each
cycle of input. It's like a set of gears, one gear with 5 teeth and
the other with 10.

Belts have errors but gears have zero error. Same idea.

John

Or more precisely, the long-term frequency offset from the reference
will be zero -- otherwise it wouldn't be locked. There can be
short-term frequency offset errors due to the component of the output
phase noise that comes from within the PLL, and both long- and short-
term frequency (or phase, if you'd rather) errors from the reference's
phase noise.

If it is locked, it won't slip a cycle. Ergo over *any* time interval there
must be less than 1 cycle error - and unless the loop stability is *real-poor*
it would be a lot less. There would really remain only phase variation, which
is a different animal to frequency error.

 

[Genome]

"Erikk" <123@abc.com> wrote in message
news:fm5a31hbdedc9b7u54aqhst80b2bvlo46c@4ax.com...

All PLL chips specify phase noise and application notes talk about how
to measure it but I haven't seen anything that specifies the freq
error. If the reference frequency is 100.0000000MHz and the PLL is
designed to multiply the input frequency by integer 2, is the output
freq 200.0000000MHz with phase noise?

Not really knowing the details, I expected some finite error in the
output frequency, say 1ppm error or 200Hz in this case, which seemed
like a believable number. But then I was wondering, can a PLL be in
lock without input and output edges lined which I think means the freq
error is zero? I know the phase noise will be there. I just don't
understand how the lock happens with even 1ppm freq error.

If the freq error is a fact of life, how can it be reduced in a fixed
frequency PLL application?

FUCK YOU

I'd like to know the effect of the divider on the loop gain. If the VCO
changes its output frequency.... how does that propagate down the divider.

DNA

 

[John Larkin]

On Mon, 14 Mar 2005 20:50:40 +1300, Terry Given <my_name@ieee.org>
wrote:

Just like any other control loop, I betcha there are quite a few PLLs in
existence that *do* have nyquist oscillations.

I've done a few loops that use a d-flipflop as a bang-bang phase
detector, a pure binary early-late detector. Arguably, it seesaws all
the time. The best one (ecl logic, 155.52 MHz) has a measured RMS
jitter in the 2 ps range.

The other extreme is just an xor gate inside an fpga, driving an r-r-c
into the vco input of a crystal oscillator. That works well for narrow
acquisition ranges.

John

 

[John Larkin]

On Mon, 14 Mar 2005 13:53:32 GMT, "Genome" <ilike_spam@yahoo.co.uk>
wrote:

"Erikk" <123@abc.com> wrote in message
news:fm5a31hbdedc9b7u54aqhst80b2bvlo46c@4ax.com...

All PLL chips specify phase noise and application notes talk about how
to measure it but I haven't seen anything that specifies the freq
error. If the reference frequency is 100.0000000MHz and the PLL is
designed to multiply the input frequency by integer 2, is the output
freq 200.0000000MHz with phase noise?

Not really knowing the details, I expected some finite error in the
output frequency, say 1ppm error or 200Hz in this case, which seemed
like a believable number. But then I was wondering, can a PLL be in
lock without input and output edges lined which I think means the freq
error is zero? I know the phase noise will be there. I just don't
understand how the lock happens with even 1ppm freq error.

If the freq error is a fact of life, how can it be reduced in a fixed
frequency PLL application?



FUCK YOU

I'd like to know the effect of the divider on the loop gain. If the VCO
changes its output frequency.... how does that propagate down the divider.

DNA

Easy. Given an Umpteen mhz vco with a Whatever vco constant in
mhz/volt, and a Somethingorother divider in the loop, just black-box
replace that whole mess with a readily available Radio Shack vco
having

U' = U / S

not to mention

W' = W / S

and go about your business. These aren't the droids we want.

John

 

[Larry Brasfield]

"John Larkin" <jjSNIPlarkin@highTHISlandPLEASEtechnology.XXX> wrote
in message news:a0eb31pvev0v6j2fusssfklrei8o94koot@4ax.com...

On Mon, 14 Mar 2005 20:50:40 +1300, Terry Given <my_name@ieee.org
wrote:

Just like any other control loop, I betcha there are quite a few PLLs in
existence that *do* have nyquist oscillations.

What is a nyquist oscillation? Can there
be more than one in the same loop?

I've done a few loops that use a d-flipflop as a bang-bang phase
detector, a pure binary early-late detector. Arguably, it seesaws all
the time. The best one (ecl logic, 155.52 MHz) has a measured RMS
jitter in the 2 ps range.

I'm not sure what circuit you are talking about,
but the ones I have seen using DFFs have a
more or less proportional output, (neglecting
the offset term), and are normally operated in
proportional feedback loops so they need not
hunt, seesaw, bang-bang or otherwise thrash
around in a non-random manner.

The MC12040 and similar so-called "phase
frequency detectors" (which actually employ a
pair of set/reset flip-flops) do have a small
dead zone and tend to hunt a little bit when
used in circuits taken from the app notes,
but they can be made to stablize outside of
that dead zone with a little applied bias.

The other extreme is just an xor gate inside an fpga, driving an r-r-c
into the vco input of a crystal oscillator. That works well for narrow
acquisition ranges.

Yes, but it can be a PITA to get the VCO
initially close enough to allow lock when
there is no frequency detection. All the
harder with a narrowband loop filter.

--
--Larry Brasfield
email: donotspam_larry_brasfield@hotmail.com
Above views may belong only to me.

 

[Tim Wescott]

bill.sloman@ieee.org wrote:

Erikk wrote:

All PLL chips specify phase noise and application notes talk about

how

to measure it but I haven't seen anything that specifies the freq
error. If the reference frequency is 100.0000000MHz and the PLL is
designed to multiply the input frequency by integer 2, is the output
freq 200.0000000MHz with phase noise?

Not really knowing the details, I expected some finite error in the
output frequency, say 1ppm error or 200Hz in this case, which seemed
like a believable number. But then I was wondering, can a PLL be in
lock without input and output edges lined which I think means the

freq

error is zero? I know the phase noise will be there. I just don't
understand how the lock happens with even 1ppm freq error.

If the freq error is a fact of life, how can it be reduced in a fixed
frequency PLL application?


You need to get a decent textbook on phase locked loops. I use Floyd M.
Gardner's "Phaselock Techniques" ISBN 0-471-04294-3 but it was
published in 1979.

Gardner makes the point that second order phase-locked loops (the sort
used in most practical applications) integrate the phase error to zero,
so that there is no finite error in output frequency, unless you get
cycle slipping, which ought to be rare to non-existent with a
reasonably clean input signal.

He backs up this proposition with extensive references to the then
published literature on the subject. A more recent textbook will
probably have lots more scholarly publications to refer to.

Actually even a 1st-order loop will give you zero frequency error, at

the expense of having some fixed phase error to provide the DC voltage
to pull the VCO. A 2nd-order (more correctly a type II) loop gives you
zero phase error as well, as you've pointed out.

--

Tim Wescott
Wescott Design Services
http://www.wescottdesign.com

 

[John Larkin]

On Mon, 14 Mar 2005 08:45:44 -0800, "Larry Brasfield"
<donotspam_larry_brasfield@hotmail.com> wrote:

I've done a few loops that use a d-flipflop as a bang-bang phase
detector, a pure binary early-late detector. Arguably, it seesaws all
the time. The best one (ecl logic, 155.52 MHz) has a measured RMS
jitter in the 2 ps range.

I'm not sure what circuit you are talking about,

A single D flipflop!

John

 

[Larry Brasfield]

"John Larkin" <jjlarkin@highSNIPlandTHIStechPLEASEnology.com>
wrote in message news:vmpb31hu67cjdo9f6ciigt45dhhlngdcdd@4ax.com...

On Mon, 14 Mar 2005 08:45:44 -0800, "Larry Brasfield"
donotspam_larry_brasfield@hotmail.com> wrote:

I've done a few loops that use a d-flipflop as a bang-bang phase
detector, a pure binary early-late detector. Arguably, it seesaws all
the time. The best one (ecl logic, 155.52 MHz) has a measured RMS
jitter in the 2 ps range.

I'm not sure what circuit you are talking about,

A single D flipflop!

Well, I suspected that much. But since that
circuit is not a bang-bang phase detector
any more than any other phase detector
that responds only to edges, I wondered
if the bang-bang in question was the kind
that arises with the more complex detector.

I suppose that if the seesaw you mention
is the carrier frequency output of that phase
detector, and that has not been filtered out
to an unarguably negligible degree, and if
the PLL harmonic output is considered
rather the fundamental, I would agree with
your "Arguably seesaws" statement. But
somehow I doubted that was your meaning
and so I was puzzled as to what you meant.

--
--Larry Brasfield
email: donotspam_larry_brasfield@hotmail.com
Above views may belong only to me.

 

[John Larkin]

On Mon, 14 Mar 2005 11:40:25 -0800, "Larry Brasfield"
<donotspam_larry_brasfield@hotmail.com> wrote:

"John Larkin" <jjlarkin@highSNIPlandTHIStechPLEASEnology.com
wrote in message news:vmpb31hu67cjdo9f6ciigt45dhhlngdcdd@4ax.com...
On Mon, 14 Mar 2005 08:45:44 -0800, "Larry Brasfield"
donotspam_larry_brasfield@hotmail.com> wrote:

I've done a few loops that use a d-flipflop as a bang-bang phase
detector, a pure binary early-late detector. Arguably, it seesaws all
the time. The best one (ecl logic, 155.52 MHz) has a measured RMS
jitter in the 2 ps range.

I'm not sure what circuit you are talking about,

A single D flipflop!


Well, I suspected that much. But since that
circuit is not a bang-bang phase detector
any more than any other phase detector
that responds only to edges, I wondered
if the bang-bang in question was the kind
that arises with the more complex detector.

This detector applies one signal to the D input and the other to the
clock. I like to assign the incoming data stream to clock, and the
local vco to D. The q/qbar pair is the differential output into the
loop filter.

Well, every clock, the classic charge-pump pd outputs a hunk of charge
that's proportional to the time difference between the reference and
the input, so has a clearly definable Kvco slope. The d-flop outputs
only a 1 or a 0 every time it operates, so the Kvco is infinite. So
it's clearly more bang-bangy than the charge pump or an xor.

I suppose that if the seesaw you mention
is the carrier frequency output of that phase
detector, and that has not been filtered out
to an unarguably negligible degree, and if
the PLL harmonic output is considered
rather the fundamental, I would agree with
your "Arguably seesaws" statement. But
somehow I doubted that was your meaning
and so I was puzzled as to what you meant.

In the ideal noiseless case, the flipflop alternates between 1 and 0
every time it's clocked, as the loop hunts delicately about the
early/late boundary. In real life, noise and jitter add to the fun.

John

 

[Terry Given]

Larry Brasfield wrote:

"John Larkin" <jjSNIPlarkin@highTHISlandPLEASEtechnology.XXX> wrote
in message news:a0eb31pvev0v6j2fusssfklrei8o94koot@4ax.com...

On Mon, 14 Mar 2005 20:50:40 +1300, Terry Given <my_name@ieee.org
wrote:

Just like any other control loop, I betcha there are quite a few PLLs in
existence that *do* have nyquist oscillations.


What is a nyquist oscillation? Can there
be more than one in the same loop?

OK, closed-loop instability. whose criteria? depends how many times you
want to spin around -1 if you like drawing Nyquist plots. Or take the
easy way out and draw a Bode plot

More than one? yeah, sure, all it takes is more unstable poles (I think
- I haven't actually proved it though).

Hell, its probably not that hard to build a chaotic PLL that does some
really crazy stuff.

[snip]

Cheers
Terry

 

[Larry Brasfield]

"Terry Given" <my_name@ieee.org> wrote in message
news:cEmZd.9584$1S4.1017944@news.xtra.co.nz...

Larry Brasfield wrote:
"John Larkin" <jjSNIPlarkin@highTHISlandPLEASEtechnology.XXX> wrote
in message news:a0eb31pvev0v6j2fusssfklrei8o94koot@4ax.com...

On Mon, 14 Mar 2005 20:50:40 +1300, Terry Given <my_name@ieee.org
wrote:

Just like any other control loop, I betcha there are quite a few PLLs in
existence that *do* have nyquist oscillations.

What is a nyquist oscillation? Can there
be more than one in the same loop?

OK, closed-loop instability. whose criteria? depends how many times you want to spin around -1 if you like drawing Nyquist plots.
Or take the easy way out and draw a Bode plot

Shucks. I was hoping that there was some new
(to me) kind of oscillation to learn about. You
are referring to a (too) common problem by an
uncommon name. (So says Google.)

I wonder if Mr. Nyquist, who devised a readily
applied criterion for evaluating stablity, presumably
to help people achieve said condition, would like
to have a misbehavior named after him that is most
often caused by not applying his method.

More than one? yeah, sure, all it takes is more unstable poles (I think - I haven't actually proved it though).

I've seen no circuits that I remember exhibiting
more than one oscillation involving the same loop.
They have a way of electing a winner among all
the modes that are contenders.

Hell, its probably not that hard to build a chaotic PLL that does some really crazy stuff.

I can assure you that it is easy. The newer
frequency detector types make it even easier.

--
--Larry Brasfield
email: donotspam_larry_brasfield@hotmail.com
Above views may belong only to me.

 

[Terry Given]

Larry Brasfield wrote:

"Terry Given" <my_name@ieee.org> wrote in message
news:cEmZd.9584$1S4.1017944@news.xtra.co.nz...

Larry Brasfield wrote:

"John Larkin" <jjSNIPlarkin@highTHISlandPLEASEtechnology.XXX> wrote
in message news:a0eb31pvev0v6j2fusssfklrei8o94koot@4ax.com...


On Mon, 14 Mar 2005 20:50:40 +1300, Terry Given <my_name@ieee.org
wrote:


Just like any other control loop, I betcha there are quite a few PLLs in
existence that *do* have nyquist oscillations.

What is a nyquist oscillation? Can there
be more than one in the same loop?

OK, closed-loop instability. whose criteria? depends how many times you want to spin around -1 if you like drawing Nyquist plots.
Or take the easy way out and draw a Bode plot


Shucks. I was hoping that there was some new
(to me) kind of oscillation to learn about. You
are referring to a (too) common problem by an
uncommon name. (So says Google.)

just me, being cryptic :}

Google looks like a great way to ensure (*NOT* Insure. Aargh, that
particular mangling of English drives me bonkers /rant) conformity (aka
mediocrity).

I wonder if Mr. Nyquist, who devised a readily
applied criterion for evaluating stablity, presumably
to help people achieve said condition, would like
to have a misbehavior named after him that is most
often caused by not applying his method.

I think it would take a Ouija board to find out

But I *have* seen the term "Nyquist oscillation" used to describe
closed-loop instabilities. just not frequently (har har).

More than one? yeah, sure, all it takes is more unstable poles (I think - I haven't actually proved it though).


I've seen no circuits that I remember exhibiting
more than one oscillation involving the same loop.
They have a way of electing a winner among all
the modes that are contenders.

Its actually a pretty good question. I'll put my maths hat on, and do
some thinking. For example can a pair of not-too-closely spaced unstable
poles cause oscillation at the beat frequency?

Hell, its probably not that hard to build a chaotic PLL that does some really crazy stuff.


I can assure you that it is easy. The newer
frequency detector types make it even easier.

That doesnt surprise me (nothing ever works), but please do elaborate

Regards,
Terry

 

[Larry Brasfield]

"Terry Given" <my_name@ieee.org> wrote in message
news:vhoZd.9618$1S4.1024599@news.xtra.co.nz...

Larry Brasfield wrote:
"Terry Given" <my_name@ieee.org> wrote in message
news:cEmZd.9584$1S4.1017944@news.xtra.co.nz...
....
I wonder if Mr. Nyquist, who devised a readily
applied criterion for evaluating stablity, presumably
to help people achieve said condition, would like
to have a misbehavior named after him that is most
often caused by not applying his method.

I think it would take a Ouija board to find out

Well, it was just a thought experiment.

But I *have* seen the term "Nyquist oscillation" used to describe closed-loop instabilities. just not frequently (har har).

That wouldn't have been here, would it? (There
would be a <g> here if I thought you were touchy.)

I've seen no circuits that I remember exhibiting
more than one oscillation involving the same loop.
They have a way of electing a winner among all
the modes that are contenders.

Its actually a pretty good question. I'll put my maths hat on, and do some thinking. For example can a pair of not-too-closely
spaced
unstable poles cause oscillation at the beat frequency?

If there was a way for two oscillations to barely occur,
such that they could softly "limit" (meaning reach an
effective unity loop gain), then maybe the two modes
of oscillation could coexist. I would expect, even then,
that they would mode lock via the non-linearity under
most circumstances unless they had high Q. Since
these conditions are unlikely, I am not surprised to
have never observed such a phenomenon.

Hell, its probably not that hard to build a chaotic PLL that does some really crazy stuff.

I can assure you that it is easy. The newer
frequency detector types make it even easier.

That doesnt surprise me (nothing ever works), but please do elaborate

The few chaotic PAL's [1] I have faced were
taxing in the comprehension department, so I
should beg off of this. But here is what I have
seen with a PLL using a predecessor of the
OnSemi frequency-phase detector. This was
a type II loop (counting the frequency to phase
conversion as one integrator).

[1. A PAL is a phase affected loop, meant to be
a phase locked loop but not actually locked. ]

All is fine when the VCO frequency is way off
the (hoped for) lock frequency. The frequency
detector drives the loop closer to where it might
lock. (Ha!) Then the phase detector begins to
work, but, (due to inadequate forseeing, I admit),
the (explicit) integrator takes a little longer to be
turned around than it should because of error
built up elsewhere. The result is an overshoot
thru the phase lock range, but with an impetus
that varies according to what phases existed
as that range was approached from the other
side. After the frequency detector gets the
VCO back to the point after the "HA", the
cycle repeats, if "repeat" can be meaningfully
applied to something that seems to never do
quite the same thing twice.

I'm not saying this is inevitable, and careful
attention to where limiting occurs can likely
preclude such problems. But they are easy
to court when one is young and eager.

A PLL without a frequency detector can get
interesting too, near the limits of its capture
range, but my memory fails me as to how.

Regards,

Happier day!
--
--Larry Brasfield
email: donotspam_larry_brasfield@hotmail.com
Above views may belong only to me.

 

[John Larkin]

On Mon, 14 Mar 2005 15:33:32 -0800, "Larry Brasfield"
<donotspam_larry_brasfield@hotmail.com> wrote:

If there was a way for two oscillations to barely occur,
such that they could softly "limit" (meaning reach an
effective unity loop gain), then maybe the two modes
of oscillation could coexist. I would expect, even then,
that they would mode lock via the non-linearity under
most circumstances unless they had high Q. Since
these conditions are unlikely, I am not surprised to
have never observed such a phenomenon.

It's not unheard of to have a low frequency oscillation with "squeggs"
of higher-frequency stuff on the rising and falling edges. The hf
oscillations are opportunistic infections that live in the linear slew
regions of the slower instability; they tend to die out at the extreme
swings when the lf oscillation saturates the system. But in a complex
system, multiple loops can oscillate locally.

John

 

[Larry Brasfield]

"John Larkin" <jjlarkin@highSNIPlandTHIStechPLEASEnology.com>
wrote in message news:gs9c311338tg2npaemsjetc6d79ipefdt9@4ax.com...

On Mon, 14 Mar 2005 15:33:32 -0800, "Larry Brasfield"
donotspam_larry_brasfield@hotmail.com> wrote:

If there was a way for two oscillations to barely occur,
such that they could softly "limit" (meaning reach an
effective unity loop gain), then maybe the two modes
of oscillation could coexist. I would expect, even then,
that they would mode lock via the non-linearity under
most circumstances unless they had high Q. Since
these conditions are unlikely, I am not surprised to
have never observed such a phenomenon.

It's not unheard of to have a low frequency oscillation with "squeggs"
of higher-frequency stuff on the rising and falling edges.

Yes, although that stretches the idea of "coexist" a bit.

The hf
oscillations are opportunistic infections that live in the linear slew
regions of the slower instability; they tend to die out at the extreme
swings when the lf oscillation saturates the system.

Sometimes the way that such parasitic oscillations
become manifest (when one does not have the
equipment to detect them more directly) is that
there are distortion products that should not be
present according to the device nonlinearities.

But in a complex
system, multiple loops can oscillate locally.

Of course. I suspect Murphy's law would be
compromised if that were not so. Earlier, I tried
to exclude those cases by saying: "more than one
oscillation involving the same loop".

--
--Larry Brasfield
email: donotspam_larry_brasfield@hotmail.com
Above views may belong only to me.

 

[John Larkin]

On Mon, 14 Mar 2005 16:27:20 -0800, "Larry Brasfield"
<donotspam_larry_brasfield@hotmail.com> wrote:

Of course. I suspect Murphy's law would be
compromised if that were not so. Earlier, I tried
to exclude those cases by saying: "more than one
oscillation involving the same loop".

Oh, I'm reminded of the original TouchTone telephones. The DTMF tone
pairs were generated by a mess of pot cores, capacitors, switches, and
a *single* germanium transistor. The transistor presented a negative
resistance to two series-connected LC tanks. There was a varistor
across each LC, so each limited its own swing and neither got the
upper hand. Clever.

John