Can I include include a constant in a constant array?

[Fredxx]

Example

type word_type is array (0 to 1) of std_logic_vector(7 downto 0);
constant height : word_type := (x"04", x"05");

and I would like to place this constant in

type Con_Array_type is array (0 to size - 1) of std_logic_vector(7 downto
0);
constant Con_Array : Con_Array_type := (
x"00", x"01",
x"02", x"03",
height[1], height[0],
x"06", x"07"
);

Is this possible? If so where am I going wrong?

 

[Jonathan Bromley]

On Tue, 14 Jul 2009 16:15:56 +0100, "Fredxx" <fredxx@spam.com> wrote:

type word_type is array (0 to 1) of std_logic_vector(7 downto 0);
constant height : word_type := (x"04", x"05");

and I would like to place this constant in

type Con_Array_type is array (0 to size - 1) of std_logic_vector(7 downto
0);
constant Con_Array : Con_Array_type := (
x"00", x"01",
x"02", x"03",
height[1], height[0],
x"06", x"07"
);

Is this possible?

I think so.

If so where am I going wrong?

Square brackets for VHDL array subscripts?

What kind of error message do you get?
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

[Fredxx]

"Jonathan Bromley" <jonathan.bromley@MYCOMPANY.com> wrote in message
news:a78p55p35l0p7po6pbs5v74jln5jruktgt@4ax.com...

On Tue, 14 Jul 2009 16:15:56 +0100, "Fredxx" <fredxx@spam.com> wrote:

type word_type is array (0 to 1) of std_logic_vector(7 downto 0);
constant height : word_type := (x"04", x"05");

and I would like to place this constant in

type Con_Array_type is array (0 to size - 1) of std_logic_vector(7 downto
0);
constant Con_Array : Con_Array_type := (
x"00", x"01",
x"02", x"03",
height[1], height[0],
x"06", x"07"
);

Is this possible?

I think so.

If so where am I going wrong?

Square brackets for VHDL array subscripts?

What kind of error message do you get?
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

<feeling_embarrassed>
Thank you very kindly for your prompt reply. It was indeed the square
brackets as I was porting some code from "C"!!!
Now all working.
</feeling_embarrassed>

 

[Mark McDougall]

Fredxx wrote:

feeling_embarrassed
Thank you very kindly for your prompt reply. It was indeed the square
brackets as I was porting some code from "C"!!!
Now all working.
/feeling_embarrassed

LOL!

Wait 'til you're debugging a mixed-language design, with VHDL and Verilog,
which includes a soft-core processor running C-code! You get some
interesting syntax errors there!

Regards,

--
Mark McDougall, Engineer
Virtual Logic Pty Ltd, <http://www.vl.com.au>
21-25 King St, Rockdale, 2216
Ph: +612-9599-3255 Fax: +612-9599-3266

 

[Martin Thompson]

Mark McDougall <markm@vl.com.au> writes:

Fredxx wrote:

feeling_embarrassed
Thank you very kindly for your prompt reply. It was indeed the square
brackets as I was porting some code from "C"!!!
Now all working.
/feeling_embarrassed

LOL!

Wait 'til you're debugging a mixed-language design, with VHDL and Verilog,
which includes a soft-core processor running C-code! You get some
interesting syntax errors there!

Then try and compare your results with the Matlab simulation indexing
from 1 rather than 0 as well for yet more debugging fun

Cheers,
Martin

--
martin.j.thompson@trw.com
TRW Conekt - Consultancy in Engineering, Knowledge and Technology
http://www.conekt.net/electronics.html