Brain Cramps...

[rickman]

On Dec 1, 12:20 pm, Jan Decaluwe <j...@jandecaluwe.com> wrote:

rickman wrote:

Yes, if "only full word match" is used, then "write_n" won't match a
"write" search and replace so only "write" will change.

It seems that you do not appreciate the difference between Rename
and global search and replace yet.

The same identifier may refer to a lot of different objects in
a design. Rename is based on object identify, not identifier identity.
This makes it intelligent and safe.

Oh? How does that work. When can you use the same name for different
objects??? Why would you if you can?

1 minute screencast on Rename (no sound as yet):

   http://www.sigasi.com/screencast/rename

And those completions include both keywords as well as your signal/
variable names?  If this feature works well enough I might consider
Sigasi.  Especially if it could be used for other languages than just
VHDL.  Is the VHDL aspect hard coded?  I expect it will also support
Verilog, but what about generic languages?  Does it have a means of
setting it up for an arbitrary language like CW does?

Sigasi HDT is available as a plugin to a standard Eclipse installation,
which means that it plays well with thousands of open-source and
commercial plugins from other parties. More info:

I don't use eclipse or any plugins of that nature.

   http://www.sigasi.com/download

Sigasi HDT itself has no Verilog support yet.

There is a definite strike against it. I had planned to spend some
time this year learning Verilog at least well enough to figure out if
I wanted to make it my primary HDL. It seems very limiting to use a
tool that works great for only one language.

Rick

 

[Thomas Entner]

The features of this editor sound great! (Althought rickman
persistently denies the usefulness of the refactoring-feature ;-)
Especially the integrated error-checking would be a big help (for some
reason, I have a feeled 20x more typos in the same amount of code when
writing VHDL compared to e.g. C).

In the moment I use mainly the editors from the vendors-IDEs, simply
because they are well integrated regarding double-clicking on errors,
etc., althought the editors themself, with minor differences between
the vendors, quite primitive.

The only thing that is not attractive is the price (also considering
that it appears to be heavily based on Eclipse, an open-source-
software). Maybe you can find a license-model with about a 10th of the
pricing (EUR 150,- perpetual + EUR 20,- maintainance), maybe with the
restriction to FPGA-use only, or small companies/private use, or
something... I think this would make it more attractive to many users.

Thomas

www.entner-electronics.com

 

[glen herrmannsfeldt]

Thomas Entner <thomas.entner@entner-electronics.com> wrote:

The features of this editor sound great! (Althought rickman
persistently denies the usefulness of the refactoring-feature ;-)
Especially the integrated error-checking would be a big help (for some
reason, I have a feeled 20x more typos in the same amount of code when
writing VHDL compared to e.g. C).

Maybe you would like verilog better. Before I learned verilog,
I was told that C programmers usually liked verilog better
than VHDL. I can usually read VHDL, but won't claim to be
able to write it. I have even translated some VHDL routines
to verilog. (Not trying to start a verilog vs. VHDL argument,
just suggesting that you might like it.)

-- glen

 

[Martin Thompson]

rickman <gnuarm@gmail.com> writes:

On Dec 1, 8:29 am, Martin Thompson <martin.j.thomp...@trw.com> wrote:
rickman <gnu...@gmail.com> writes:
On Nov 30, 8:18 am, Martin Thompson <martin.j.thomp...@trw.com> wrote:

This is better than a global (ie multi-file) replace because when you
change "write" on one entity to "write_n" you don't want every entity
with a "write" pin changing! And heaven help you changing rd to wr -
hope the characters 'rd' don't appear in any other pins anywhere else
(like the "one_third" pin of your "divide_by_three" entity

That's not a big deal.  My editor, and I suspect many others, has a
check box on the search that says "only full word match" so that
write_n won't match a write search.

No, my point was if you have "write" on another entity you don;t want
that one changing as well.

Yes, if "only full word match" is used, then "write_n" won't match a
"write" search and replace so only "write" will change.

Here's a concrete example (to try and make the point I keep failing to
say clearly in a single sentence, sorry about that!):

I have a FIFO with a write pin on it, and a memory with a write pin
on it.

If I decide to change the FIFO to have an active low write, then I
rename the pin write_n.

I've instantiated the FIFO and the memory a dozen times each in my
large project.

If I do a global replace of "write" with "write_n" in the entire
project, all the references on the memory block will also change. If
I do an interactive global replace, I have to be really careful to get
it all right. Now, admittedly it's likely the compiler will catch it,
but I'll waste time sorting it all out.

Sigasi just does it all for me.

<snip>

I'm not inclined to spend a kilobuck on something that will give me
a minor improvement in what I do maybe 10% of the time.  Then on top
of it all, a tool that requires support from a company is already a
rung lower on the ladder

Sorry, which ladder are you talking about?

Sorry, the evaluation of the tool ladder. I don't know how this tool
is licensed, but I am very down on commercial tools because of the
licensing issues and the seeming lack of support. That automatically
puts a commercial tool below any open source tool when I am evaluating
them. So the commercial tool has to be significantly better for me to
want it.

There's another aspect of the licensing which I forgot to mention -
it's based around Eclipse, which is an open-source IDE which supports
Java and C well out of the box (dunno about Forth - as a
replacement for CW on it's own Eclipse isn't bad (and if you end up
using Xilinx or Altera soft processors, their IDE is also
Eclipse-based). So the investment in Eclipse might be worth it
irrespective of Sigasi... [I still haven't quite made up my mind
whether to switch from Emacs to Eclipse for C-coding. It doesn't have
a Usenet reader like Gnus though, so I'll have to keep Emacs around
for a bit yet!]

Is this the way it works in Sigasi with signal names?  If you are
typing a signal name as the first thing on a line, does it add the
assignment operator?  What happens the first time you type an
assignment to a signal or variable?  Does it add a declaration for the
name?

IIRC you start typing the first few chars and hit ctrl-space, and it
gives you a drop-down of potential completions.

And those completions include both keywords as well as your signal/
variable names?

I think so yes (it's been a while since my eval)

If this feature works well enough I might consider
Sigasi. Especially if it could be used for other languages than just
VHDL. Is the VHDL aspect hard coded? I expect it will also support
Verilog, but what about generic languages? Does it have a means of
setting it up for an arbitrary language like CW does?

Raw Eclipse deals with other languages, not Verilog though.
Completion works in C, for example, and the "go to declaration" type things.

Some Other things it does (full list is athttp://www.sigasi.com/featurelist):
* Autocomplete templates for "if", "process", and the rest.
Nice, but not a big deal, for me anyway.

Ahh, I'd thought you'd said automating boilerplate code was on your
list - sorry.

It is, but I guess I'm saying this is not a big enough feature to move
to a new tool for. I may have some down time in the new year. Maybe
I'll give the Sigasi tool a try. You are starting to convince me.
But learning curves are a PITA and if I have to pay for the tool, the
curve has to be short and the reward has to be big!

It's another little thing that adds up

* Line alignment (so all your : and <= and => line up nicely)
That would be nice.

Much more than "nice" to me - esp. if others see your code - nothing
like bad formatting to make people wonder whether the logic is
similarly wiggly!

Line indentation is a bigger hassle for me. I can line up the <=
and : parts without too much trouble. But I have to admit if you
bring a number of these little features together it might be worth
something.

I *can* line them up by hand, but I very rarely did in the old days,
and my code looked a mess! Nowadays, I hit Ctrl-C, Ctrl-B fairly
frequently to "beautify my buffer" (as Emacs terms it) as I code.

I'll be finished with my VHDL coding in another week or two and won't
want to spend time with a VHDL tool.  I am going to look into a design
using a multiprocessor chip that is micro power or nano power or pico
power, what ever it is being called these days.  Idle state is 100
micro watts per processor with 144 processors on the chip.  Running
full out they use 4.5 mW at over 500 MIPS!  

Sounds fun - that sounds like a greenarray?

Give the man a cupie doll!

Erm, thanks

In the Spring they will have a 144 processor part with five ADC and
DAC and have released a data sheet for the GA4 (4 processors) with
no device release date. But Chuck's blog indicates they have had
prototype GA4 and GA32 devices for some time. On the other hand,
Chuck's blog seems to show a company that is on the low end of
struggling. I have no idea if they will manage to stay solvent long
enough to ship product.

Yes, it looks very interesting.

I am considering designing a Radio Controlled Clock using a GA4 which
would run off of two AAA cells for over a year. That should be a good
demo of the low power capabilities, no? Would that make you believe
that the chip can be pretty low power? The interesting part is that
this can be done with the GA144 nearly as easily as the GA4, you just
pay more to have 143 processors sitting idle 100% of the time and 1
processor idle 95% of the time.

Or you could split the job up and have all 144 of them sitting idle
for 99.9% of the time

Cheers,
Martin

--
martin.j.thompson@trw.com
TRW Conekt - Consultancy in Engineering, Knowledge and Technology
http://www.conekt.co.uk/capabilities/39-electronic-hardware

 

[Martin Thompson]

Thomas Entner <thomas.entner@entner-electronics.com> writes:

The features of this editor sound great! (Althought rickman
persistently denies the usefulness of the refactoring-feature ;-)
Especially the integrated error-checking would be a big help (for some
reason, I have a feeled 20x more typos in the same amount of code when
writing VHDL compared to e.g. C).

Likely because there's 20x as many characters to type in VHDL

<ducks>

Martin

--
martin.j.thompson@trw.com
TRW Conekt - Consultancy in Engineering, Knowledge and Technology
http://www.conekt.co.uk/capabilities/39-electronic-hardware

 

[Martin Thompson]

rickman <gnuarm@gmail.com> writes:

There is a definite strike against it. I had planned to spend some
time this year learning Verilog at least well enough to figure out if
I wanted to make it my primary HDL. It seems very limiting to use a
tool that works great for only one language.

Eclipse verilog plugin - no idea how good it is!

http://sourceforge.net/projects/veditor/

Cheers,
Martin

--
martin.j.thompson@trw.com
TRW Conekt - Consultancy in Engineering, Knowledge and Technology
http://www.conekt.co.uk/capabilities/39-electronic-hardware

 

[David Brown]

On 01/12/2010 19:36, rickman wrote:

On Dec 1, 12:20 pm, Jan Decaluwe<j...@jandecaluwe.com> wrote:
rickman wrote:

Yes, if "only full word match" is used, then "write_n" won't match a
"write" search and replace so only "write" will change.

It seems that you do not appreciate the difference between Rename
and global search and replace yet.

The same identifier may refer to a lot of different objects in
a design. Rename is based on object identify, not identifier identity.
This makes it intelligent and safe.

Oh? How does that work. When can you use the same name for different
objects??? Why would you if you can?

I think the key to understanding here is that "search and replace" is a
purely textual function, while "rename" is a type of "refactoring". I
have no experience with this in VHDL, but I have used it a bit with C
programming (again using Eclipse).

The point here is that Eclipse and the plugin (CDT for C or C++, Sigasi
for VHDL) analyses the syntax of the code - it effectively has the
front-end of a compiler for the language in question. It is not just a
matter of syntax highlighting based on regular expressions, as used by
most editors. It knows the difference between an entity called "write",
a signal called "write" and a function called "write" - because, like a
VHDL compiler, it knows the difference between these concepts.

Assuming Sigasi has similar functions to CDT, this will also allow fast
cross-linking of information between files. With CDT, you can hold your
mouse over an identifier and a tooltip will show you a short definition
of the identifier. You can navigate quickly to the definition of the
identifier, or to other uses of it.

Whether or not you find this sort of thing useful is up to you.
Personally, I am using Eclipse more and more for C programming, though I
still like a simpler and faster text editor for many other tasks.

There are other editors that can do a certain amount of refactoring, or
support the use of "tag" information for cross-navigation by identifier,
but I don't think anything else has the support Eclipse provides.
That's why a company like Sigasi has built a plugin for Eclipse -
Eclipse gives them a solid base for the refactoring, and they only need
to worry about the VHDL-specific part. It's also why - like it or not -
steadily more tool vendors are dropping their IDE's and editors and
moving to an Eclipse + plugin model.

 

[Jan Decaluwe]

rickman wrote:

On Dec 1, 12:20 pm, Jan Decaluwe <j...@jandecaluwe.com> wrote:
rickman wrote:

Yes, if "only full word match" is used, then "write_n" won't match a
"write" search and replace so only "write" will change.
It seems that you do not appreciate the difference between Rename
and global search and replace yet.

The same identifier may refer to a lot of different objects in
a design. Rename is based on object identify, not identifier identity.
This makes it intelligent and safe.

Oh? How does that work. When can you use the same name for different
objects???

Same name for a port on a different entity or component.
Same name for a formal argument of different functions.
Same name for a formal and an actual in a named association.
Same name that occurs in a comment string explanation.

Of course, I'm sure this is all obvious to you and I realize that
it must have been my explanation that was inadequate. But there
really was no need for this confusion. You could have seen all
these things for yourself by just spending one minute to see
the screencast. Sigh.

Why would you if you can?

Because that's what we expect from an HDL, or any programming
language for that matter. Without it, no namespaces, no parametrization,
no hierarchy, no reuse.

Jan

--
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Python as a HDL: http://www.myhdl.org
VHDL development, the modern way: http://www.sigasi.com
Analog design automation: http://www.mephisto-da.com
World-class digital design: http://www.easics.com

 

[rickman]

On Dec 2, 5:14 am, David Brown <da...@westcontrol.removethisbit.com>
wrote:

On 01/12/2010 19:36, rickman wrote:

On Dec 1, 12:20 pm, Jan Decaluwe<j...@jandecaluwe.com> wrote:
rickman wrote:

Yes, if "only full word match" is used, then "write_n" won't match a
"write" search and replace so only "write" will change.

It seems that you do not appreciate the difference between Rename
and global search and replace yet.

The same identifier may refer to a lot of different objects in
a design. Rename is based on object identify, not identifier identity.
This makes it intelligent and safe.

Oh? How does that work. When can you use the same name for different
objects??? Why would you if you can?

I think the key to understanding here is that "search and replace" is a
purely textual function, while "rename" is a type of "refactoring". I
have no experience with this in VHDL, but I have used it a bit with C
programming (again using Eclipse).

Calling it "refactoring" doesn't really help me understand what you
are saying.

The point here is that Eclipse and the plugin (CDT for C or C++, Sigasi
for VHDL) analyses the syntax of the code - it effectively has the
front-end of a compiler for the language in question. It is not just a
matter of syntax highlighting based on regular expressions, as used by
most editors. It knows the difference between an entity called "write",
a signal called "write" and a function called "write" - because, like a
VHDL compiler, it knows the difference between these concepts.

So you are saying that this tool will allow me to use the same name
for an entity that I use for a signal and not get them confused when I
change one of their names. I find that very unimportant. I never use
the same names on entities that I use for signals and I'm not sure you
can even do that in VHDL.

I don't really care what the tools "know" and don't "know". I care
about what that does for me. In this case it sounds like it does
little that I would find interesting. I will say that if this stuff
can be made to work in real time with reasonable error indications
that are effective without being intrusive, then maybe it would be
worthwhile. But there are the other issues to consider of it being a
commercial product, support, cost and inflexibility of licensing.

Assuming Sigasi has similar functions to CDT, this will also allow fast
cross-linking of information between files. With CDT, you can hold your
mouse over an identifier and a tooltip will show you a short definition
of the identifier. You can navigate quickly to the definition of the
identifier, or to other uses of it.

I do that pretty easily now for signals and variables. They are
always declared in the same file. But this may be something that I
would need to see in action to appreciate.

Whether or not you find this sort of thing useful is up to you.
Personally, I am using Eclipse more and more for C programming, though I
still like a simpler and faster text editor for many other tasks.

There are other editors that can do a certain amount of refactoring, or
support the use of "tag" information for cross-navigation by identifier,
but I don't think anything else has the support Eclipse provides.
That's why a company like Sigasi has built a plugin for Eclipse -
Eclipse gives them a solid base for the refactoring, and they only need
to worry about the VHDL-specific part. It's also why - like it or not -
steadily more tool vendors are dropping their IDE's and editors and
moving to an Eclipse + plugin model.

I haven't used refactoring much in my experience. I have used
factoring and have found VHDL to be burdensome in that. Maybe I'll
get a chance this winter to take a look at what Sigasi can do for me.
To be honest, I don't bother too much with new tools unless I can be
convinced they are worth looking at. In this case I might spend the
time with the tool to see if it fits my hands.

Rick

 

[rickman]

On Dec 2, 4:35 am, Martin Thompson <martin.j.thomp...@trw.com> wrote:

rickman <gnu...@gmail.com> writes:

Yes, if "only full word match" is used, then "write_n" won't match a
"write" search and replace so only "write" will change.

Here's a concrete example (to try and make the point I keep failing to
say clearly in a single sentence, sorry about that!):

I have a FIFO with a write pin on it, and a memory with a write pin
on it.

If I decide to change the FIFO to have an active low write, then I
rename the pin write_n.

I've instantiated the FIFO and the memory a dozen times each in my
large project.

If I do a global replace of "write" with "write_n" in the entire
project, all the references on the memory block will also change. If
I do an interactive global replace, I have to be really careful to get
it all right. Now, admittedly it's likely the compiler will catch it,
but I'll waste time sorting it all out.

Sigasi just does it all for me.

I get that. Maybe I have been coding "defensively" for long enough
that this is not an issue for me. I wouldn't likely be changing a
signal name in an interface like that. I might be changing the name
of the signal used in this entity that connects to that signal in the
interface, but I would have made it distinct to begin with. I often
instantiate the same module more than once and the connecting signal
names are extended to make them unique, ..._B1 ..._B2 for example.

I appreciate what you are saying the tool can do, I guess this feature
is just not that useful to me.

Sorry, the evaluation of the tool ladder. I don't know how this tool
is licensed, but I am very down on commercial tools because of the
licensing issues and the seeming lack of support. That automatically
puts a commercial tool below any open source tool when I am evaluating
them. So the commercial tool has to be significantly better for me to
want it.

There's another aspect of the licensing which I forgot to mention -
it's based around Eclipse, which is an open-source IDE which supports
Java and C well out of the box (dunno about Forth - as a
replacement for CW on it's own Eclipse isn't bad (and if you end up
using Xilinx or Altera soft processors, their IDE is also
Eclipse-based). So the investment in Eclipse might be worth it
irrespective of Sigasi... [I still haven't quite made up my mind
whether to switch from Emacs to Eclipse for C-coding. It doesn't have
a Usenet reader like Gnus though, so I'll have to keep Emacs around
for a bit yet!]

But how does Sigasi license their code? Do they trust their
customers? Or is there something that can keep me from using the tool
after some date or if I switch machines or the like? I currently only
have one piece of software that has a license that can bring my work
to a stop and that is the Lattice tools. I have a hard time
remembering just how the licensing works and only use the tools
sporadically. So it is once a year I try to use the tools and find
they don't work because the license has expired and I have to ask for
a new license file. I just went through this a month ago and the tool
works, but it still reminds me that I haven't bought maintenance. I'm
not sure if that means anything or is just a nag to get me to buy
something.

All of my other software, even if I've paid for it, is a version that
does not need a key. Once I had to move a product to a new machine
and couldn't find the original key for it. I tried to contact the
company to get a copy of the key and they didn't respond. So I got a
cracked version off the web somewhere and am happily back in
business.

IIRC you start typing the first few chars and hit ctrl-space, and it
gives you a drop-down of potential completions.

And those completions include both keywords as well as your signal/
variable names?

I think so yes (it's been a while since my eval)

That might be worth something. I am a fast typist, but not accurate.
I do very well filling in forms because of the auto-completion. The
whole typing thing is a real bother. :-*

If this feature works well enough I might consider
Sigasi. Especially if it could be used for other languages than just
VHDL. Is the VHDL aspect hard coded? I expect it will also support
Verilog, but what about generic languages? Does it have a means of
setting it up for an arbitrary language like CW does?

Raw Eclipse deals with other languages, not Verilog though.
Completion works in C, for example, and the "go to declaration" type things.

I can't remember the last time I did any C coding. I have moved to
Forth.

It's another little thing that adds up

Yes, little things can add up. I've spent enough time with this
thread that I feel I've done the first day of eval with the tool. So
maybe I'll get the demo at some point and give it a spin.

I am considering designing a Radio Controlled Clock using a GA4 which
would run off of two AAA cells for over a year. That should be a good
demo of the low power capabilities, no? Would that make you believe
that the chip can be pretty low power? The interesting part is that
this can be done with the GA144 nearly as easily as the GA4, you just
pay more to have 143 processors sitting idle 100% of the time and 1
processor idle 95% of the time.

Or you could split the job up and have all 144 of them sitting idle
for 99.9% of the time

Actually, splitting the job up will work best because of the limited
code storage in each node. 64 words of ROM and 64 words of RAM. I
think the F18B used in the GA4 will have 128 words of ROM and RAM.
One node could operate the ADC, one node could provide a PLL to sync
to the carrier, a third node demodulates the carrier and the fourth
runs the clock based on the received radio data. They can directly
execute instructions from an I/O port which can be SPI I believe (I
may be mixing apples and oranges here, SPI and direct execution). So
I think just one node can execute a Forth out of an SPI flash. This
fourth node, programmed in high level Forth, can do all the low speed
work processing the 1 bit per second radio data and running the
clock. I'm also considering using a (fifth?) node to manage a
switched cap power converter to optimize battery life. The limited I/
O count of the GA4 may not allow this.

I see the limited memory as the biggest drawback to programming these
chips. It will be interesting learning how to use them effectively.

Rick

 

[rickman]

On Dec 2, 10:32 am, Jan Decaluwe <j...@jandecaluwe.com> wrote:

rickman wrote:
On Dec 1, 12:20 pm, Jan Decaluwe <j...@jandecaluwe.com> wrote:
rickman wrote:

Yes, if "only full word match" is used, then "write_n" won't match a
"write" search and replace so only "write" will change.
It seems that you do not appreciate the difference between Rename
and global search and replace yet.

The same identifier may refer to a lot of different objects in
a design. Rename is based on object identify, not identifier identity.
This makes it intelligent and safe.

Oh? How does that work. When can you use the same name for different
objects???

Same name for a port on a different entity or component.
Same name for a formal argument of different functions.
Same name for a formal and an actual in a named association.
Same name that occurs in a comment string explanation.

Of course, I'm sure this is all obvious to you and I realize that
it must have been my explanation that was inadequate. But there
really was no need for this confusion. You could have seen all
these things for yourself by just spending one minute to see
the screencast. Sigh.

I don't know what a screencast is and I have never seen a sales tool
that conveyed any useful info in 1 minute.

Why would you if you can?

Because that's what we expect from an HDL, or any programming
language for that matter. Without it, no namespaces, no parametrization,
no hierarchy, no reuse.

Maybe that's what you expect, but I avoid using the same name for
different things. It causes a lot of confusion in debug. My current
project uses the same UART code in the target FPGA as in the test
bench. In simulation it can be hard to tell which UART XmitBuf I am
looking at. I ended up using colors to distinguish their traces.
Adding colors to traces in Active HDL is bit bothersome. It takes
some five or more mouse clicks to set a color, even if I am only using
two in the entire simulation. They need to have some sort of named
format for the waveform display so it can be applied with just one or
two mouse clicks.

Rick

 

[Mike Treseler]

On 11/30/2010 6:31 AM, rickman wrote:

I also spend time designing the
boards, writing test code, specs, docs and even conversing with
customers... oh yeah, and that slightly important part, looking for
customers.

Until the tide turns, this is everyone's problem.

-- Mike Treseler

 

[David Brown]

On 02/12/2010 16:02, rickman wrote:

On Dec 2, 5:14 am, David Brown<da...@westcontrol.removethisbit.com
wrote:
On 01/12/2010 19:36, rickman wrote:

On Dec 1, 12:20 pm, Jan Decaluwe<j...@jandecaluwe.com> wrote:
rickman wrote:

Yes, if "only full word match" is used, then "write_n" won't match a
"write" search and replace so only "write" will change.

It seems that you do not appreciate the difference between Rename
and global search and replace yet.

The same identifier may refer to a lot of different objects in
a design. Rename is based on object identify, not identifier identity.
This makes it intelligent and safe.

Oh? How does that work. When can you use the same name for different
objects??? Why would you if you can?

I think the key to understanding here is that "search and replace" is a
purely textual function, while "rename" is a type of "refactoring". I
have no experience with this in VHDL, but I have used it a bit with C
programming (again using Eclipse).

Calling it "refactoring" doesn't really help me understand what you
are saying.


The point here is that Eclipse and the plugin (CDT for C or C++, Sigasi
for VHDL) analyses the syntax of the code - it effectively has the
front-end of a compiler for the language in question. It is not just a
matter of syntax highlighting based on regular expressions, as used by
most editors. It knows the difference between an entity called "write",
a signal called "write" and a function called "write" - because, like a
VHDL compiler, it knows the difference between these concepts.

So you are saying that this tool will allow me to use the same name
for an entity that I use for a signal and not get them confused when I
change one of their names. I find that very unimportant. I never use
the same names on entities that I use for signals and I'm not sure you
can even do that in VHDL.

Fair enough.

Different people work in different ways, and some people don't have full
control over all the code - they are working with code from other
people. It is always a nice rule to avoid using the same name for
different things.

I can't say I've used the renaming refactoring in C programming with
Eclipse either - I'm just trying to explain the difference from a purely
textual search-and-replace, rather than to persuade you to /use/ the
feature!

I don't really care what the tools "know" and don't "know". I care
about what that does for me. In this case it sounds like it does
little that I would find interesting. I will say that if this stuff
can be made to work in real time with reasonable error indications
that are effective without being intrusive, then maybe it would be
worthwhile. But there are the other issues to consider of it being a
commercial product, support, cost and inflexibility of licensing.


Assuming Sigasi has similar functions to CDT, this will also allow fast
cross-linking of information between files. With CDT, you can hold your
mouse over an identifier and a tooltip will show you a short definition
of the identifier. You can navigate quickly to the definition of the
identifier, or to other uses of it.

I do that pretty easily now for signals and variables. They are
always declared in the same file. But this may be something that I
would need to see in action to appreciate.

Again, I've only used it with C programming - and there it definitely
/is/ useful. But it also depends on things like the size of the
project, the organisation, whether you have written everything yourself,
and whether you are just patching up old code or working concentrated on
the project. If you have a solid overview of all the identifiers in
your head, you don't need to look them up.

Whether or not you find this sort of thing useful is up to you.
Personally, I am using Eclipse more and more for C programming, though I
still like a simpler and faster text editor for many other tasks.

There are other editors that can do a certain amount of refactoring, or
support the use of "tag" information for cross-navigation by identifier,
but I don't think anything else has the support Eclipse provides.
That's why a company like Sigasi has built a plugin for Eclipse -
Eclipse gives them a solid base for the refactoring, and they only need
to worry about the VHDL-specific part. It's also why - like it or not -
steadily more tool vendors are dropping their IDE's and editors and
moving to an Eclipse + plugin model.

I haven't used refactoring much in my experience. I have used
factoring and have found VHDL to be burdensome in that. Maybe I'll
get a chance this winter to take a look at what Sigasi can do for me.
To be honest, I don't bother too much with new tools unless I can be
convinced they are worth looking at. In this case I might spend the
time with the tool to see if it fits my hands.

Well, I leave it to the people with connection to or experience with
Sigasi to do the persuading. I'm just trying to help explain a couple
of features, so that you (and others reading this) can get a better idea
of what the tool can do that a simpler text editor cannot.

 

[Jan Decaluwe]

rickman wrote:

On Dec 2, 10:32 am, Jan Decaluwe <j...@jandecaluwe.com> wrote:
rickman wrote:


Of course, I'm sure this is all obvious to you and I realize that
it must have been my explanation that was inadequate. But there
really was no need for this confusion. You could have seen all
these things for yourself by just spending one minute to see
the screencast. Sigh.

I don't know what a screencast is

I'll hold your hand:

http://en.wikipedia.org/wiki/Screencast

and I have never seen a sales tool
that conveyed any useful info in 1 minute.

Look, I can assure you that many good engineers find such a
screencast very useful. I am also of the opinion that the
people who make such things, for people like you, through
hard work, deserve much better than this. Your prejudices
are so high that you don't even want to *try*, even though
it takes only a fraction of the time you spend on writing
posts with a much lower information content. Beats me.

Time to review good old school engineering practices.

--
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Python as a HDL: http://www.myhdl.org
VHDL development, the modern way: http://www.sigasi.com
Analog design automation: http://www.mephisto-da.com
World-class digital design: http://www.easics.com

 

[rickman]

On Dec 13, 6:48 am, Jan Decaluwe <j...@jandecaluwe.com> wrote:

rickman wrote:
On Dec 2, 10:32 am, Jan Decaluwe <j...@jandecaluwe.com> wrote:
rickman wrote:

Of course, I'm sure this is all obvious to you and I realize that
it must have been my explanation that was inadequate. But there
really was no need for this confusion. You could have seen all
these things for yourself by just spending one minute to see
the screencast. Sigh.

I don't know what a screencast is

I'll hold your hand:

http://en.wikipedia.org/wiki/Screencast

and I have never seen a sales tool
that conveyed any useful info in 1 minute.

Look, I can assure you that many good engineers find such a
screencast very useful. I am also of the opinion that the
people who make such things, for people like you, through
hard work, deserve much better than this. Your prejudices
are so high that you don't even want to *try*, even though
it takes only a fraction of the time you spend on writing
posts with a much lower information content. Beats me.

Wonderful for them! I find that nearly every video I have watched was
far too slow paced, covered too little material at too shallow a level
and has provided very little information relative to the marketing
content. I just don't watch them unless it is a topic I am extremely
interested in. This product has a lot of strikes against it, so in
the end the minute details of what it does is not of great interest to
me. It has been described here and I don't find it compelling.

Time to review good old school engineering practices.

I have no idea what that means. But I find your analysis of my
opinions to be rude and pointless. Clearly you wish to offend me.
But it is much less clear if you think that somehow you are being
persuasive.

Rick

 

[Jan Decaluwe]

rickman wrote:

On Dec 13, 6:48 am, Jan Decaluwe <j...@jandecaluwe.com> wrote:

Time to review good old school engineering practices.

I have no idea what that means. But I find your analysis of my
opinions to be rude and pointless. Clearly you wish to offend me.

No, but I am getting extremely frustrated that it is proving
impossible for me to have a meaningful discussion with you, though
I think the topics should be of mutual interest. No matter how hard
I try, I seem to fighting what I perceive as an attitude of
unwillingness, wasting everybody's time - this screencast
incident being an absolute low point.

Of course I should limit myself to deciding what I should do
and not try to tell you what you should do - that is
overreaction, and I take that back.

Jan

--
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Python as a HDL: http://www.myhdl.org
VHDL development, the modern way: http://www.sigasi.com
Analog design automation: http://www.mephisto-da.com
World-class digital design: http://www.easics.com