Brain Cramps...

[rickman]

Geeze! There are times I wonder how I manage to live without full
time care! I chased the strangest bug and could not find it to save
my life. If it had been a snake...

The simulation was exactly what I wanted and I've been doing this a
long time, so I'm not accustomed to the chip not working just like the
simulation. I downloaded the design and things aren't working like
they should. The data from the 232 interface was not synching as if
it were not the correct rate. Putting a probe on the data shows it is
clocking way too fast, a bit is coming out at the rate of the 16x baud
clock! I brought out several timing strobes they were all over the
map, all two fast, but not even steady. More like the clock was
glitching all over the place...

To make a long story short... opps, too late for that... I eventually
read the compiler warnings. I had seen a warning earlier about
finding 9 feedback paths or words to that effect and that didn't quite
wake me up. It was complaining about the lack of signals in the
sensitivity list of a clocked process... or so I thought. Instead of
(rising_edge(clk)) I had used ('1' = clk). Aldec used the sensitivity
list without complaining and so it simulated perfectly. The real
world saw it differently... async logic running at top speed! No
wonder the chip was warmer than usual...

A couple of hours down the drain... yes, a couple of hours! I kept
adding debug points even though none of them made any sense.

Rick

 

[Rob Gaddi]

On 11/23/2010 8:08 AM, rickman wrote:

Geeze! There are times I wonder how I manage to live without full
time care! I chased the strangest bug and could not find it to save
my life. If it had been a snake...

[snip]

A couple of hours down the drain... yes, a couple of hours! I kept
adding debug points even though none of them made any sense.

Rick

There's a lesson to be learned from all that, Rick, but I'll be damned
if I know what it is.

--
Rob Gaddi, Highland Technology
Email address is currently out of order

 

[rickman]

On Nov 23, 12:08 pm, Rob Gaddi <rga...@technologyhighland.com> wrote:

On 11/23/2010 8:08 AM, rickman wrote:

Geeze!  There are times I wonder how I manage to live without full
time care!  I chased the strangest bug and could not find it to save
my life.  If it had been a snake...

 > [snip]

A couple of hours down the drain... yes, a couple of hours!  I kept
adding debug points even though none of them made any sense.

Rick

There's a lesson to be learned from all that, Rick, but I'll be damned
if I know what it is.

Don't program in your sleep! Did I mention that much of this was done
very late?

Rick

 

[Nial Stewart]

Instead of (rising_edge(clk)) I had used ('1' = clk).

Do you type in all your code?

I have a template set up so Ctrl-P inserts a 'standard' synchronous process
to save time and cut down this sort of problem.


Nial.

 

[rickman]

On Nov 24, 6:15 am, "Nial Stewart"
<nial*REMOVE_TH...@nialstewartdevelopments.co.uk> wrote:

Instead of (rising_edge(clk)) I had used ('1' = clk).

Do you type in all your code?

I have a template set up so Ctrl-P inserts a 'standard' synchronous process
to save time and cut down this sort of problem.

I wish I had a smart(er) editor that understood VHDL a bit more. I
have some search/replace regex strings I copy and paste from one file
to another which change an entity port list into a port map or a
signal list. This helps with the tedium of instantiation.

I've never worried about the sync process before because I haven't
made a mistake like this without it showing up in the simulation.
That is the interesting part. With the way a simulation works,
comparing the clock to '1' gives exactly the same results as
rising_edge. Given the function of the sensitivity list, it seems
like the rising_edge function should be redundant. I believe it
includes some logic to only return true if the preceding state was a
'0' or 'L' rather than just any other value than '1'. I suppose a '1' simulation would not work the same triggering on a change from 'H'
to '1' as well as the others.

I'm not likely to forget this and even if I make the same mistake,
I'll likely catch it when I check the compile warnings...

But to answer your question, no, I use CodeWright and I could define
some macro to copy some text into the code, but it wouldn't be at the
correct indentation level. To do that would require getting to know
CodeWright far too well. I keep saying some day I'll look into
switching to... (insert your favorite editor here). I think EMACS is
the one I've heard the most about.

Rick

 

[Jonathan Bromley]

On Wed, 24 Nov 2010 11:22:33 -0800 (PST), rickman wrote:

Instead of (rising_edge(clk)) I had used ('1' = clk).
....
With the way a simulation works,
comparing the clock to '1' gives exactly the same results as
rising_edge. Given the function of the sensitivity list, it seems
like the rising_edge function should be redundant.

BE CAREFUL!

If there was no asynch reset in your process, then what probably
happened was that the tool saw
process (clock) begin if clock='1' then...
Not recognizing a standard clocked process, the tool would
then assume it had a combinational process. Betcha there
was a warning somewhere in the synth report about automatically
completing the incomplete sensitivity list. Consequently you
got a pile of transparent latches, enabled (made transparent)
by clock='1'.

On the other hand...

If you have an asynch reset in your sensitivity list, it is
simply not true that rising_edge is redundant.

Consider
process (clock, reset) begin
if (reset = '1' then
do-reset-ish-things;
elsif clock = '1' then
do-clocked-things;
end if;
end process;

Suppose clock is held at '1', with no edges, and you take
reset from true to false. The process trips, reset='0' so
the reset action doesn't happen, clock='1' so the clocked
action DOES happen. Bzzzt! you got a spurious extra clock
action on the trailing edge of reset.

That is why the old-fashioned (pre std_logic_1164) style
of VHDL clocked process, still seen in some dinosaur code
today, looks like this:

process (clock, reset) begin
if (reset = '1' then
do-reset-ish-things;
elsif clock'event and (clock = '1') then
do-clocked-things;
end if;
end process;

Note the extra clock'event test! The rising_edge
function includes exactly this test.

This is also the reason why Verilog clocked process
sensitivity lists look like

always @(posedge clock or posedge reset)

The "posedge reset" often mystifies beginners - hey,
it's a level-sensitive reset, isn't it? - but exactly
the same problem arises of a spurious clock action in
simulation on the trailing edge of reset. Indeed, it's
even worse in Verilog because you don't test the clock
level (posedge did that for you!) so the spurious action
occurs regardless of the value of clock.

Many synth tools will simply choke on any non-standard
form of clocked process; your tool evidently made the
best it could of it, with appropriately disastrous results.

Sorry to hear about your wasted time. Sounds to me like
a good argument for tools NOT to complete the sensitivity
list automatically when they think they've found a
combinational process.
--
Jonathan Bromley

 

[Philippe]

On Nov 24, 8:22 pm, rickman <gnu...@gmail.com> wrote:

I wish I had a smart(er) editor that understood VHDL a bit more.

Hi Rick,

You might want to take a look at Sigasi: http://www.sigasi.com
We have a VHDL development environment with a VHDL parser inside. This
way, as you put it, the VHDL editor "understands" what you type.

I have some search/replace regex strings I copy and paste from one file
to another which change an entity port list into a port map or a
signal list.  This helps with the tedium of instantiation.

Thirty second screencast on instantiations:
http://www.sigasi.com/screencast/entity-instantiation

kind regards

--
Philippe Faes
Sigasi

 

[Martin Thompson]

Philippe <philippe.faes@gmail.com> writes:

On Nov 24, 8:22 pm, rickman <gnu...@gmail.com> wrote:

I wish I had a smart(er) editor that understood VHDL a bit more.

Hi Rick,

You might want to take a look at Sigasi: http://www.sigasi.com

Seconded... Although I haven't bought a license (sorry Philippe!), as
during my eval, I still kept ending up back in Emacs, I will be
recommending it to my "less text-based" colleagues

And I may still get one for myself for the refactoring tools.

Cheers,
Martin

--
martin.j.thompson@trw.com
TRW Conekt - Consultancy in Engineering, Knowledge and Technology
http://www.conekt.co.uk/capabilities/39-electronic-hardware

 

[rickman]

On Nov 25, 5:26 am, Philippe <philippe.f...@gmail.com> wrote:

On Nov 24, 8:22 pm, rickman <gnu...@gmail.com> wrote:



I wish I had a smart(er) editor that understood VHDL a bit more.

Hi Rick,

You might want to take a look at Sigasi:http://www.sigasi.com
We have a VHDL development environment with a VHDL parser inside. This
way, as you put it, the VHDL editor "understands" what you type.

I have some search/replace regex strings I copy and paste from one file
to another which change an entity port list into a port map or a
signal list.  This helps with the tedium of instantiation.

Thirty second screencast on instantiations:http://www.sigasi.com/screencast/entity-instantiation

kind regards

--
Philippe Faes
Sigasi

To what extent does the editor "understand" the VHDL I type? I am
already using an editor that recognizes keywords, comments, numbers,
ect... and colors them as I require. What more does the Sigasi editor
do?

Rick

 

[Martin Thompson]

About Sigasi, rickman <gnuarm@gmail.com> writes:

To what extent does the editor "understand" the VHDL I type? I am
already using an editor that recognizes keywords, comments, numbers,
ect... and colors them as I require. What more does the Sigasi editor
do?

It understands the structure of the design - what instantiates what,
what calls what functions.

For example if you rename a port entry on an entity, it can go through
the design changing all the instances of that entity to match. You
*can* do this with careful use of global search/replace, but this
"just works"

Another example: you can take a process within the entity you're
working on and say "make me an entity of this process", which it will
do, putting the IO in and instantiating it where the process used to
be. This involves much more than just "matching keywords".

Get the eval and have a play

(BTW, although I may sound like a salesman, I have no connection with
Sigasi, other than being impressed with the demo I still haven't
quite been torn away from Emacs vhdl-mode though... even though it's
missing the two features above!

Cheers,
Martin

--
martin.j.thompson@trw.com
TRW Conekt - Consultancy in Engineering, Knowledge and Technology
http://www.conekt.co.uk/capabilities/39-electronic-hardware

 

[Nial Stewart]

One thing that could be done to expedite my code banging is auto-
completion of my signal and variable names, or better, completion of
lines like declarations. Or even automatically adding the entire
declaration once I add a usage of a signal/variable. I find most of
my "non-productive" typing has to do with the required support for the
object in the design, not the actual usage of them.

I think Sigasi can do some of this.

The downside for me is the EURO 499 ($650) _annual_ licence fee (or
EURO 1500 [$1900] perpetual licence).



Nial.

 

[rickman]

On Nov 29, 4:38 am, Martin Thompson <martin.j.thomp...@trw.com> wrote:

About Sigasi, rickman <gnu...@gmail.com> writes:

To what extent does the editor "understand" the VHDL I type?  I am
already using an editor that recognizes keywords, comments, numbers,
ect... and colors them as I require.  What more does the Sigasi editor
do?

It understands the structure of the design - what instantiates what,
what calls what functions.

For example if you rename a port entry on an entity, it can go through
the design changing all the instances of that entity to match.  You
*can* do this with careful use of global search/replace, but this
"just works"

I'm not sure I understand what you are saying here. Are you saying it
changes the name of the signal in the entity declaration? What about
the rest of the entity? I guess I really don't see how this is
different from a global search/replace.

Another example: you can take a process within the entity you're
working on and say "make me an entity of this process", which it will
do, putting the IO in and instantiating it where the process used to
be.  This involves much more than just "matching keywords".

I can't say I have done this very often, if ever. I have split an
entity into two but I don't recall ever taking a single process and
promoting it to an entity. When the tool does this, does it also add
the required signal declarations? How does it know which signals need
to be in the ports list and which need to be declared as local
signals?

Get the eval and have a play

I learned a long time ago that before I spend the time to learn a
tool, I need to have a pretty good reason to make the investment. So
far I haven't see such a reason to learn the Sigasi tool.

(BTW, although I may sound like a salesman, I have no connection with
Sigasi, other than being impressed with the demo I still haven't
quite been torn away from Emacs vhdl-mode though... even though it's
missing the two features above!

It has been very seldom that I have seen a tool which I decided I
needed enough to drop an old tool and pick up the new. However, there
has been a number of times that I realized that my present tool was
not doing the job as well as I would like and I then started looking
for a better tool. That is the case now, but I haven't seen any
features of Sigasi that help deal with any of the issues I experience
with CodeWright.

One thing that could be done to expedite my code banging is auto-
completion of my signal and variable names, or better, completion of
lines like declarations. Or even automatically adding the entire
declaration once I add a usage of a signal/variable. I find most of
my "non-productive" typing has to do with the required support for the
object in the design, not the actual usage of them.

Rick

 

[Dave]

I do embedded development with C++ and VHDL in parallel and have
always longed for an editing tool for the VHDL side that came even
close to what is available for C/C++ development. I'm only a couple
of days into my Sigasi trial but so far it feels like what I have been
looking for. The tool understands VHDL and allows painless navigation
around the design in addition to the code refactoring features (auto-
completion, intelligent signal renaming, automatic declaration of
signals missing from an instantiation etc...).

I have nothing to-do with the people behind Sigasi but I think it is
worth giving it a shot. Their support is very fast also if you have
any questions.

 

[Martin Thompson]

rickman <gnuarm@gmail.com> writes:

On Nov 29, 4:38 am, Martin Thompson <martin.j.thomp...@trw.com> wrote:
About Sigasi, rickman <gnu...@gmail.com> writes:

To what extent does the editor "understand" the VHDL I type?  I am
already using an editor that recognizes keywords, comments, numbers,
ect... and colors them as I require.  What more does the Sigasi editor
do?

It understands the structure of the design - what instantiates what,
what calls what functions.

For example if you rename a port entry on an entity, it can go through
the design changing all the instances of that entity to match.  You
*can* do this with careful use of global search/replace, but this
"just works"

I'm not sure I understand what you are saying here. Are you saying it
changes the name of the signal in the entity declaration? What about
the rest of the entity? I guess I really don't see how this is
different from a global search/replace.

Yes, it changes the entity delaaration, uses of that port inside the
entity and the port mapping of the instantiation(s) of the entity.

This is better than a global (ie multi-file) replace because when you
change "write" on one entity to "write_n" you don't want every entity
with a "write" pin changing! And heaven help you changing rd to wr -
hope the characters 'rd' don't appear in any other pins anywhere else
(like the "one_third" pin of your "divide_by_three" entity

http://www.sigasi.com/screencast/rename (1 minute video)

Another example: you can take a process within the entity you're
working on and say "make me an entity of this process", which it will
do, putting the IO in and instantiating it where the process used to
be.  This involves much more than just "matching keywords".

I can't say I have done this very often, if ever.

Possibly because it's an awful lot of pain?

I have split an entity into two

Which is a similar process (if you'll excuse the pun .

but I don't recall ever taking a single process and
promoting it to an entity. When the tool does this, does it also add
the required signal declarations? How does it know which signals need
to be in the ports list and which need to be declared as local
signals?

Things that go "into" the process or "out of" the process are entity
ports. There's no need for local signals, as it's just one process
you're pushing.

Get the eval and have a play

I learned a long time ago that before I spend the time to learn a
tool, I need to have a pretty good reason to make the investment. So
far I haven't see such a reason to learn the Sigasi tool.

Forgive me, but if you're still using Codewright (unless it has
changed immeasureably since I migrated from it to Emacsin the CW5.x
days) I'd be amazed if Sigasi wouldn't help.

How much time do you spend copying "columns" from entities and
changing : to => in port maps to instance a component? That used to
drive me demented in CW.

(BTW, although I may sound like a salesman, I have no connection with
Sigasi, other than being impressed with the demo I still haven't
quite been torn away from Emacs vhdl-mode though... even though it's
missing the two features above!

It has been very seldom that I have seen a tool which I decided I
needed enough to drop an old tool and pick up the new.

Me too. Migrating from CW to Emacs was the last time I recall doing
it. And that was a *serious* learning curve, but still worth it.
Sigasi is way easier IMHO.

However, there
has been a number of times that I realized that my present tool was
not doing the job as well as I would like and I then started looking
for a better tool. That is the case now, but I haven't seen any
features of Sigasi that help deal with any of the issues I experience
with CodeWright.

One thing that could be done to expedite my code banging is auto-
completion of my signal and variable names

Yes, it does that. I kind of took that as read (coming from VHDL-mode)

or better, completion of lines like declarations.

If I understand you rightly, yes.

Or even
automatically adding the entire declaration once I add a usage of a
signal/variable.

Not yet - that would be fun. I guess it would have to ask you what
type to make the signal/variable, which might interrupt my flow of
coding though.

Some Other things it does (full list is at http://www.sigasi.com/featurelist):
* Autocomplete templates for "if", "process", and the rest.
* Line alignment (so all your : and <= and => line up nicely)
* automatic reindentation
* sensitivity list checking
* generate makefiles
* Built in errors and warnings (no need to compile, it does it on the
fly) Having this "in-the-editing-loop" is more of a boon than you'd
think until you've tried it (IMHO)
* "Go to declaration" (CW might be configurable to do this?)

I find most of my "non-productive" typing has to do with the
required support for the object in the design, not the actual usage
of them.

Indeed, that's precisely where the tools like Emacs' vhdl-mode and
Sigasi come in.

Anyway, I probably ought to shut up now and let the Sigasi people talk
about their own tool, they'll no doubt be much more eloquent than I!

Cheers,
Martin

--
martin.j.thompson@trw.com
TRW Conekt - Consultancy in Engineering, Knowledge and Technology
http://www.conekt.co.uk/capabilities/39-electronic-hardware

 

[rickman]

On Nov 30, 8:18 am, Martin Thompson <martin.j.thomp...@trw.com> wrote:

rickman <gnu...@gmail.com> writes:
On Nov 29, 4:38 am, Martin Thompson <martin.j.thomp...@trw.com> wrote:
About Sigasi, rickman <gnu...@gmail.com> writes:

To what extent does the editor "understand" the VHDL I type? I am
already using an editor that recognizes keywords, comments, numbers,
ect... and colors them as I require. What more does the Sigasi editor
do?

It understands the structure of the design - what instantiates what,
what calls what functions.

For example if you rename a port entry on an entity, it can go through
the design changing all the instances of that entity to match. You
*can* do this with careful use of global search/replace, but this
"just works"

I'm not sure I understand what you are saying here.  Are you saying it
changes the name of the signal in the entity declaration?  What about
the rest of the entity?  I guess I really don't see how this is
different from a global search/replace.

Yes, it changes the entity delaaration, uses of that port inside the
entity and the port mapping of the instantiation(s) of the entity.

This is better than a global (ie multi-file) replace because when you
change "write" on one entity to "write_n" you don't want every entity
with a "write" pin changing!  And heaven help you changing rd to wr -
hope the characters 'rd' don't appear in any other pins anywhere else
(like the "one_third" pin of your "divide_by_three" entity

That's not a big deal. My editor, and I suspect many others, has a
check box on the search that says "only full word match" so that
write_n won't match a write search.

Another example: you can take a process within the entity you're
working on and say "make me an entity of this process", which it will
do, putting the IO in and instantiating it where the process used to
be. This involves much more than just "matching keywords".

I can't say I have done this very often, if ever.  

Possibly because it's an awful lot of pain?

It's not a pain issue. I can't remember ever taking just a process
and turning it into an entity. I typically have some amount of
concurrent code to go with a process and the only times I can remember
doing this it was more than one process. I don't like instantiation
because of the verbosity. But I don't let that determine my code
structure.

I have split an entity into two

Which is a similar process (if you'll excuse the pun .

I've also combined entities. Does the tool help with either combining
or splitting processes at arbitrary margins?

but I don't recall ever taking a single process and
promoting it to an entity.  When the tool does this, does it also add
the required signal declarations?  How does it know which signals need
to be in the ports list and which need to be declared as local
signals?

Things that go "into" the process or "out of" the process are entity
ports.  There's no need for local signals, as it's just one process
you're pushing.

Exactly. I nearly always have some concurrent logic that goes with
the process.

Get the eval and have a play

I learned a long time ago that before I spend the time to learn a
tool, I need to have a pretty good reason to make the investment.  So
far I haven't see such a reason to learn the Sigasi tool.

Forgive me, but if you're still using Codewright (unless it has
changed immeasureably since I migrated from it to Emacsin the CW5.x
days) I'd be amazed if Sigasi wouldn't help.

How much time do you spend copying "columns" from entities and
changing : to => in port maps to instance a component?  That used to
drive me demented in CW.

That's the part I have regex lines to handle. I have to tweek the
last line of the port list so it has a terminator, apply the regex,
tweek the terminator back and adjust the column alignments (manually,
I am a little OCD about this part). Then I have everything perfectly
formatted and even the comments within the port list are transferred.
After a dozen or so passes with the regex it was tweeked enough to
cover all the weird cases such as including "_" in the names, etc. I
have one regex to generate the instantiation port map and another to
generate signal declarations.

I may spend a little more time with it so it will write the code for
the entity body given a customer's description of the problem. ;^)

(BTW, although I may sound like a salesman, I have no connection with
Sigasi, other than being impressed with the demo I still haven't
quite been torn away from Emacs vhdl-mode though... even though it's
missing the two features above!

It has been very seldom that I have seen a tool which I decided I
needed enough to drop an old tool and pick up the new.  

Me too.  Migrating from CW to Emacs was the last time I recall doing
it.  And that was a *serious* learning curve, but still worth it.
Sigasi is way easier IMHO.

I only have two problems with Sigasi. One is spending time with it to
be convinced that it is better in some so far, unidentified way. The
other is that it is commercial software with an up front cost and I
assume a recurring cost. Being a small shop I don't often pay for
tools unless I am absolutely convinced I need them. Notice I said
"need", not "would like" or "nice to have" or even "would be more
productive if". When I am working the VHDL I bang code all day long.
But I don't do it all the time. I also spend time designing the
boards, writing test code, specs, docs and even conversing with
customers... oh yeah, and that slightly important part, looking for
customers. I'm not inclined to spend a kilobuck on something that
will give me a minor improvement in what I do maybe 10% of the time.
Then on top of it all, a tool that requires support from a company is
already a rung lower on the ladder than a tool that is either static
because it is already unsupported (Codewright and Eudora) or open
source and supported by an active community. The most useful tools I
have are (other than the FPGA tools that I have no choice with) are
one of those two categories. The biggest bane to my existence, tool-
wise, is the licensed tools I have to keep running, but only weekdays
9-5. I am having a problem with the Lattice tools right now that I am
having to go through support (or around actually) to resolve.

However, there
has been a number of times that I realized that my present tool was
not doing the job as well as I would like and I then started looking
for a better tool.  That is the case now, but I haven't seen any
features of Sigasi that help deal with any of the issues I experience
with CodeWright.

One thing that could be done to expedite my code banging is auto-
completion of my signal and variable names

Yes, it does that.  I kind of took that as read (coming from VHDL-mode)

This could be interesting. How does that work? My email program has
auto-completion of email addresses and my browser has auto completion
of form fields. As I type it pops up a list and as I type more the
list grows shorter. At any point I use the up or down arrow keys to
select the entry I want and hit enter. Sometimes in a web page they
haven't implemented it correctly and using return causes the form to
be submitted. Otherwise this is a real time saver.

Is this the way it works in Sigasi with signal names? If you are
typing a signal name as the first thing on a line, does it add the
assignment operator? What happens the first time you type an
assignment to a signal or variable? Does it add a declaration for the
name?

 or better, completion of lines like declarations.  

If I understand you rightly, yes.

Or even
automatically adding the entire declaration once I add a usage of a
signal/variable.

Not yet - that would be fun.  I guess it would have to ask you what
type to make the signal/variable, which might interrupt my flow of
coding though.

Yep, I don't know if the interruption would be worth it or not. Maybe
selecting the name and using a function key. Keeping the declarations
in line with my signal/variable usage is one of the time consumers/
wasters of my coding time.

Some Other things it does (full list is athttp://www.sigasi.com/featurelist):
* Autocomplete templates for "if", "process", and the rest.
Nice, but not a big deal, for me anyway.

* Line alignment (so all your : and <= and => line up nicely)
That would be nice.

* automatic reindentation
This is a PITA for me. Regex scripting doesn't work so well here.

You have to make a pass for each indentation level in use.

* sensitivity list checking
* generate makefiles
* Built in errors and warnings (no need to compile, it does it on the
  fly) Having this "in-the-editing-loop" is more of a boon than you'd
  think until you've tried it (IMHO)
I would agree with that. I have been looking at a programming tool

that has the philosophy of catching errors as soon in the development
process as possible. Some errors that might not be caught until run
time can be checked in a language aware editor.

* "Go to declaration" (CW might be configurable to do this?)
No, CW doesn't understand the language that well. It really only

knows keywords, names, numbers, comments and strings. Structure is
beyond CW.

I find most of my "non-productive" typing has to do with the
required support for the object in the design, not the actual usage
of them.

Indeed, that's precisely where the tools like Emacs' vhdl-mode and
Sigasi come in.

Anyway, I probably ought to shut up now and let the Sigasi people talk
about their own tool, they'll no doubt be much more eloquent than I!

So far I've gotten a lot more from you than I have them. I seem to
recall years ago Aldec was big on sending out CDs of their software
for you to try. They would call me and push the CD so I would say
"send it" and then it would sit waiting for me to spend the time to
learn the stuff. I never did. Then I paid for my Lattice tools and
was expecting a copy of Modelsim. By the time I called in to get the
license keys, they had switched and would only license Aldec
ActiveHDL. I was livid over the apparent "bait an switch". Having no
choice, and believe me I tried!, I learned ActiveHDL and it turned out
to be pretty durn good. I like it a lot now and it doesn't have the
long running Modelsim memory allocation crash bug.

I'll be finished with my VHDL coding in another week or two and won't
want to spend time with a VHDL tool. I am going to look into a design
using a multiprocessor chip that is micro power or nano power or pico
power, what ever it is being called these days. Idle state is 100
micro watts per processor with 144 processors on the chip. Running
full out they use 4.5 mW at over 500 MIPS! The transition between
running and idle is just a matter of reading a processor I/O port with
virtually no time wasted ramping clocks up and down. They have
described a four node chip that I might use to design a radio
controlled clock "atomic clock" as a demonstration of the low power
capabilities. This will use a totally different set of tools than
Sigasi, et al.

Rick

 

[Jan Decaluwe]

Andy wrote:

On Nov 30, 8:31 am, rickman <gnu...@gmail.com> wrote:
On Nov 30, 8:18 am, Martin Thompson <martin.j.thomp...@trw.com> wrote:
rickman <gnu...@gmail.com> writes:
On Nov 29, 4:38 am, Martin Thompson <martin.j.thomp...@trw.com> wrote:
but I don't recall ever taking a single process and
promoting it to an entity. When the tool does this, does it also add
the required signal declarations? How does it know which signals need
to be in the ports list and which need to be declared as local
signals?
Things that go "into" the process or "out of" the process are entity
ports. There's no need for local signals, as it's just one process
you're pushing.
Exactly. I nearly always have some concurrent logic that goes with
the process.

I'm curious about the case where a process is the only reader and
writer of a signal (obviously declared outside the process). Does
Sigasi know that it does not need to create an inout port for that
signal when it promotes the process to an entity?

It sure does.

Does Sigasi only
look at the process, and not the rest of the architecture to which it
belongs, when deciding which signals need promoting to ports?

It looks at the complete picture, because it understands the code as a
complete design.

Jan

--
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Python as a HDL: http://www.myhdl.org
VHDL development, the modern way: http://www.sigasi.com
Analog design automation: http://www.mephisto-da.com
World-class digital design: http://www.easics.com

 

[Andy]

On Nov 30, 8:31 am, rickman <gnu...@gmail.com> wrote:

On Nov 30, 8:18 am, Martin Thompson <martin.j.thomp...@trw.com> wrote:
rickman <gnu...@gmail.com> writes:
On Nov 29, 4:38 am, Martin Thompson <martin.j.thomp...@trw.com> wrote:
but I don't recall ever taking a single process and
promoting it to an entity.  When the tool does this, does it also add
the required signal declarations?  How does it know which signals need
to be in the ports list and which need to be declared as local
signals?

Things that go "into" the process or "out of" the process are entity
ports.  There's no need for local signals, as it's just one process
you're pushing.

Exactly.  I nearly always have some concurrent logic that goes with
the process.

I'm curious about the case where a process is the only reader and
writer of a signal (obviously declared outside the process). Does
Sigasi know that it does not need to create an inout port for that
signal when it promotes the process to an entity? Does Sigasi only
look at the process, and not the rest of the architecture to which it
belongs, when deciding which signals need promoting to ports?

I use local variables for this case, but many others use a signal
because they prefer the postponed update semantics of signals vs
variables.

Andy

 

[Martin Thompson]

rickman <gnuarm@gmail.com> writes:

On Nov 30, 8:18 am, Martin Thompson <martin.j.thomp...@trw.com> wrote:
rickman <gnu...@gmail.com> writes:
On Nov 29, 4:38 am, Martin Thompson <martin.j.thomp...@trw.com> wrote:
Yes, it changes the entity delaaration, uses of that port inside the
entity and the port mapping of the instantiation(s) of the entity.

This is better than a global (ie multi-file) replace because when you
change "write" on one entity to "write_n" you don't want every entity
with a "write" pin changing!  And heaven help you changing rd to wr -
hope the characters 'rd' don't appear in any other pins anywhere else
(like the "one_third" pin of your "divide_by_three" entity

That's not a big deal. My editor, and I suspect many others, has a
check box on the search that says "only full word match" so that
write_n won't match a write search.

No, my point was if you have "write" on another entity you don;t want
that one changing as well.

I learned a long time ago that before I spend the time to learn a
tool, I need to have a pretty good reason to make the investment.  So
far I haven't see such a reason to learn the Sigasi tool.

Forgive me, but if you're still using Codewright (unless it has
changed immeasureably since I migrated from it to Emacsin the CW5.x
days) I'd be amazed if Sigasi wouldn't help.

How much time do you spend copying "columns" from entities and
changing : to => in port maps to instance a component?  That used to
drive me demented in CW.

That's the part I have regex lines to handle. I have to tweek the
last line of the port list so it has a terminator, apply the regex,
tweek the terminator back and adjust the column alignments (manually,
I am a little OCD about this part).

All stuff you'd rather not do, right?

Then

That's the key word After doing some stuff...

I have everything perfectly formatted and even the comments within
the port list are transferred. After a dozen or so passes with the
regex it was tweeked enough to cover all the weird cases such as
including "_" in the names, etc. I have one regex to generate the
instantiation port map and another to generate signal declarations.

OK, you've gotten further configurating CW than I ever did

I may spend a little more time with it so it will write the code for
the entity body given a customer's description of the problem. ;^)

Good plan, let us know when you've got that sorted, we could all use
it

(BTW, although I may sound like a salesman, I have no connection with
Sigasi, other than being impressed with the demo I still haven't
quite been torn away from Emacs vhdl-mode though... even though it's
missing the two features above!

It has been very seldom that I have seen a tool which I decided I
needed enough to drop an old tool and pick up the new.  

Me too.  Migrating from CW to Emacs was the last time I recall doing
it.  And that was a *serious* learning curve, but still worth it.
Sigasi is way easier IMHO.

I only have two problems with Sigasi. One is spending time with it to
be convinced that it is better in some so far, unidentified way.

Well, with respect, I've indentified a number of ways it's better than
raw Codewright. The fact that you've overcome those was unknown to
me. I see below that I've also identified some things you *would* like...

The other is that it is commercial software with an up front cost
and I assume a recurring cost. Being a small shop I don't often pay
for tools unless I am absolutely convinced I need them. Notice I
said "need", not "would like" or "nice to have" or even "would be
more productive if". When I am working the VHDL I bang code all day
long. But I don't do it all the time.
I also spend time designing the boards, writing test code, specs,
docs and even conversing with customers... oh yeah, and that
slightly important part, looking for customers.

This I also understand - I'd like to use some of the c-to-gates tools,
but I don't want to pay for a whole year's worth of flat-out license
when I'd use it maybe 25% of the year.

Emacs also suits me nicely license-wise!

I'm not inclined to spend a kilobuck on something that will give me
a minor improvement in what I do maybe 10% of the time. Then on top
of it all, a tool that requires support from a company is already a
rung lower on the ladder

Sorry, which ladder are you talking about?

than a tool that is either static because it is already
unsupported (Codewright and Eudora) or open source and supported by
an active community. The most useful tools I have are (other than
the FPGA tools that I have no choice with) are one of those two
categories. The biggest bane to my existence, tool- wise, is the
licensed tools I have to keep running, but only weekdays 9-5. I am
having a problem with the Lattice tools right now that I am having
to go through support (or around actually) to resolve.

Agreed - licensed tools can cause a lot of pain!

<about autocompletion>

Is this the way it works in Sigasi with signal names? If you are
typing a signal name as the first thing on a line, does it add the
assignment operator? What happens the first time you type an
assignment to a signal or variable? Does it add a declaration for the
name?

IIRC you start typing the first few chars and hit ctrl-space, and it
gives you a drop-down of potential completions.

Some Other things it does (full list is athttp://www.sigasi.com/featurelist):
* Autocomplete templates for "if", "process", and the rest.
Nice, but not a big deal, for me anyway.

Ahh, I'd thought you'd said automating boilerplate code was on your
list - sorry.

* Line alignment (so all your : and <= and => line up nicely)
That would be nice.

Much more than "nice" to me - esp. if others see your code - nothing
like bad formatting to make people wonder whether the logic is
similarly wiggly!

<snip>

I'll be finished with my VHDL coding in another week or two and won't
want to spend time with a VHDL tool. I am going to look into a design
using a multiprocessor chip that is micro power or nano power or pico
power, what ever it is being called these days. Idle state is 100
micro watts per processor with 144 processors on the chip. Running
full out they use 4.5 mW at over 500 MIPS!

Sounds fun - that sounds like a greenarray?

Cheers,
Martin
--
martin.j.thompson@trw.com
TRW Conekt - Consultancy in Engineering, Knowledge and Technology
http://www.conekt.co.uk/capabilities/39-electronic-hardware

 

[rickman]

On Dec 1, 8:29 am, Martin Thompson <martin.j.thomp...@trw.com> wrote:

rickman <gnu...@gmail.com> writes:
On Nov 30, 8:18 am, Martin Thompson <martin.j.thomp...@trw.com> wrote:

This is better than a global (ie multi-file) replace because when you
change "write" on one entity to "write_n" you don't want every entity
with a "write" pin changing! And heaven help you changing rd to wr -
hope the characters 'rd' don't appear in any other pins anywhere else
(like the "one_third" pin of your "divide_by_three" entity

That's not a big deal.  My editor, and I suspect many others, has a
check box on the search that says "only full word match" so that
write_n won't match a write search.

No, my point was if you have "write" on another entity you don;t want
that one changing as well.

Yes, if "only full word match" is used, then "write_n" won't match a
"write" search and replace so only "write" will change.

How much time do you spend copying "columns" from entities and
changing : to => in port maps to instance a component? That used to
drive me demented in CW.

That's the part I have regex lines to handle.  I have to tweek the
last line of the port list so it has a terminator, apply the regex,
tweek the terminator back and adjust the column alignments (manually,
I am a little OCD about this part).  

All stuff you'd rather not do, right?

My point is it's not much of a problem. I can live with a regex
replace. It is not on the list of things I want to switch editors to
prevent doing.

Then

That's the key word  After doing some stuff...

I have everything perfectly formatted and even the comments within
the port list are transferred.  After a dozen or so passes with the
regex it was tweeked enough to cover all the weird cases such as
including "_" in the names, etc.  I have one regex to generate the
instantiation port map and another to generate signal declarations.

OK, you've gotten further configurating CW than I ever did

I'd be happy to share my regex strings ;-) The limitation of CW is
that you can't hard code these replace strings into a button... that I
have been able to figure out. There are some real programming
capabilities, but I haven't learned it all and the product is no
longer supported or even sold I believe.

I may spend a little more time with it so it will write the code for
the entity body given a customer's description of the problem.  ;^)

Good plan, let us know when you've got that sorted, we could all use
it

But you'd have to use CW! Or if I get a little more familiarity with
the tool, I could code it in Win32Forth... ;^)

It has been very seldom that I have seen a tool which I decided I
needed enough to drop an old tool and pick up the new.

Me too. Migrating from CW to Emacs was the last time I recall doing
it. And that was a *serious* learning curve, but still worth it.
Sigasi is way easier IMHO.

I only have two problems with Sigasi.  One is spending time with it to
be convinced that it is better in some so far, unidentified way.  

Well, with respect, I've indentified a number of ways it's better than
raw Codewright.  The fact that you've overcome those was unknown to
me.  I see below that I've also identified some things you *would* like....

The other is that it is commercial software with an up front cost
and I assume a recurring cost.  Being a small shop I don't often pay
for tools unless I am absolutely convinced I need them.  Notice I
said "need", not "would like" or "nice to have" or even "would be
more productive if".  When I am working the VHDL I bang code all day
long.  But I don't do it all the time.
I also spend time designing the boards, writing test code, specs,
docs and even conversing with customers... oh yeah, and that
slightly important part, looking for customers.  

This I also understand - I'd like to use some of the c-to-gates tools,
but I don't want to pay for a whole year's worth of flat-out license
when I'd use it maybe 25% of the year.

Emacs also suits me nicely license-wise!

I'm not inclined to spend a kilobuck on something that will give me
a minor improvement in what I do maybe 10% of the time.  Then on top
of it all, a tool that requires support from a company is already a
rung lower on the ladder

Sorry, which ladder are you talking about?

Sorry, the evaluation of the tool ladder. I don't know how this tool
is licensed, but I am very down on commercial tools because of the
licensing issues and the seeming lack of support. That automatically
puts a commercial tool below any open source tool when I am evaluating
them. So the commercial tool has to be significantly better for me to
want it.

than a tool that is either static because it is already
unsupported (Codewright and Eudora) or open source and supported by
an active community.  The most useful tools I have are (other than
the FPGA tools that I have no choice with) are one of those two
categories.  The biggest bane to my existence, tool- wise, is the
licensed tools I have to keep running, but only weekdays 9-5.  I am
having a problem with the Lattice tools right now that I am having
to go through support (or around actually) to resolve.

Agreed - licensed tools can cause a lot of pain!

about autocompletion

Is this the way it works in Sigasi with signal names?  If you are
typing a signal name as the first thing on a line, does it add the
assignment operator?  What happens the first time you type an
assignment to a signal or variable?  Does it add a declaration for the
name?

IIRC you start typing the first few chars and hit ctrl-space, and it
gives you a drop-down of potential completions.

And those completions include both keywords as well as your signal/
variable names? If this feature works well enough I might consider
Sigasi. Especially if it could be used for other languages than just
VHDL. Is the VHDL aspect hard coded? I expect it will also support
Verilog, but what about generic languages? Does it have a means of
setting it up for an arbitrary language like CW does?

Some Other things it does (full list is athttp://www.sigasi.com/featurelist):
* Autocomplete templates for "if", "process", and the rest.
Nice, but not a big deal, for me anyway.

Ahh, I'd thought you'd said automating boilerplate code was on your
list - sorry.

It is, but I guess I'm saying this is not a big enough feature to move
to a new tool for. I may have some down time in the new year. Maybe
I'll give the Sigasi tool a try. You are starting to convince me.
But learning curves are a PITA and if I have to pay for the tool, the
curve has to be short and the reward has to be big!

* Line alignment (so all your : and <= and => line up nicely)
That would be nice.

Much more than "nice" to me - esp. if others see your code - nothing
like bad formatting to make people wonder whether the logic is
similarly wiggly!

Line indentation is a bigger hassle for me. I can line up the <and : parts without too much trouble. But I have to admit if you
bring a number of these little features together it might be worth
something.

I'll be finished with my VHDL coding in another week or two and won't
want to spend time with a VHDL tool.  I am going to look into a design
using a multiprocessor chip that is micro power or nano power or pico
power, what ever it is being called these days.  Idle state is 100
micro watts per processor with 144 processors on the chip.  Running
full out they use 4.5 mW at over 500 MIPS!  

Sounds fun - that sounds like a greenarray?

Give the man a cupie doll! In the Spring they will have a 144
processor part with five ADC and DAC and have released a data sheet
for the GA4 (4 processors) with no device release date. But Chuck's
blog indicates they have had prototype GA4 and GA32 devices for some
time. On the other hand, Chuck's blog seems to show a company that is
on the low end of struggling. I have no idea if they will manage to
stay solvent long enough to ship product.

I am considering designing a Radio Controlled Clock using a GA4 which
would run off of two AAA cells for over a year. That should be a good
demo of the low power capabilities, no? Would that make you believe
that the chip can be pretty low power? The interesting part is that
this can be done with the GA144 nearly as easily as the GA4, you just
pay more to have 143 processors sitting idle 100% of the time and 1
processor idle 95% of the time.

Rick

 

[Jan Decaluwe]

rickman wrote:

Yes, if "only full word match" is used, then "write_n" won't match a
"write" search and replace so only "write" will change.

It seems that you do not appreciate the difference between Rename
and global search and replace yet.

The same identifier may refer to a lot of different objects in
a design. Rename is based on object identify, not identifier identity.
This makes it intelligent and safe.

1 minute screencast on Rename (no sound as yet):

http://www.sigasi.com/screencast/rename

And those completions include both keywords as well as your signal/
variable names? If this feature works well enough I might consider
Sigasi. Especially if it could be used for other languages than just
VHDL. Is the VHDL aspect hard coded? I expect it will also support
Verilog, but what about generic languages? Does it have a means of
setting it up for an arbitrary language like CW does?

Sigasi HDT is available as a plugin to a standard Eclipse installation,
which means that it plays well with thousands of open-source and
commercial plugins from other parties. More info:

http://www.sigasi.com/download

Sigasi HDT itself has no Verilog support yet.

Jan

--
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Python as a HDL: http://www.myhdl.org
VHDL development, the modern way: http://www.sigasi.com
Analog design automation: http://www.mephisto-da.com
World-class digital design: http://www.easics.com