Bootstrap help (PD-TIA)

[George Herold]

OK Before getting to the question a picture and good news.
https://www.dropbox.com/s/i4r7xw5ra2bzasv/PD-preamp.JPG?dl=0
I've replaced the rotary switch with some toggles. These NKK toggle
switches have ~0.25 pF between the pins, which is a bit less than
the C&K toggles (~0.38 pF) This allowed me to get the ~1 MHz BW
I need (at R_tia= 100k ohm).

So today I wanted to investigate the bootstrap (BS). I built this simple circuit
https://www.dropbox.com/s/on3w4bgytpmb4o3/BS-test.JPG?dl=0
And measured the step response and bandwidth (BW).

With no BS, the step response had a 1.2 usec TC and ~140 kHz BW,
all in agreement with ~120 pF of PD capacitance and 10 k ohm.

With the opamp BS, Step response had some uglies, ~400n sec (two pole)
and ~600 kHz BW. PD capacitance reduced by a factor of four.
(Everything I read says I can do better.)

The Jfet bootstrap was less good, TC = 500 nsec (single pole)
and ~400 kHz BW.

Finally the npn (2n3904) was nice and snappy, ~160 nsec rise times
and 2.6 MHz BW! But I'm stealing a bunch of the photocurrent.
(I_col ~3mA, I_b ~ 10 uA) So not practical.

So any ideas?
A darlington?
How do I pick a better Jfet?

TIA

George H.

 

[Winfield Hill]

George Herold wrote...

The Jfet bootstrap was less good, TC = 500 nsec
(single pole) and ~400 kHz BW.

Finally the npn (2n3904) was nice and snappy,
~160 nsec rise times and 2.6 MHz BW! But I'm
stealing a bunch of the photocurrent.

I use a JFET with BJT, e.g., AoE3, Figure 8.83,
page 548, and Figure 4x.25. Or see my RIS-617
designs, with my preferred PNP, see schematics,

https://www.dropbox.com/s/jdlxdesycw695sb/RIS-617E_A-D%285%29_E-versions%285%29_12pgs.pdf?dl=1


--
Thanks,
- Win

 

[Phil Hobbs]

On 9/25/19 2:30 PM, George Herold wrote:

OK Before getting to the question a picture and good news.
https://www.dropbox.com/s/i4r7xw5ra2bzasv/PD-preamp.JPG?dl=0
I've replaced the rotary switch with some toggles. These NKK toggle
switches have ~0.25 pF between the pins, which is a bit less than
the C&K toggles (~0.38 pF) This allowed me to get the ~1 MHz BW
I need (at R_tia= 100k ohm).

So today I wanted to investigate the bootstrap (BS). I built this simple circuit
https://www.dropbox.com/s/on3w4bgytpmb4o3/BS-test.JPG?dl=0
And measured the step response and bandwidth (BW).

With no BS, the step response had a 1.2 usec TC and ~140 kHz BW,
all in agreement with ~120 pF of PD capacitance and 10 k ohm.

With the opamp BS, Step response had some uglies, ~400n sec (two pole)
and ~600 kHz BW. PD capacitance reduced by a factor of four.
(Everything I read says I can do better.)

The Jfet bootstrap was less good, TC = 500 nsec (single pole)
and ~400 kHz BW.

Finally the npn (2n3904) was nice and snappy, ~160 nsec rise times
and 2.6 MHz BW! But I'm stealing a bunch of the photocurrent.
(I_col ~3mA, I_b ~ 10 uA) So not practical.

So any ideas?
A darlington?
How do I pick a better Jfet?

Sounds like your bootstrap's output impedance is too high.

If you don't care too much about getting the lowest noise, you can make
a Darlington-style bootstrap by putting a CPH3910 in front of a
3904-type transistor.

I often use a JFET/PNP series-feedback pair for this. You put about 600
ohms in series with the JFET's drain, and wrap a PNP around it, as in
AoE3 Fig 2.92 with R5 = 0, Q1 = CPH3910, and Q2 = BFT92. (The BFT92 is
EOL, but I have a couple of reels.) The idea is that Q2 tries to keep
Q1's drain current constant. It works best when Q2 isn't running much
quiescent collector current, maybe 2 mA. (It's different from a Sziklai
pair in that the first stage takes most of the current.)


It might need some tweaking to get it to be stable with a much slower
PNP--maybe a bead in the base. You can get fancier, e.g. by putting a
diode in series with the drain and sense resistor, and a parallel RC in
the emitter, and wring a few more decibels out of it.

The other thing that helps a lot is to use a stiff tail current source.

We sell and license a proprietary version of the White cathode follower
idea--see <https://hobbs-eo.com>.

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC / Hobbs ElectroOptics
Optics, Electro-optics, Photonics, Analog Electronics
Briarcliff Manor NY 10510

http://electrooptical.net
http://hobbs-eo.com

 

[George Herold]

On Wednesday, September 25, 2019 at 3:36:48 PM UTC-4, Winfield Hill wrote:

George Herold wrote...

The Jfet bootstrap was less good, TC = 500 nsec
(single pole) and ~400 kHz BW.

Finally the npn (2n3904) was nice and snappy,
~160 nsec rise times and 2.6 MHz BW! But I'm
stealing a bunch of the photocurrent.

I use a JFET with BJT, e.g., AoE3, Figure 8.83,
page 548, and Figure 4x.25. Or see my RIS-617
designs, with my preferred PNP, see schematics,

Right thanks. I saw that but didn't know why it was there.

https://www.dropbox.com/s/jdlxdesycw695sb/RIS-617E_A-D%285%29_E-versions%285%29_12pgs.pdf?dl=1

Ahh and look an inductor in the PD bias line. :^)

George H.

--
Thanks,
- Win

 

[George Herold]

On Wednesday, September 25, 2019 at 3:27:09 PM UTC-4, Phil Hobbs wrote:

On 9/25/19 2:30 PM, George Herold wrote:
OK Before getting to the question a picture and good news.
https://www.dropbox.com/s/i4r7xw5ra2bzasv/PD-preamp.JPG?dl=0
I've replaced the rotary switch with some toggles. These NKK toggle
switches have ~0.25 pF between the pins, which is a bit less than
the C&K toggles (~0.38 pF) This allowed me to get the ~1 MHz BW
I need (at R_tia= 100k ohm).

So today I wanted to investigate the bootstrap (BS). I built this simple circuit
https://www.dropbox.com/s/on3w4bgytpmb4o3/BS-test.JPG?dl=0
And measured the step response and bandwidth (BW).

With no BS, the step response had a 1.2 usec TC and ~140 kHz BW,
all in agreement with ~120 pF of PD capacitance and 10 k ohm.

With the opamp BS, Step response had some uglies, ~400n sec (two pole)
and ~600 kHz BW. PD capacitance reduced by a factor of four.
(Everything I read says I can do better.)

The Jfet bootstrap was less good, TC = 500 nsec (single pole)
and ~400 kHz BW.

Finally the npn (2n3904) was nice and snappy, ~160 nsec rise times
and 2.6 MHz BW! But I'm stealing a bunch of the photocurrent.
(I_col ~3mA, I_b ~ 10 uA) So not practical.

So any ideas?
A darlington?
How do I pick a better Jfet?

Sounds like your bootstrap's output impedance is too high.

I think that's right. I had to reduce the value of the bias resistor
between PD anode and negative power supply...

If you don't care too much about getting the lowest noise, you can make
a Darlington-style bootstrap by putting a CPH3910 in front of a
3904-type transistor.
OK thanks I can give that a try. (I don't know enough about jfets...)

I often use a JFET/PNP series-feedback pair for this. You put about 600
ohms in series with the JFET's drain, and wrap a PNP around it, as in
AoE3 Fig 2.92 with R5 = 0, Q1 = CPH3910, and Q2 = BFT92. (The BFT92 is
EOL, but I have a couple of reels.) The idea is that Q2 tries to keep
Q1's drain current constant. It works best when Q2 isn't running much
quiescent collector current, maybe 2 mA. (It's different from a Sziklai
pair in that the first stage takes most of the current.)

Hmm sounds trickier, I'm not sure I understand it... which always makes
it harder to get working. :^)

It might need some tweaking to get it to be stable with a much slower
PNP--maybe a bead in the base. You can get fancier, e.g. by putting a
diode in series with the drain and sense resistor, and a parallel RC in
the emitter, and wring a few more decibels out of it.

The other thing that helps a lot is to use a stiff tail current source.

We sell and license a proprietary version of the White cathode follower
idea--see <https://hobbs-eo.com>.
Nice... I'm thinking out of my price range.

Say, maybe if I put a bit of inductance in the line between PD anode and the
negative bias supply? That may reduce the loading on my bootstrap.

Hey thanks, I've got a few things to try.

George H.

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC / Hobbs ElectroOptics
Optics, Electro-optics, Photonics, Analog Electronics
Briarcliff Manor NY 10510

http://electrooptical.net
http://hobbs-eo.com

 

[George Herold]

On Wednesday, September 25, 2019 at 4:26:31 PM UTC-4, George Herold wrote:

On Wednesday, September 25, 2019 at 3:36:48 PM UTC-4, Winfield Hill wrote:
George Herold wrote...

The Jfet bootstrap was less good, TC = 500 nsec
(single pole) and ~400 kHz BW.

Finally the npn (2n3904) was nice and snappy,
~160 nsec rise times and 2.6 MHz BW! But I'm
stealing a bunch of the photocurrent.

I use a JFET with BJT, e.g., AoE3, Figure 8.83,
page 548, and Figure 4x.25. Or see my RIS-617
designs, with my preferred PNP, see schematics,

Right thanks. I saw that but didn't know why it was there.

https://www.dropbox.com/s/jdlxdesycw695sb/RIS-617E_A-D%285%29_E-versions%285%29_12pgs.pdf?dl=1

Ahh and look an inductor in the PD bias line. :^)

George H.


--
Thanks,
- Win

Oh dear, this 'final' project just withered on the vine.
I was fired today... (expected.)
I'm off for a week at cape cod, looking after my mother-in-law
who has some crappy neurological disease. And then I need a new
gig.

George H.

 

[John Larkin]

On 25 Sep 2019 12:36:30 -0700, Winfield Hill <winfieldhill@yahoo.com>
wrote:

George Herold wrote...

The Jfet bootstrap was less good, TC = 500 nsec
(single pole) and ~400 kHz BW.

Finally the npn (2n3904) was nice and snappy,
~160 nsec rise times and 2.6 MHz BW! But I'm
stealing a bunch of the photocurrent.

I use a JFET with BJT, e.g., AoE3, Figure 8.83,
page 548, and Figure 4x.25. Or see my RIS-617
designs, with my preferred PNP, see schematics,

https://www.dropbox.com/s/jdlxdesycw695sb/RIS-617E_A-D%285%29_E-versions%285%29_12pgs.pdf?dl=1

Bootstrapping a photodiode over a cable gets interesting as the cable
gets longer. I had to explain that to a customer who elected to not
manage his cabling to his photodiode.

 

[Phil Hobbs]

On 9/26/19 2:39 PM, George Herold wrote:

On Wednesday, September 25, 2019 at 4:26:31 PM UTC-4, George Herold wrote:
On Wednesday, September 25, 2019 at 3:36:48 PM UTC-4, Winfield Hill wrote:
George Herold wrote...

The Jfet bootstrap was less good, TC = 500 nsec
(single pole) and ~400 kHz BW.

Finally the npn (2n3904) was nice and snappy,
~160 nsec rise times and 2.6 MHz BW! But I'm
stealing a bunch of the photocurrent.

I use a JFET with BJT, e.g., AoE3, Figure 8.83,
page 548, and Figure 4x.25. Or see my RIS-617
designs, with my preferred PNP, see schematics,

Right thanks. I saw that but didn't know why it was there.

https://www.dropbox.com/s/jdlxdesycw695sb/RIS-617E_A-D%285%29_E-versions%285%29_12pgs.pdf?dl=1

Ahh and look an inductor in the PD bias line. :^)

George H.


--
Thanks,
- Win

Oh dear, this 'final' project just withered on the vine.
I was fired today... (expected.)
I'm off for a week at cape cod, looking after my mother-in-law
who has some crappy neurological disease. And then I need a new
gig.

George H.

Huge fun for all concerned.

Send me your home email--I'm happy to be a reference.

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC / Hobbs ElectroOptics
Optics, Electro-optics, Photonics, Analog Electronics
Briarcliff Manor NY 10510

http://electrooptical.net
http://hobbs-eo.com

 

[George Herold]

On Thursday, September 26, 2019 at 3:04:32 PM UTC-4, John Larkin wrote:

On 25 Sep 2019 12:36:30 -0700, Winfield Hill <winfieldhill@yahoo.com
wrote:

George Herold wrote...

The Jfet bootstrap was less good, TC = 500 nsec
(single pole) and ~400 kHz BW.

Finally the npn (2n3904) was nice and snappy,
~160 nsec rise times and 2.6 MHz BW! But I'm
stealing a bunch of the photocurrent.

I use a JFET with BJT, e.g., AoE3, Figure 8.83,
page 548, and Figure 4x.25. Or see my RIS-617
designs, with my preferred PNP, see schematics,

https://www.dropbox.com/s/jdlxdesycw695sb/RIS-617E_A-D%285%29_E-versions%285%29_12pgs.pdf?dl=1

Bootstrapping a photodiode over a cable gets interesting as the cable
gets longer. I had to explain that to a customer who elected to not
manage his cabling to his photodiode.

My first bootstrap was the noise of a 100k ohm resistor,
down ~2 feet of cable and probe, to 77 K.

George H.

 

[George Herold]

On Thursday, September 26, 2019 at 4:22:14 PM UTC-4, Phil Hobbs wrote:

On 9/26/19 2:39 PM, George Herold wrote:
On Wednesday, September 25, 2019 at 4:26:31 PM UTC-4, George Herold wrote:
On Wednesday, September 25, 2019 at 3:36:48 PM UTC-4, Winfield Hill wrote:
George Herold wrote...

The Jfet bootstrap was less good, TC = 500 nsec
(single pole) and ~400 kHz BW.

Finally the npn (2n3904) was nice and snappy,
~160 nsec rise times and 2.6 MHz BW! But I'm
stealing a bunch of the photocurrent.

I use a JFET with BJT, e.g., AoE3, Figure 8.83,
page 548, and Figure 4x.25. Or see my RIS-617
designs, with my preferred PNP, see schematics,

Right thanks. I saw that but didn't know why it was there.

https://www.dropbox.com/s/jdlxdesycw695sb/RIS-617E_A-D%285%29_E-versions%285%29_12pgs.pdf?dl=1

Ahh and look an inductor in the PD bias line. :^)

George H.


--
Thanks,
- Win

Oh dear, this 'final' project just withered on the vine.
I was fired today... (expected.)
I'm off for a week at cape cod, looking after my mother-in-law
who has some crappy neurological disease. And then I need a new
gig.

George H.


Huge fun for all concerned.

Send me your home email--I'm happy to be a reference.

Cheers

Phil Hobbs

Thanks, SED is my best/favorite collaborator currently.
Which is nice, but also stinks.

ggherold@gmail.com

I'm going to cape cod for a week.
George stares at ocean and thinks about life,
nothing new. :^)

GH

--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC / Hobbs ElectroOptics
Optics, Electro-optics, Photonics, Analog Electronics
Briarcliff Manor NY 10510

http://electrooptical.net
http://hobbs-eo.com

 

[Winfield Hill]

George Herold wrote...

I was fired today... (expected.)

Brilliant idea on their part ... NOT !!!
But a chance for you to branch out anew.
I'll be glad to give a good recommendation.


--
Thanks,
- Win

 

[Phil Hobbs]

On 9/26/19 4:40 PM, George Herold wrote:

On Thursday, September 26, 2019 at 4:22:14 PM UTC-4, Phil Hobbs wrote:
On 9/26/19 2:39 PM, George Herold wrote:
On Wednesday, September 25, 2019 at 4:26:31 PM UTC-4, George Herold wrote:
On Wednesday, September 25, 2019 at 3:36:48 PM UTC-4, Winfield Hill wrote:
George Herold wrote...

The Jfet bootstrap was less good, TC = 500 nsec
(single pole) and ~400 kHz BW.

Finally the npn (2n3904) was nice and snappy,
~160 nsec rise times and 2.6 MHz BW! But I'm
stealing a bunch of the photocurrent.

I use a JFET with BJT, e.g., AoE3, Figure 8.83,
page 548, and Figure 4x.25. Or see my RIS-617
designs, with my preferred PNP, see schematics,

Right thanks. I saw that but didn't know why it was there.

https://www.dropbox.com/s/jdlxdesycw695sb/RIS-617E_A-D%285%29_E-versions%285%29_12pgs.pdf?dl=1

Ahh and look an inductor in the PD bias line. :^)

George H.


--
Thanks,
- Win

Oh dear, this 'final' project just withered on the vine.
I was fired today... (expected.)
I'm off for a week at cape cod, looking after my mother-in-law
who has some crappy neurological disease. And then I need a new
gig.

George H.


Huge fun for all concerned.

Send me your home email--I'm happy to be a reference.

Cheers

Phil Hobbs
Thanks, SED is my best/favorite collaborator currently.
Which is nice, but also stinks.

ggherold@gmail.com

I'm going to cape cod for a week.
George stares at ocean and thinks about life,
nothing new. :^)

GH

Next time go to Cape May, so you can swing by Burg Frankenstein here for
a beer en route.

Cheers

Phil Hobbs


--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC / Hobbs ElectroOptics
Optics, Electro-optics, Photonics, Analog Electronics
Briarcliff Manor NY 10510

http://electrooptical.net
http://hobbs-eo.com

 

[John Larkin]

On Thu, 26 Sep 2019 12:49:51 -0700 (PDT), George Herold
<gherold@teachspin.com> wrote:

On Thursday, September 26, 2019 at 3:04:32 PM UTC-4, John Larkin wrote:
On 25 Sep 2019 12:36:30 -0700, Winfield Hill <winfieldhill@yahoo.com
wrote:

George Herold wrote...

The Jfet bootstrap was less good, TC = 500 nsec
(single pole) and ~400 kHz BW.

Finally the npn (2n3904) was nice and snappy,
~160 nsec rise times and 2.6 MHz BW! But I'm
stealing a bunch of the photocurrent.

I use a JFET with BJT, e.g., AoE3, Figure 8.83,
page 548, and Figure 4x.25. Or see my RIS-617
designs, with my preferred PNP, see schematics,

https://www.dropbox.com/s/jdlxdesycw695sb/RIS-617E_A-D%285%29_E-versions%285%29_12pgs.pdf?dl=1

Bootstrapping a photodiode over a cable gets interesting as the cable
gets longer. I had to explain that to a customer who elected to not
manage his cabling to his photodiode.

My first bootstrap was the noise of a 100k ohm resistor,
down ~2 feet of cable and probe, to 77 K.

George H.

Works fine as long as the cable is short compared to system rise time.

That particular customer liked to poke loose photodiode wires in a big
pipe at random.

 

[piglet]

On 26/09/2019 7:39 pm, George Herold wrote:

On Wednesday, September 25, 2019 at 4:26:31 PM UTC-4, George Herold wrote:
On Wednesday, September 25, 2019 at 3:36:48 PM UTC-4, Winfield Hill wrote:
George Herold wrote...

The Jfet bootstrap was less good, TC = 500 nsec
(single pole) and ~400 kHz BW.

Finally the npn (2n3904) was nice and snappy,
~160 nsec rise times and 2.6 MHz BW! But I'm
stealing a bunch of the photocurrent.

I use a JFET with BJT, e.g., AoE3, Figure 8.83,
page 548, and Figure 4x.25. Or see my RIS-617
designs, with my preferred PNP, see schematics,

Right thanks. I saw that but didn't know why it was there.

https://www.dropbox.com/s/jdlxdesycw695sb/RIS-617E_A-D%285%29_E-versions%285%29_12pgs.pdf?dl=1

Ahh and look an inductor in the PD bias line. :^)

George H.


--
Thanks,
- Win

Oh dear, this 'final' project just withered on the vine.
I was fired today... (expected.)
I'm off for a week at cape cod, looking after my mother-in-law
who has some crappy neurological disease. And then I need a new
gig.

George H.

Hi George, similar feeling here too, after years of plowing along
steadily this seems to be a year of change.

piglet

 

[George Herold]

On Thursday, September 26, 2019 at 4:54:32 PM UTC-4, Phil Hobbs wrote:

On 9/26/19 4:40 PM, George Herold wrote:
On Thursday, September 26, 2019 at 4:22:14 PM UTC-4, Phil Hobbs wrote:
On 9/26/19 2:39 PM, George Herold wrote:
On Wednesday, September 25, 2019 at 4:26:31 PM UTC-4, George Herold wrote:
On Wednesday, September 25, 2019 at 3:36:48 PM UTC-4, Winfield Hill wrote:
George Herold wrote...

The Jfet bootstrap was less good, TC = 500 nsec
(single pole) and ~400 kHz BW.

Finally the npn (2n3904) was nice and snappy,
~160 nsec rise times and 2.6 MHz BW! But I'm
stealing a bunch of the photocurrent.

I use a JFET with BJT, e.g., AoE3, Figure 8.83,
page 548, and Figure 4x.25. Or see my RIS-617
designs, with my preferred PNP, see schematics,

Right thanks. I saw that but didn't know why it was there.

https://www.dropbox.com/s/jdlxdesycw695sb/RIS-617E_A-D%285%29_E-versions%285%29_12pgs.pdf?dl=1

Ahh and look an inductor in the PD bias line. :^)

George H.


--
Thanks,
- Win

Oh dear, this 'final' project just withered on the vine.
I was fired today... (expected.)
I'm off for a week at cape cod, looking after my mother-in-law
who has some crappy neurological disease. And then I need a new
gig.

George H.


Huge fun for all concerned.

Send me your home email--I'm happy to be a reference.

Cheers

Phil Hobbs
Thanks, SED is my best/favorite collaborator currently.
Which is nice, but also stinks.

ggherold@gmail.com

I'm going to cape cod for a week.
George stares at ocean and thinks about life,
nothing new. :^)

GH

Next time go to Cape May, so you can swing by Burg Frankenstein here for
a beer en route.

Thanks Phil, If it wasn't such a long drive I'd swing by on my way home.

George H.

Cheers

Phil Hobbs


--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC / Hobbs ElectroOptics
Optics, Electro-optics, Photonics, Analog Electronics
Briarcliff Manor NY 10510

http://electrooptical.net
http://hobbs-eo.com

 

[George Herold]

On Thursday, September 26, 2019 at 5:48:29 PM UTC-4, piglet wrote:

On 26/09/2019 7:39 pm, George Herold wrote:
On Wednesday, September 25, 2019 at 4:26:31 PM UTC-4, George Herold wrote:
On Wednesday, September 25, 2019 at 3:36:48 PM UTC-4, Winfield Hill wrote:
George Herold wrote...

The Jfet bootstrap was less good, TC = 500 nsec
(single pole) and ~400 kHz BW.

Finally the npn (2n3904) was nice and snappy,
~160 nsec rise times and 2.6 MHz BW! But I'm
stealing a bunch of the photocurrent.

I use a JFET with BJT, e.g., AoE3, Figure 8.83,
page 548, and Figure 4x.25. Or see my RIS-617
designs, with my preferred PNP, see schematics,

Right thanks. I saw that but didn't know why it was there.

https://www.dropbox.com/s/jdlxdesycw695sb/RIS-617E_A-D%285%29_E-versions%285%29_12pgs.pdf?dl=1

Ahh and look an inductor in the PD bias line. :^)

George H.


--
Thanks,
- Win

Oh dear, this 'final' project just withered on the vine.
I was fired today... (expected.)
I'm off for a week at cape cod, looking after my mother-in-law
who has some crappy neurological disease. And then I need a new
gig.

George H.


Hi George, similar feeling here too, after years of plowing along
steadily this seems to be a year of change.

piglet

Hi piglet, Come on in, the water's fine. :^)

George H.

 

[George Herold]

On Thursday, September 26, 2019 at 5:35:55 PM UTC-4, Winfield Hill wrote:

George Herold wrote...

I was fired today... (expected.)

Brilliant idea on their part ... NOT !!!
But a chance for you to branch out anew.

Yeah, mostly I feel relieved. I torpedoed this one new hire,
and so I've been expecting it.

Let me share this piece of the severance letter.

"That Mr. Herold agrees not to share plans, designs, electronic
circuits or any other Teachspin property with any commercial company or
educational institution for a period of 20 years."

I have no idea what this means, but it seems crazy to sign on to such
terms. (Property would seem to imply any circuit scribble I've
done at work.)

I love the twenty years part. :^)

George H.

I'll be glad to give a good recommendation.


--
Thanks,
- Win

 

[Winfield Hill]

George Herold wrote...

"That Mr. Herold agrees not to share plans, designs,
electronic circuits or any other Teachspin property
with any commercial company or educational institution
for a period of 20 years."

The maximum term should be no more than 3 years.

But you SHOULD NOT sign such a vague document,
especially one calling out "electronic circuits".

If something is to be protected, the protected
item(s) need to be spelled out very clearly,
otherwise your entire engineering career can
be put at risk. For example, you know how to
design a specific high-performance amplifier.
Maybe they have one like that in a product,
maybe you designed it, maybe not. But you
should not be prevented from creating a similar,
or even nearly identical, design in the future.

The company has various educational products.
You can agree not to divulged relevant details
of those specific products. But say a product
has a circuit you're familiar with, an amplifier,
etc., that's part of your engineering toolkit, it
cannot be magically included with vague language.


--
Thanks,
- Win

 

On Sat, 28 Sep 2019 05:49:11 -0700 (PDT), George Herold
<gherold@teachspin.com> wrote:

On Thursday, September 26, 2019 at 5:35:55 PM UTC-4, Winfield Hill wrote:
George Herold wrote...

I was fired today... (expected.)

Brilliant idea on their part ... NOT !!!
But a chance for you to branch out anew.

Yeah, mostly I feel relieved. I torpedoed this one new hire,
and so I've been expecting it.

Let me share this piece of the severance letter.

"That Mr. Herold agrees not to share plans, designs, electronic
circuits or any other Teachspin property with any commercial company or
educational institution for a period of 20 years."

I have no idea what this means, but it seems crazy to sign on to such
terms. (Property would seem to imply any circuit scribble I've
done at work.)

I love the twenty years part. :^)

George H.

I'll be glad to give a good recommendation.


--
Thanks,
- Win

You can agree to not share accepted-definition trade secrets,
presumably in return for something of value to you. You have a legal
right to "practise your trade" which includes doing normal stuff.

I wouldn't sign anything like that unless a giant severance is
included.

I really enjoyed being fired. Got a nice fresh start on life.
Unemployment and severance financed some shopping around for six
months.

Maybe you can do some serious scientific instrumentation next, not the
educational things.




--

John Larkin Highland Technology, Inc

lunatic fringe electronics

 

[Tom Gardner]

On 28/09/19 13:49, George Herold wrote:

On Thursday, September 26, 2019 at 5:35:55 PM UTC-4, Winfield Hill wrote:
George Herold wrote...

I was fired today... (expected.)

Brilliant idea on their part ... NOT !!!
But a chance for you to branch out anew.

Yeah, mostly I feel relieved. I torpedoed this one new hire,
and so I've been expecting it.

Let me share this piece of the severance letter.

"That Mr. Herold agrees not to share plans, designs, electronic
circuits or any other Teachspin property with any commercial company or
educational institution for a period of 20 years."

I have no idea what this means, but it seems crazy to sign on to such
terms. (Property would seem to imply any circuit scribble I've
done at work.)

What you think it implies is, of course, irrelevant!

As written, it can easily be interpreted to mean that
plans/designs/circuits you develop after leaving cannot
be shared with your new clients. (Ridiculous, maybe
not enforceable).

Ditto Teachspin property, but /that/ isn't ridiculous.

In the UK you could amend that letter to be something
to your liking, sign and date the amendment, and
return that.

Or, as I once did w.r.t. a patent application, edit
the PDF to insert a word such as "reasonable" in the
relevant point.


> I love the twenty years part. :^)

Restraint of trade.