Bit reversing

[Mad I.D.]

....
a : in std_logic_vector(3 downto 0);
....
signal abr : std_logic_vector (3 downto 0);

abr <= a(0)&a(1)&a(2)&a(3); --OK
abr <= a(0 to 3); --NOT OK

Why not OK? Thank you !

By the way, br for bit reversed

 

[Ken Cecka]

Mad I.D. wrote:

...
a : in std_logic_vector(3 downto 0);
...
signal abr : std_logic_vector (3 downto 0);

abr <= a(0)&a(1)&a(2)&a(3); --OK
abr <= a(0 to 3); --NOT OK

Why not OK? Thank you !

By the way, br for bit reversed

Not sure I can answer the why - that's just how the language works. Up vectors and down vectors are different types and you can't mix-and-match syntax.

You can automate the reversal with a function though:

FUNCTION reverse(a : IN STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR IS
VARIABLE result : STD_LOGIC_VECTOR(a'RANGE);
ALIAS aa : STD_LOGIC_VECTOR(a'REVERSE_RANGE) IS a;
BEGIN
FOR i IN aa'RANGE LOOP
result(i) := aa(i);
END LOOP;
RETURN result;
END;

....

abr <= reverse(a);

Ken

 

[Jim Lewis]

Mad I.D. wrote:

...
a : in std_logic_vector(3 downto 0);
...
signal abr : std_logic_vector (3 downto 0);

abr <= a(0)&a(1)&a(2)&a(3); --OK
abr <= a(0 to 3); --NOT OK

Why not OK? Thank you !

By the way, br for bit reversed

It is a safety check built into the language.

Does anyone reverse bits enough to justify
adding an operator to do it? I don't.

Best,
Jim
--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis SynthWorks VHDL Training http://www.synthworks.com

A bird in the hand may be worth two in the bush,
but it sure makes it hard to type.

 

[Jonathan Bromley]

On Tue, 10 Feb 2009 09:17:45 -0800, Jim Lewis wrote:

Does anyone reverse bits enough to justify
adding an operator to do it?

FFT algorithms need a bit-reverse function.
That's the only place I've ever met the need.

However, SystemVerilog seems to think you need it.
Suppose ABCDEFGH is an 8-bit number, with one letter
standing for each bit, and suppose we've stored
that number in variable v. Then

{ << { v } } yields HGFEDCBA (simple bit reverse)
{ << 2 { v } } yields GHEFCDAB (reverse in 2-bit groups)
{ << 4 { v } } yields EFGHABCD (reverse in 4-bit groups)
{ << { { << 4 { v } } } } yields DCBAHGFE (reverse each 4-bit group)

How cool is that? ;-)

I have already made public my disappointment that
SystemVerilog lacks a operator....
--
Jonathan Bromley, Consultant

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