basic question about data types

M

Martin Sauer

Guest
Hi,

I have some basic question about data types in vhdl. I hope you can give
me an answer. Which library should I use in new designs (numeric_std or
std_logic_unsigned)? The unsigned type is a vector type?

Thank your for your answer.

bye

martin sauer
 
Hi,

I have an example:

In my VHDL code I have two unsigned signals

signal sDataR : unsigned (9 downto 0);
signal sR : unsigned (1 downto 0);

I want to add bit 1 of sR to sDataR. sDataR + sR(1) doesn't work. I will
get the following error:

ERROR: cannot convert type std_ulogic to type unsigned

How can I add one bit of an unsigned signal to another unsigned signal?

Thank you for your answer.

bye

martin sauer

Martin Sauer schrieb:
Hi,

I have some basic question about data types in vhdl. I hope you can give
me an answer. Which library should I use in new designs (numeric_std or
std_logic_unsigned)? The unsigned type is a vector type?

Thank your for your answer.

bye

martin sauer
Click to expand...
 
On Mon, 01 Dec 2008 09:00:49 +0100, Martin Sauer wrote:
[in two messages]

Which library should I use in new designs (numeric_std or
std_logic_unsigned)?
Click to expand...
Absolutely no argument about that: use numeric_std and
avoid std_logic_arith/[un]signed. numeric_std is
properly standardised, better-designed and more complete.

In my VHDL code I have two unsigned signals

signal sDataR : unsigned (9 downto 0);
signal sR : unsigned (1 downto 0);

I want to add bit 1 of sR to sDataR. sDataR + sR(1) doesn't work. I will
get the following error:

ERROR: cannot convert type std_ulogic to type unsigned

How can I add one bit of an unsigned signal to another unsigned signal?
Click to expand...
By making sure that both operands of "+" are unsigned vectors:

result := sDataR + sR(1 downto 1);

--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
 
On 1 Dec, 08:00, Martin Sauer <m...@displaign.de> wrote:
Hi,

I have an example:

In my VHDL code I have two unsigned signals

signal sDataR : unsigned (9 downto 0);
signal sR : unsigned (1 downto 0);

I want to add bit 1 of sR to sDataR. sDataR + sR(1) doesn't work. I will
get the following error:

ERROR: cannot convert type std_ulogic to type unsigned

How can I add one bit of an unsigned signal to another unsigned signal?

Thank you for your answer.

bye

martin sauer

Martin Sauer schrieb:

Hi,

I have some basic question about data types in vhdl. I hope you can give
me an answer. Which library should I use in new designs (numeric_std or
std_logic_unsigned)? The unsigned type is a vector type?

Thank your for your answer.

bye

martin sauer
Click to expand...
Definatly use numeric_std, because it is an actual IEEE standard,
std_logic_unsigned is not - it was origionally defined by Synopsys and
compiled (wrongly) in to the IEEE library. Different vendors implement
std_logic_unsigned differently, whereas the IEEE defined numeric_std.

As for your error, sR(1) is just a single bit, which is why you're
getting the problem. Addition has to be done on 2 unsigned numbers
that have the same length that match the result length. So, the best
way around your problem:

signal output : unsigned(10 downto 0); --addition output will be 1
bit bigger than largest input if you dont want overflow
...
output <= ('0' & sDataR) + resize(sR, output'length);
--'0' is concatenated the make sDataR 11 bits.

if you really wanted to add a single bit from sR then you have to use
a range to keep it as an unsigned type. Indexing just 1 returns a
std_ulogic, as you found.:

output <= ('0' & sDataR) + resize(sR(1 downto 1), output'length);
 
Martin Sauer wrote:
Hi,

I have an example:

In my VHDL code I have two unsigned signals

signal sDataR : unsigned (9 downto 0);
signal sR : unsigned (1 downto 0);

I want to add bit 1 of sR to sDataR. sDataR + sR(1) doesn't work. I will
get the following error:

ERROR: cannot convert type std_ulogic to type unsigned

How can I add one bit of an unsigned signal to another unsigned signal?

Thank you for your answer.

bye

martin sauer

Martin Sauer schrieb:
Hi,

I have some basic question about data types in vhdl. I hope you can give
me an answer. Which library should I use in new designs (numeric_std or
std_logic_unsigned)? The unsigned type is a vector type?
Click to expand...
operator '+' is defined in std_logic_unsigned for logic vectors. So
you can do it like

use ieee.std_logic_unsigned;
.....
srout <= sDataR + sR(1 downto 1);

It will certainly compile

Regards
 
Hi all,

thank you for your fast answer.

Now it works fine.

bye

martin sauer

olekk schrieb:
Martin Sauer wrote:
Hi,

I have an example:

In my VHDL code I have two unsigned signals

signal sDataR : unsigned (9 downto 0);
signal sR : unsigned (1 downto 0);

I want to add bit 1 of sR to sDataR. sDataR + sR(1) doesn't work. I will
get the following error:

ERROR: cannot convert type std_ulogic to type unsigned

How can I add one bit of an unsigned signal to another unsigned signal?

Thank you for your answer.

bye

martin sauer

Martin Sauer schrieb:
Hi,

I have some basic question about data types in vhdl. I hope you can give
me an answer. Which library should I use in new designs (numeric_std or
std_logic_unsigned)? The unsigned type is a vector type?


operator '+' is defined in std_logic_unsigned for logic vectors. So
you can do it like

use ieee.std_logic_unsigned;
....
srout <= sDataR + sR(1 downto 1);

It will certainly compile

Regards
Click to expand...
 
Martin Sauer a écrit :
Hi all,

thank you for your fast answer.

Now it works fine.
Click to expand...
The quick and ugly way. Read the other answers please. Please. I
*really* mean it.

Nicolas
 
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