Are there similar features in verilog as those of VHDL

Hi,
I have some VHDL knowledge. While I have to use Verilog now, I always think some VHDL features in Verilog. I do not find these answers for the two questions on line. Could you help me?

1. There is impure keyword in VHDL. Is there a similar, or substitute in Verilog?

2. There are signal and variable in VHDL. I see that there are signal and register in Verilog. Register in Verilog is not VHDL variable?


Thanks,

 

[Jonathan Bromley]

On Sat, 29 Mar 2014 16:27:29 -0700 (PDT), rxjwg98@gmail.com wrote:

Hi,
... I always think some VHDL features in Verilog.

Sometimes this is a useful thing to do - especially if you are writing
RTL code for synthesis. Sometimes, however, it can be very misleading.

>1. There is impure keyword in VHDL. Is there a similar, or substitute in Verilog?

No.

There is a "pure" keyword in SystemVerilog, but it applies
to the object-oriented concept of a "pure virtual function",
i.e. one that must be overridden in a derived class.

There are a few places in (System)Verilog where a language
construct requires an expression with no side-effects, but
these situations are mentioned one by one in the LRM.
Otherwise, you can simply assume that all functions
are impure.

2. There are signal and variable in VHDL. I see that there are
signal and register in Verilog. Register in Verilog is not
VHDL variable?

There is no strict definition of "signal" in Verilog.

A VHDL signal carries information from one process to another,
and has delta-cycle update semantics. A VHDL variable is
strictly local to a process, and has immediate update-on-write
just like a software variable.

There is no way to enforce this distinction in Verilog.
Instead, data objects are split in a different way: Verilog
has variables and nets. Variables get their values from
write operations (assignment) in procedural code - "always"
and "initial" blocks, tasks and functions. Nets, by contrast,
get their values from structural drivers that are permanently
connected to the net - such as a continuous-assign statement,
an output port of a module that's connected to the net, and
a few other similar situations. If a net has more than one
structural driver connected to it, the net's value is the
resolved value of all the drivers (rather like a VHDL
resolved signal). A variable, however, is updated by any
process that writes to it - the most recent write wins.

This last point makes a big difference between
VHDL and Verilog. In Verilog, a variable can
be written by more than one process, and the process's
values are NOT resolved in the way VHDL would do it;
instead, you get last-write-wins.

The different treatment of delta delays between VHDL
and Verilog is also extremely important. It's been
raked-over many, many times here and elsewhere; I'm
not going to recite the issues yet again. Do a Google
search for "blocking nonblocking verilog" and you will
get more information than is good for anyone.

Finally, please be careful about using the word "register".
Verilog's basic variable data type - a bit that can hold
the values 0,1,X,Z - is called "reg". This was always a
very poor choice of name, because it is NOT a register -
it's just a variable in the Verilog programming language,
and you can make a "reg" behave like a register, a gate or
a wire by manipulating it in the appropriate way.
SystemVerilog tried to fix this by renaming "reg" to "logic",
but the old name is still there for legacy compatibility.

In a similar but less confusing way, "wire" is the standard
data type for a Verilog net. There are other kinds of net -
"wor", "wand", "medium" and a few more - but you should avoid
them unless you are trying to do very specialized gate level
modelling.

Once again for emphasis: THERE IS NO SUCH THING AS A REGISTER
IN VERILOG.

--
Jonathan
who thought he would never visit comp.lang.verilog
ever again, but seems to have changed his mind.

 

[Gabor]

On 3/30/2014 5:11 AM, Jonathan Bromley wrote:

On Sat, 29 Mar 2014 16:27:29 -0700 (PDT), rxjwg98@gmail.com wrote:

Hi,
... I always think some VHDL features in Verilog.
[snip]

2. There are signal and variable in VHDL. I see that there are
signal and register in Verilog. Register in Verilog is not
VHDL variable?

There is no strict definition of "signal" in Verilog.

A VHDL signal carries information from one process to another,
and has delta-cycle update semantics. A VHDL variable is
strictly local to a process, and has immediate update-on-write
just like a software variable.

There is no way to enforce this distinction in Verilog.
Instead, data objects are split in a different way: Verilog
has variables and nets. Variables get their values from
write operations (assignment) in procedural code - "always"
and "initial" blocks, tasks and functions. Nets, by contrast,
get their values from structural drivers that are permanently
connected to the net - such as a continuous-assign statement,
an output port of a module that's connected to the net, and
a few other similar situations. If a net has more than one
structural driver connected to it, the net's value is the
resolved value of all the drivers (rather like a VHDL
resolved signal). A variable, however, is updated by any
process that writes to it - the most recent write wins.

This last point makes a big difference between
VHDL and Verilog. In Verilog, a variable can
be written by more than one process, and the process's
values are NOT resolved in the way VHDL would do it;
instead, you get last-write-wins.

The different treatment of delta delays between VHDL
and Verilog is also extremely important. It's been
raked-over many, many times here and elsewhere; I'm
not going to recite the issues yet again. Do a Google
search for "blocking nonblocking verilog" and you will
get more information than is good for anyone.

Finally, please be careful about using the word "register".
Verilog's basic variable data type - a bit that can hold
the values 0,1,X,Z - is called "reg". This was always a
very poor choice of name, because it is NOT a register -
it's just a variable in the Verilog programming language,
and you can make a "reg" behave like a register, a gate or
a wire by manipulating it in the appropriate way.
SystemVerilog tried to fix this by renaming "reg" to "logic",
but the old name is still there for legacy compatibility.

In a similar but less confusing way, "wire" is the standard
data type for a Verilog net. There are other kinds of net -
"wor", "wand", "medium" and a few more - but you should avoid
them unless you are trying to do very specialized gate level
modelling.

Once again for emphasis: THERE IS NO SUCH THING AS A REGISTER
IN VERILOG.

For synthesis, there aren't as many differences between
VHDL and Verilog:

Assigning a variable in more than one process is illegal for
synthesis.

Signals in VHDL map into both reg (variable) and wire (net)
types in Verilog. Assignments outside of a process must
be applied to nets, and assignments inside a process must
be done to variables.

A Verilog variable can look like a VHDL signal when it gets
only non-blocking assignments.

A Verilog variable can look (something) like a VHDL variable
when it gets only blocking assignments - but local usage is
not enforced, making it easy to get in trouble. The closest
thing to a VHDL variable in Verilog is a local variable
(declared inside a named process) that is only assigned using
blocking assignments. If you're going to use blocking
assignments in a clocked process, this is the preferred
method to avoid unintentional use outside the process.

For synthesis it is not legal to use both blocking and
non-blocking assignments to the same variable.

--
Gabor