J
Jim Lewis
Guest
OSVVM release 2013.04 is now available at either http://www.synthworks.com/downloads or http://www.osvvm.org/downloads.
Open Source VHDL Verification Methodology (OSVVM) is VHDLs leading edge verification methodology. OSVVM makes adding functional coverage, randomization, and Intelligent Coverage (coverage driven randomization) to your VHDL testbench simple, concise, and powerful.
With OSVVM, you don't need a specialized verification language such as SystemVerilog or 'e' to do verification, in fact, in many key areas, OSVVM is a step ahead.
You can get more information about OSVVM at http://www.synthworks.com/blog/osvvm or at http://www.osvvm.org
Get training in our VHDL Testbenches and Verification - OS-VVM Boot Camp. See http://www.synthworks.com/vhdl_testbench_verification.htm
Open Source VHDL Verification Methodology (OSVVM) is VHDLs leading edge verification methodology. OSVVM makes adding functional coverage, randomization, and Intelligent Coverage (coverage driven randomization) to your VHDL testbench simple, concise, and powerful.
With OSVVM, you don't need a specialized verification language such as SystemVerilog or 'e' to do verification, in fact, in many key areas, OSVVM is a step ahead.
You can get more information about OSVVM at http://www.synthworks.com/blog/osvvm or at http://www.osvvm.org
Get training in our VHDL Testbenches and Verification - OS-VVM Boot Camp. See http://www.synthworks.com/vhdl_testbench_verification.htm