An unconstrained array problem

[Weng Tianxiang]

I have a problem with how to deal with an unconstrained array.

Here is the code snippet:

Package A_package is
constant DATA_OUT_WIDTH : positive := 8; -- data out width
type OUT_DATA_ARRAY is array(natural range <&gt
of unsigned(DATA_OUT_WIDTH-1 downto 0);
end A_package;

-- B_module would be used as a VHDL system module shared by all designers
entity B_module is
generic (
MULTIPLE : positive := 1)
port (
...
D_I : in OUT_DATA_ARRAY(MULTIPLE-1 downto 0);
...
);
end B_module;

architecture B of B_module is
...
end B;

If B_module is for use for one person or one company,
there is no problem with VHDL-2002,
what to do for a user to use B_module is to change DATA_OUT_WIDTH's value
in A_package to meet his new width requirement for B_module.

Now B_package is designed for all designers with VHDL and B_package
is expected to be included into any VHDL system library.
Problem comes! User cannot change DATA_OUT_WIDTH for OUT_DATA_ARRAY.

What I want to do is:

-- C_module would be used as a VHDL system module shared by all designers
entity C_module is
generic (
MULTIPLE : positive := 1;
DATA_OUT_WIDTH : positive := 8;
type OUT_DATA_ARRAY is array(natural range <&gt
of unsigned(DATA_OUT_WIDTH-1 downto 0))
port (
...
D_I : in OUT_DATA_ARRAY(MULTIPLE-1 downto 0);
...
);
end C_module;

In other words,if new type definition can be introduced into generic,
each time C_module is used, OUT_DATA_ARRAY can be any type a user wants.

I think it is the easiest way to deal with unconstrained array while
it complies with current VHDL grammar style.

Two helps are needed:
1. For VHDL-2002, is there any method to resolve the problem?
2. For VHDL-2008, is there any method to resolve the problem as
I suggested in C_module?

Thank you.

Weng

 

[Jim Lewis]

Hi Weng,
VHDL-2008 allows arrays to have unconstrained elements. Hence, you could have a package that defines

type std_logic_matrix is array (natural range <&gt of std_logic_vector ;

And then constrain both dimensions in a signal or port:
signal A : std_logic_matrix(5 downto 0)(7 downto 0) ;

It is a VHDL-2008 feature, so synthesis vendor support may vary.

Jim

 

[Weng Tianxiang]

Hi Jim,
I haven't heard you for a long time. I hope to give you some new ideas in near future.

Your comments are excellent and appreciated.

Thank you.

Weng