An English sentence?

[Weng Tianxiang]

Hi,

I am writing a paper now. I am not sure which English sentence is right in VHDL:

signal A : std_logic;

....

A <= '1';

1. set A to '1'; -- I am now using.
2. set A equal to '1';
3. set '1' to A;

Thank you.

Weng

 

[Alan Fitch]

On 04/11/14 20:19, Weng Tianxiang wrote:

Hi,

I am writing a paper now. I am not sure which English sentence is right in VHDL:

signal A : std_logic;

...

A <= '1';

1. set A to '1'; -- I am now using.
2. set A equal to '1';
3. set '1' to A;

Thank you.

Weng

Set A to '1' is fine, but I would probably say

assign '1' to A
or
assign the value '1' to A

simply because it is referred to as signal assignment in the standard,

regards
Alan

--
Alan Fitch

 

[Anssi Saari]

Alan Fitch <apf@invalid.invalid> writes:

Set A to '1' is fine, but I would probably say

assign '1' to A
or
assign the value '1' to A

simply because it is referred to as signal assignment in the standard,

OTOH, if the paper discusses generated hardware rather than pure VHDL,
then I'd prefer set.

 

[rickman]

On 11/5/2014 8:50 AM, Anssi Saari wrote:

Alan Fitch <apf@invalid.invalid> writes:

Set A to '1' is fine, but I would probably say

assign '1' to A
or
assign the value '1' to A

simply because it is referred to as signal assignment in the standard,

OTOH, if the paper discusses generated hardware rather than pure VHDL,
then I'd prefer set.

I agree with both of you.

--

Rick

 

[Weng Tianxiang]

On Tuesday, November 4, 2014 12:20:02 PM UTC-8, Weng Tianxiang wrote:

Hi,

I am writing a paper now. I am not sure which English sentence is right in VHDL:

signal A : std_logic;

...

A <= '1';

1. set A to '1'; -- I am now using.
2. set A equal to '1';
3. set '1' to A;

Thank you.

Weng

Alan, Anssi and rick,

I am very glad that three of you gave my reply. I would like to do a great change in my paper to use "assign '1' to A".

Thank you very much.

Weng