Alternative for NB4L6254 (Clock Switch that eliminates runt

Hi.

I'm working on an ECL circuit that switches an 1.5GHz clock off for
some nanoseconds and than turns it on again.

The switched clock must not contain runt pulses (truncated clock
cycles).

Onsemi's NB4L6254 has a feature they call "Eliminates Output Runt
PulseGeneration and Metastability".

Are there similar parts available?


Regards,
Norbert N.

 

[Hal Murray]

In article <b97c2f50-fa24-45c7-83c4-24db7cebb762@t18g2000prt.googlegroups.com>,
norbert.notz@gmx.de writes:

Hi.

I'm working on an ECL circuit that switches an 1.5GHz clock off for
some nanoseconds and than turns it on again.

The switched clock must not contain runt pulses (truncated clock
cycles).

Onsemi's NB4L6254 has a feature they call "Eliminates Output Runt
PulseGeneration and Metastability".

Are there similar parts available?

There are two interesting cases in this area. One is switching
between 2 clock sources. The other is just turning a clock
on and off.

The latter is simple. Just clock a FF (with the correct edge)
and use that to AND with your clock. It's all simple digital
logic. You have to check the setup/hold/prop to make sure
it works. That check is more complicated than just meeting
setup for the next cycle. You have to make sure that setup
lets the whole clock pulse through.

(Stand on your head and use OR rather than AND if
you want the clock to park high rather than low...)

Switching between clocks without letting any runts through
is a bit tricky. It requires a few cycles of dead time
while switching. The old clock has to say "done" and
turn off. The new clock has to run that "done" signal
through a synchronizer and then turn itself on.

--
These are my opinions, not necessarily my employer's. I hate spam.

 

On 10 Nov., 21:07, hal-use...@ip-64-139-1-69.sjc.megapath.net (Hal
Murray) wrote:

The latter is simple.  Just clock a FF (with the correct edge)
and use that to AND with your clock.  It's all simple digital
logic.  You have to check the setup/hold/prop to make sure
it works.  That check is more complicated than just meeting
setup for the next cycle.  You have to make sure that setup
lets the whole clock pulse through.

Thank you very much for your suggestions. What type of FF do you mean?

 

Could you please explain your suggestion a bit more detailed? A D-FF
would halve the the clock frequency.

 

On 10 Nov., 21:07, hal-use...@ip-64-139-1-69.sjc.megapath.net (Hal
Murray) wrote:

Switching between clocks without letting any runts through
is a bit tricky.  It requires a few cycles of dead time
while switching.  The old clock has to say "done" and
turn off.  The new clock has to run that "done" signal
through a synchronizer and then turn itself on.

Hi Hal,

I understand your suggestion. In this circuit the D-FF's propagation
delay is USED (desired) to generate a runt pulse free clock. I want to
turn off/on a 1.5GHz (T = 666 ps) clock. As D-FF I consider to use the
MC100EP29, the MC100LVEP05 as AND.

Because of T = 666 ps the D-FF's propagation delay has to be in the
range 333 ps - 666 ps. The MC100EP29 has a propagation delay 350 ps -
550 ps (25°C - 85°C), so it may work.

The problem I see is the asynchronism between the switch-signal (D-
FF's D-input) and the clock: Setup and Hold times could be violated
driving the D-FF into metastable state.

Do you have practical experience using this circuit build with ECL-
gates?


Regards,
Norbert N.

 

On 10 Nov., 21:07, hal-use...@ip-64-139-1-69.sjc.megapath.net (Hal
Murray) wrote:

Just clock a FF (with the correct edge)
and use that to AND with your clock.  It's all simple digital
logic.  You have to check the setup/hold/prop to make sure
it works.  That check is more complicated than just meeting
setup for the next cycle.  You have to make sure that setup
lets the whole clock pulse through.

Hi Hal,

I understand your suggestion. In this circuit the D-FF's propagation
delay is USED (desired) to generate a runt pulse free clock. I want to
turn off/on a 1.5GHz (T = 666 ps) clock. As D-FF I consider to use the
MC100EP29, the MC100LVEP05 as AND.

Because of T = 666 ps the D-FF's propagation delay has to be in the
range 333 ps - 666 ps. The MC100EP29 has a propagation delay 350 ps -
550 ps (25°C - 85°C), so it may work.

The problem I see is the asynchronism between the switch-signal (D-
FF's D-input) and the clock: Setup and Hold times could be violated
driving the D-FF into metastable state.

Do you have practical experience using this circuit build with ECL-
gates?

Regards,
Norbert N.

 

[Hal Murray]

I understand your suggestion. In this circuit the D-FF's propagation
delay is USED (desired) to generate a runt pulse free clock. I want to
turn off/on a 1.5GHz (T =3D 666 ps) clock. As D-FF I consider to use the
MC100EP29, the MC100LVEP05 as AND.

Because of T = 666 ps the D-FF's propagation delay has to be in the
range 333 ps - 666 ps. The MC100EP29 has a propagation delay 350 ps -
550 ps (25C - 85C), so it may work.

The problem I see is the asynchronism between the switch-signal (D-
FF's D-input) and the clock: Setup and Hold times could be violated
driving the D-FF into metastable state.

It's not a simple circuit. I think Xilinx had an app note about it.

The basic idea is a FF and AND gate to make each side, and an
OR gate to merge them together. Call the FFs EnableClkA and
EnableClkB.

You have to turn them on cleanly and turn them off cleanly.
They get clocked by their own clock.

With 2 FFs, you have 4 states. 10 and 01 are normal operational
modes. 11 is illegal. 00 is a transition.

You also have an external (asynchronous) signal to select
which clock to use. It needs 2 synchronizers, one for each
clock domain.

To switch from ClkA to ClkB, you have to turn EnableClkA off
then turn EnableClkB on. From ClkB's view, EnableClkA is
anynchronous so you need a synchronizer in that path.

So if you are running with EnableClkA on, and the control
signal says switch to ClkB, first you turn EnableClkA off,
then EnableClkB can get turned on.


--
These are my opinions, not necessarily my employer's. I hate spam.