Advise for intel about integrating RAM onto chip.

[Rick C]

On Thursday, February 13, 2020 at 2:32:20 PM UTC-5, Whoey Louie wrote:

On Wednesday, February 12, 2020 at 10:49:04 AM UTC-5, DecadentLinux...@decadence.org wrote:
Whoey Louie <trader4@optonline.net> wrote in news:7bfb4c1d-998a-4bfb-
a8ba-f2816c3e79a5@googlegroups.com:

TSMC will
be rolling out 5nm later this year.

With 7nm just entering the market, it will take a few years to
amortize the fab hardware costs.

Got a citation?

Google broken? TSMC demonstrated it last year, they will be shipping
iPhone chips on 5 nm in Q2. They've been doing 7nm since 2018.

Like I said, TSMC is now ahead of Intel on process technology. A very
bad sign for America. And it validates AMD's decision to get out of
the fab business. At the time, the common wisdom was that without fabs,
they would fall further behind Intel, by not having the latest process
tech. Instead, it's worked the other way around. Now AMD has 7nm for
much of it's product line and Intel only has 10nm for it;s mobile chips.
That is simply stunning. But it shows what happens when bean counters
take over a tech giant.

Not sure who you are referring to about the bean counters. Fabs are hugely expensive, but with the sort of volume CPUs are made they are worth it. Well, you either pay for your own fabs or you pay for someone else's. So was it the Intel bean counters who said it was still better to keep working their own fabs or was it AMD's bean counters who said the smart move was to sell off their fabs and pay for TMSC expertise?

Aren't they all run by bean counters? You can actually do a lot with sub-optimal technical decisions, but if you count your beans wrong you go out of business. That's why people short Tesla stock. There are many, many ways Tesla can get it wrong and end up as a GM skate board. There are many fewer ways Tesla can actually support a $900 a share price.

Bean counters have to run the company at some point.

--

Rick C.

- Get 1,000 miles of free Supercharging
- Tesla referral code - https://ts.la/richard11209

 

[Rick C]

On Monday, February 10, 2020 at 4:01:10 PM UTC-5, upsid...@downunder.com wrote:

On Sun, 9 Feb 2020 17:29:40 -0800 (PST), skybuck2000@hotmail.com
wrote:

One more posting though about the "RAM" integration attempt of intel and others onto CPUs/chips.

It seems Intel is trying to be "nice" about it and trying to create an "eco" system for other RAM manufacturers to deliver "RAM" chips for integration on top of the Intel's CPUs.

Just stacking RAM and CPU on separate chips in the horizontal
direction or vertical direction is very boring.

I am interested if someone integrates a one gigabit of RAM with a SIMD
(vector processor). A 32Krows x 32 Kcolumn RAM with 1024 parallel 32
bit ALUs would be an interesting parallel architecture.

You should take a harder look at your design. First, if you are using SDRAM this is going to be very slow. If you use SRAM it's going to be very hot. Are you talking about 1024 memories, one per CPU for 1 Tbits?

I'm not seeing a viable architecture. I would think the GPU in desktops would be pretty optimal these days. What part of that do you think you can improve upon?

--

Rick C.

+ Get 1,000 miles of free Supercharging
+ Tesla referral code - https://ts.la/richard11209

 

[Whoey Louie]

On Thursday, February 13, 2020 at 3:08:52 PM UTC-5, Rick C wrote:

On Thursday, February 13, 2020 at 2:32:20 PM UTC-5, Whoey Louie wrote:
On Wednesday, February 12, 2020 at 10:49:04 AM UTC-5, DecadentLinux...@decadence.org wrote:
Whoey Louie <trader4@optonline.net> wrote in news:7bfb4c1d-998a-4bfb-
a8ba-f2816c3e79a5@googlegroups.com:

TSMC will
be rolling out 5nm later this year.

With 7nm just entering the market, it will take a few years to
amortize the fab hardware costs.

Got a citation?

Google broken? TSMC demonstrated it last year, they will be shipping
iPhone chips on 5 nm in Q2. They've been doing 7nm since 2018.

Like I said, TSMC is now ahead of Intel on process technology. A very
bad sign for America. And it validates AMD's decision to get out of
the fab business. At the time, the common wisdom was that without fabs,
they would fall further behind Intel, by not having the latest process
tech. Instead, it's worked the other way around. Now AMD has 7nm for
much of it's product line and Intel only has 10nm for it;s mobile chips..
That is simply stunning. But it shows what happens when bean counters
take over a tech giant.

Not sure who you are referring to about the bean counters.

Intel. It's been taken over by bean counters. The CEO was CFO
at Ebay. He came to Intel to be their CFO four years ago. Can't see
any problems there, right? Prior to him it was
run for a year by Bryant, Intel's been counter, after they
fired Krazinch in silly overreaction to a "me too" offense.
The decline really started under Otellini, another bean counter.
Though at least he did have a long career at Intel in various
marketing type positions. The chairman of the board is Intel's
bean counter. Another great idea. Most of the rest of the board isn't
very impressive either.




Fabs are hugely expensive, but with the sort of volume CPUs are made they are worth it. Well, you either pay for your own fabs or you pay for someone else's. So was it the Intel bean counters who said it was still better to keep working their own fabs or was it AMD's bean counters who said the smart move was to sell off their fabs and pay for TMSC expertise?

Apparently both.

Aren't they all run by bean counters?

Who is "all"? All chip companies? All tech companies? All Fortune 500?
AMD isn't run by one. She's an electrical engineer, with history in
the business, including developing process technology.


> You can actually do a lot with sub-optimal technical decisions, but if you count your beans wrong you go out of business.

And how hard is it and what experience does one need to count beans
as opposed to figure out what products businesses and people need
for the future, how manage design teams, and how to build and run fabs?
Sure, companies need accountant types. But they sure shouldn't be
running the place.

That's why people short Tesla stock.

There are many, many ways Tesla can get it wrong and end up as a GM skate board. There are many fewer ways Tesla can actually support a $900 a share price.

Bean counters have to run the company at some point.

BS. Intel's where it is today because of Gordon Moore, Bob Noyce
and Andy Grove. None were bean counters. Tesla is where it is
today because of Musk. You think it would be a
good idea to put a CFO from Ebay in charge of your beloved Tesla
or Space X, instead of Musk?

--

Rick C.

- Get 1,000 miles of free Supercharging
- Tesla referral code - https://ts.la/richard11209

 

On Thu, 13 Feb 2020 12:24:17 -0800 (PST), Rick C
<gnuarm.deletethisbit@gmail.com> wrote:

On Monday, February 10, 2020 at 4:01:10 PM UTC-5, upsid...@downunder.com wrote:
On Sun, 9 Feb 2020 17:29:40 -0800 (PST), skybuck2000@hotmail.com
wrote:

One more posting though about the "RAM" integration attempt of intel and others onto CPUs/chips.

It seems Intel is trying to be "nice" about it and trying to create an "eco" system for other RAM manufacturers to deliver "RAM" chips for integration on top of the Intel's CPUs.

Just stacking RAM and CPU on separate chips in the horizontal
direction or vertical direction is very boring.

I am interested if someone integrates a one gigabit of RAM with a SIMD
(vector processor). A 32Krows x 32 Kcolumn RAM with 1024 parallel 32
bit ALUs would be an interesting parallel architecture.

You should take a harder look at your design. First, if you are using SDRAM this is going to be very slow.

SDRAM is mainly an interface specification. I am talking about the
internal structure of a dynamic RAM array. The interesting part is the
propagation time from row address input to sense amplifier output.
This should these days be well below 10 ms and considering the column
write back, we are talking about 10-15 ns. Within that time, you get
e.g. 32 K column bits which could feed 1024 array processors each 32
bits wide. The memory data read rate would be 32 K x 100 MHz or 3200
Gbit/s or 400 Gbytes/s, thus 16 times faster than the fastest DDR4.
..

With a few decade of (S)DRAM chips a large number of column bits are
internally available and then the column address is used to select a
few of these column bits to I/O pins. To speed up access, various
burst modes are used, in which the row address is held constant and
the memory access time is required and only different parts of the
columns will run through the column bit selector (which has a shorter
propagation delay than the memory cell access time. Huge burst rates
can be displayed, but before that, there is a large access time
latency, before the first bits are available at the I/O pins.

My suggestion gets rid of the column selector and I/O pin driver.


>If you use SRAM it's going to be very hot.

I am talking about dynamic RAM.

>Are you talking about 1024 memories, one per CPU for 1 Tbits?

I am talking about a single 1 Gbit DRAM array organized as 32 K rows x
32 K columns feeding 1024 ALUs. Of course running 1024 ALUs at a few
hundred MHz is going to consume some power.

>I'm not seeing a viable architecture.

My point is getting rid of the memory _interface_ bottle neck.

> I would think the GPU in desktops would be pretty optimal these days. What part of that do you think you can improve upon?

There are some GPUs (without video output that are used e.g. in
radio telescopes for hard number crunching. Unfortunately the
instruction sets are designed for graphic operations, so a very
special compiler is needed to translate e.g. Fortran to use some side
effects of the graphical instructions.

 

[Rick C]

On Thursday, February 13, 2020 at 5:06:27 PM UTC-5, upsid...@downunder.com wrote:

On Thu, 13 Feb 2020 12:24:17 -0800 (PST), Rick C
gnuarm.deletethisbit@gmail.com> wrote:

On Monday, February 10, 2020 at 4:01:10 PM UTC-5, upsid...@downunder.com wrote:
On Sun, 9 Feb 2020 17:29:40 -0800 (PST), skybuck2000@hotmail.com
wrote:

One more posting though about the "RAM" integration attempt of intel and others onto CPUs/chips.

It seems Intel is trying to be "nice" about it and trying to create an "eco" system for other RAM manufacturers to deliver "RAM" chips for integration on top of the Intel's CPUs.

Just stacking RAM and CPU on separate chips in the horizontal
direction or vertical direction is very boring.

I am interested if someone integrates a one gigabit of RAM with a SIMD
(vector processor). A 32Krows x 32 Kcolumn RAM with 1024 parallel 32
bit ALUs would be an interesting parallel architecture.

You should take a harder look at your design. First, if you are using SDRAM this is going to be very slow.

SDRAM is mainly an interface specification. I am talking about the
internal structure of a dynamic RAM array. The interesting part is the
propagation time from row address input to sense amplifier output.
This should these days be well below 10 ms and considering the column
write back, we are talking about 10-15 ns. Within that time, you get
e.g. 32 K column bits which could feed 1024 array processors each 32
bits wide. The memory data read rate would be 32 K x 100 MHz or 3200
Gbit/s or 400 Gbytes/s, thus 16 times faster than the fastest DDR4.

15 ns cycle time, or 66 MHz is very slow for a high speed processor. Why would anyone bother?

With a few decade of (S)DRAM chips a large number of column bits are
internally available and then the column address is used to select a
few of these column bits to I/O pins. To speed up access, various
burst modes are used, in which the row address is held constant and
the memory access time is required and only different parts of the
columns will run through the column bit selector (which has a shorter
propagation delay than the memory cell access time. Huge burst rates
can be displayed, but before that, there is a large access time
latency, before the first bits are available at the I/O pins.

My suggestion gets rid of the column selector and I/O pin driver.

It doesn't get past the slow part of the cycle.

If you use SRAM it's going to be very hot.

I am talking about dynamic RAM.

Are you talking about 1024 memories, one per CPU for 1 Tbits?

I am talking about a single 1 Gbit DRAM array organized as 32 K rows x
32 K columns feeding 1024 ALUs. Of course running 1024 ALUs at a few
hundred MHz is going to consume some power.

I'm not seeing a viable architecture.

My point is getting rid of the memory _interface_ bottle neck.

And substituting your own 66 MHz bottle neck.

I would think the GPU in desktops would be pretty optimal these days. What part of that do you think you can improve upon?

There are some GPUs (without video output that are used e.g. in
radio telescopes for hard number crunching. Unfortunately the
instruction sets are designed for graphic operations, so a very
special compiler is needed to translate e.g. Fortran to use some side
effects of the graphical instructions.

What is your point? These apps do have a very unbalanced development cost to volume so there aren't a lot of systems to spread the cost across. That has nothing to do with speed of the result. Any processor you design will have the same difficulties developing software for them.

Also, the memory size would likely be rather limiting for many apps. 32 kWords of memory is not much for a processor these days. It would be enough to turn 1000 ALUs loose on a single task, but that's what graphic chips do and you seem to be saying that's not the problem space your chip would be good at.

Others have thought of adding processing to memory chips. It would be nearly free with the comparatively small size of the processors. But there are technical issues (DRAM processes are not optimized for logic) and demand issues (no one wants to buy them).

New architectures are hard to promote.

--

Rick C.

-+ Get 1,000 miles of free Supercharging
-+ Tesla referral code - https://ts.la/richard11209

 

[Rick C]

On Thursday, February 13, 2020 at 3:45:44 PM UTC-5, Whoey Louie wrote:

On Thursday, February 13, 2020 at 3:08:52 PM UTC-5, Rick C wrote:
On Thursday, February 13, 2020 at 2:32:20 PM UTC-5, Whoey Louie wrote:
On Wednesday, February 12, 2020 at 10:49:04 AM UTC-5, DecadentLinux....@decadence.org wrote:
Whoey Louie <trader4@optonline.net> wrote in news:7bfb4c1d-998a-4bfb-
a8ba-f2816c3e79a5@googlegroups.com:

TSMC will
be rolling out 5nm later this year.

With 7nm just entering the market, it will take a few years to
amortize the fab hardware costs.

Got a citation?

Google broken? TSMC demonstrated it last year, they will be shipping
iPhone chips on 5 nm in Q2. They've been doing 7nm since 2018.

Like I said, TSMC is now ahead of Intel on process technology. A very
bad sign for America. And it validates AMD's decision to get out of
the fab business. At the time, the common wisdom was that without fabs,
they would fall further behind Intel, by not having the latest process
tech. Instead, it's worked the other way around. Now AMD has 7nm for
much of it's product line and Intel only has 10nm for it;s mobile chips.
That is simply stunning. But it shows what happens when bean counters
take over a tech giant.

Not sure who you are referring to about the bean counters.

Intel. It's been taken over by bean counters. The CEO was CFO
at Ebay. He came to Intel to be their CFO four years ago. Can't see
any problems there, right? Prior to him it was
run for a year by Bryant, Intel's been counter, after they
fired Krazinch in silly overreaction to a "me too" offense.
The decline really started under Otellini, another bean counter.
Though at least he did have a long career at Intel in various
marketing type positions. The chairman of the board is Intel's
bean counter. Another great idea. Most of the rest of the board isn't
very impressive either.




Fabs are hugely expensive, but with the sort of volume CPUs are made they are worth it. Well, you either pay for your own fabs or you pay for someone else's. So was it the Intel bean counters who said it was still better to keep working their own fabs or was it AMD's bean counters who said the smart move was to sell off their fabs and pay for TMSC expertise?

Apparently both.




Aren't they all run by bean counters?

Who is "all"? All chip companies? All tech companies? All Fortune 500?
AMD isn't run by one. She's an electrical engineer, with history in
the business, including developing process technology.

Everyone running a company is a bean counter. Do you think she has anything to do with technical decisions at any other than the absolute highest level? No, a CEO gets reports and either approves what the people below want to do or fires them and finds someone else. There are plenty of technical mistakes that can be made, but few of them are fatal. There are any number of financial mistakes that will sink a company.

You can actually do a lot with sub-optimal technical decisions, but if you count your beans wrong you go out of business.

And how hard is it and what experience does one need to count beans
as opposed to figure out what products businesses and people need
for the future, how manage design teams, and how to build and run fabs?
Sure, companies need accountant types. But they sure shouldn't be
running the place.



That's why people short Tesla stock.



There are many, many ways Tesla can get it wrong and end up as a GM skate board. There are many fewer ways Tesla can actually support a $900 a share price.

Bean counters have to run the company at some point.



BS. Intel's where it is today because of Gordon Moore, Bob Noyce
and Andy Grove. None were bean counters. Tesla is where it is
today because of Musk. You think it would be a
good idea to put a CFO from Ebay in charge of your beloved Tesla
or Space X, instead of Musk?

A few days ago at the last earnings call, Musk said, "it doesn't make sense to raise money because we expect to generate cash despite this growth level". Today they announced they were raising $2 billion. What makes you think Musk is in control of the company???

--

Rick C.

-- Get 1,000 miles of free Supercharging
-- Tesla referral code - https://ts.la/richard11209

 

Whoey Louie <trader4@optonline.net> wrote in news:4120c8a3-3e7e-40f6-
95c9-b761650ffad6@googlegroups.com:

Did you stop to google Intel's roadmap before you made a fool of
yourself, again? They are on 10 now, 7 next, stupid.

Wrong, always wrong.

I also read where they were considering skipping 7.

Fuck you.

I would not have said it had I not read it.

 

Whoey Louie <trader4@optonline.net> wrote in news:f469b57c-0695-4a9d-
9a06-f3755002c519@googlegroups.com:

Got a citation?

Google broken?

Fuck you. Go back to staying the fuck out of my threads.

 

[Whoey Louie]

On Thursday, February 13, 2020 at 8:29:58 PM UTC-5, Rick C wrote:

On Thursday, February 13, 2020 at 3:45:44 PM UTC-5, Whoey Louie wrote:
On Thursday, February 13, 2020 at 3:08:52 PM UTC-5, Rick C wrote:
On Thursday, February 13, 2020 at 2:32:20 PM UTC-5, Whoey Louie wrote:
On Wednesday, February 12, 2020 at 10:49:04 AM UTC-5, DecadentLinux....@decadence.org wrote:
Whoey Louie <trader4@optonline.net> wrote in news:7bfb4c1d-998a-4bfb-
a8ba-f2816c3e79a5@googlegroups.com:

TSMC will
be rolling out 5nm later this year.

With 7nm just entering the market, it will take a few years to
amortize the fab hardware costs.

Got a citation?

Google broken? TSMC demonstrated it last year, they will be shipping
iPhone chips on 5 nm in Q2. They've been doing 7nm since 2018.

Like I said, TSMC is now ahead of Intel on process technology. A very
bad sign for America. And it validates AMD's decision to get out of
the fab business. At the time, the common wisdom was that without fabs,
they would fall further behind Intel, by not having the latest process
tech. Instead, it's worked the other way around. Now AMD has 7nm for
much of it's product line and Intel only has 10nm for it;s mobile chips.
That is simply stunning. But it shows what happens when bean counters
take over a tech giant.

Not sure who you are referring to about the bean counters.

Intel. It's been taken over by bean counters. The CEO was CFO
at Ebay. He came to Intel to be their CFO four years ago. Can't see
any problems there, right? Prior to him it was
run for a year by Bryant, Intel's been counter, after they
fired Krazinch in silly overreaction to a "me too" offense.
The decline really started under Otellini, another bean counter.
Though at least he did have a long career at Intel in various
marketing type positions. The chairman of the board is Intel's
bean counter. Another great idea. Most of the rest of the board isn't
very impressive either.




Fabs are hugely expensive, but with the sort of volume CPUs are made they are worth it. Well, you either pay for your own fabs or you pay for someone else's. So was it the Intel bean counters who said it was still better to keep working their own fabs or was it AMD's bean counters who said the smart move was to sell off their fabs and pay for TMSC expertise?

Apparently both.




Aren't they all run by bean counters?

Who is "all"? All chip companies? All tech companies? All Fortune 500?
AMD isn't run by one. She's an electrical engineer, with history in
the business, including developing process technology.

Everyone running a company is a bean counter.

Apparently you are unfamiliar with that term. It;s a finance type,
an accounting major who doesn't know shit about engineering, product
development, manufacturing, etc.



Do you think she has anything to do with technical decisions at any other than the absolute highest level? No,

But she damn well understands technology and what it takes to design
and fab a chip. Does an accoutant? Is an accountant qualified to
make technology decisions at the highest level? Geez



a CEO gets reports and either approves what the people below want to do or fires them and finds someone else.

Ypu really are dumber than I even thought.



There are plenty of technical mistakes that can be made, but few of them are fatal. There are any number of financial mistakes that will sink a company.

You really are even dumber that I thought a minute ago. It's pretty rare
for a tech company to go out of business due to a financial mistake. Name
some of them for us. The companies that went bust from financial mistakes
were wall street companies that screwed themselves with junk mortgages
or ones that were outright frauds, eg Enron, Tyco, etc. All of them
had great bean counters with excellent credentials. I can find you
bean counters. Finding an Andy Grove, Elon Musk, Steve Jobs, Bill Gates,
now that's hard. But you want someone like that running a tech company,
not a fucking finance guy from Ebay.

You can actually do a lot with sub-optimal technical decisions, but if you count your beans wrong you go out of business.

And how hard is it and what experience does one need to count beans
as opposed to figure out what products businesses and people need
for the future, how manage design teams, and how to build and run fabs?
Sure, companies need accountant types. But they sure shouldn't be
running the place.



That's why people short Tesla stock.



There are many, many ways Tesla can get it wrong and end up as a GM skate board. There are many fewer ways Tesla can actually support a $900 a share price.

Bean counters have to run the company at some point.



BS. Intel's where it is today because of Gordon Moore, Bob Noyce
and Andy Grove. None were bean counters. Tesla is where it is
today because of Musk. You think it would be a
good idea to put a CFO from Ebay in charge of your beloved Tesla
or Space X, instead of Musk?

A few days ago at the last earnings call, Musk said, "it doesn't make sense to raise money because we expect to generate cash despite this growth level". Today they announced they were raising $2 billion. What makes you think Musk is in control of the company???

Well, if the CEO isn't in charge of the company, then they must
be really fucked up.

You really are on a winning streak today. Been breathing those Tesla fumes?

 

[Rick C]

On Thursday, February 13, 2020 at 10:03:39 PM UTC-5, Whoey Louie wrote:

Ypu really are dumber than I even thought.

While my opinion of you has remained unchanged.

--

Rick C.

+- Get 1,000 miles of free Supercharging
+- Tesla referral code - https://ts.la/richard11209

 

[Wolf Bagger]

On 2020-02-13 17:41, Rick C wrote:

On Thursday, February 13, 2020 at 5:06:27 PM UTC-5, upsid...@downunder.com wrote:

My point is getting rid of the memory _interface_ bottle neck.

And substituting your own 66 MHz bottle neck.

Do you even DDR4 bro?

 

Wolf Bagger <wolfbagger@pm.me> wrote in
news:wdGdnQjMGqG1fc_DnZ2dnUU7-VHNnZ2d@supernews.com:

On 2020-02-13 17:41, Rick C wrote:
On Thursday, February 13, 2020 at 5:06:27 PM UTC-5,
upsid...@downunder.com wrote:

My point is getting rid of the memory _interface_ bottle neck.

And substituting your own 66 MHz bottle neck.


Do you even DDR4 bro?

Wowsey, wowsey, woo woo...

Or as Ozzie would say... "SHHhhhh!!! I'm hunting wabbits!"