Advise for intel about integrating RAM onto chip.

One more posting though about the "RAM" integration attempt of intel and others onto CPUs/chips.

It seems Intel is trying to be "nice" about it and trying to create an "eco" system for other RAM manufacturers to deliver "RAM" chips for integration on top of the Intel's CPUs.

This tactic/strategy is probably flawed and weak. Bussiness is war, in war help nobody, everybody has to fight for themselfes, effectively.

Nobody will probably join Intel into this effort until it's proven that it will work and even then it is doubtfull. This tactic/strategy is taking too long apperently.

RAM chips may be necessary for other devices or laptop or what not. This may be an unforseen complication with this idea.

Thus I must concluse that this RAM integration onto CHIPS is an ALL-or-NOTHING strategy.

That means Intel will have to pull this off WITHOUT help from RAM manufacturers and they must do it in such a fashion that it involves ALL of their products.

Laptops/PC chips, server chips maybe even mobile phones or surface device and so forth.

Intel MUST be willing to "DESTROY" the RAM companies. It is either DESTROY or be DESTROYED potentially.

Intel stands for "integrated electronics" this is what they do, this is at the hart of their company. In the past Intel integrated CACHE chips into their CPUs.

They could very well do the same with RAM chips. But they must produce these themselfes and integrate them well.

Perhaps RAM companies will then come to intel to strike a deal before they go out of bussiness.

For now basically my conclusion is that CEO and maybe head of intel is too nice and to weak to bite through and make this happens.

Investors may have to call for FIREING of CEO if CEO is not willing to destroy RAM companies.

Intel may be very well in trouble and their future is at stake. It's other Intel destroy RAM companies or they have no good product to survive against the uncoming unslaught of AMD.

And these many-core processors will start to trickle down to laptops as well.

One temporarely solution would be to "clone" and "copy paste" threadripper design/chiplet design and go with that for now, it's proven to work somewhat, it gets hot but is doable.

Until ram on chip is decently integrated and if it's coolable.

In a way AMD seems to have beaten intel to this thanks to chiplet design and HUGE 288 MB cache in total on Threadripper 3 3990x.

I write this message mainly to try and save INTEL from destruction, Intel is needed to keep prices competitive and don't play under one HOOD lol ! =D

Bye for now,
Skybuck.

P.S.: Thoughen up ! =D

 

skybuck2000@hotmail.com wrote in news:d27e3361-d297-4bbe-ade9-
81150b04155a@googlegroups.com:

> One more posting

SNIP!

You are such an idiot.

I am pretty certain that Intel knows a lot more about things than you
ever will, child.

 

On Monday, 10 February 2020 01:29:45 UTC, skybu...@hotmail.com wrote:
> One more posting though about the "RAM" integration attempt of intel and others onto CPUs/chips.

Please don't, or we'll have to killfile you.

 

On Sun, 9 Feb 2020 17:29:40 -0800 (PST), skybuck2000@hotmail.com
wrote:

One more posting though about the "RAM" integration attempt of intel and others onto CPUs/chips.

It seems Intel is trying to be "nice" about it and trying to create an "eco" system for other RAM manufacturers to deliver "RAM" chips for integration on top of the Intel's CPUs.

Just stacking RAM and CPU on separate chips in the horizontal
direction or vertical direction is very boring.

I am interested if someone integrates a one gigabit of RAM with a SIMD
(vector processor). A 32Krows x 32 Kcolumn RAM with 1024 parallel 32
bit ALUs would be an interesting parallel architecture.

 

[Whoey Louie]

On Monday, February 10, 2020 at 4:01:10 PM UTC-5, upsid...@downunder.com wrote:

On Sun, 9 Feb 2020 17:29:40 -0800 (PST), skybuck2000@hotmail.com
wrote:

One more posting though about the "RAM" integration attempt of intel and others onto CPUs/chips.

It seems Intel is trying to be "nice" about it and trying to create an "eco" system for other RAM manufacturers to deliver "RAM" chips for integration on top of the Intel's CPUs.

Just stacking RAM and CPU on separate chips in the horizontal
direction or vertical direction is very boring.

But the title of the post is integrating it onto the CPU chip.
And of course Intel CPUs have had cache RAM since the 386.
So, again, IDK what he's talking about.

I am interested if someone integrates a one gigabit of RAM

Gigabit?


with a SIMD

(vector processor). A 32Krows x 32 Kcolumn RAM with 1024 parallel 32
bit ALUs would be an interesting parallel architecture.

 

upsidedown@downunder.com wrote in
news:qmg34fdrejgq4oc6a0o80ktn177s5o9dvn@4ax.com:

On Sun, 9 Feb 2020 17:29:40 -0800 (PST), skybuck2000@hotmail.com
wrote:

One more posting though about the "RAM" integration attempt of
intel and others onto CPUs/chips.

It seems Intel is trying to be "nice" about it and trying to
create an "eco" system for other RAM manufacturers to deliver
"RAM" chips for integration on top of the Intel's CPUs.

Just stacking RAM and CPU on separate chips in the horizontal
direction or vertical direction is very boring.

I am interested if someone integrates a one gigabit of RAM with a
SIMD (vector processor). A 32Krows x 32 Kcolumn RAM with 1024
parallel 32 bit ALUs would be an interesting parallel
architecture.

IBM's 7nm stuff looks really cool. How they gonna connect up to
that onto the outside world?

<https://cdn.arstechnica.net/wp-
content/uploads/sites/3/2015/07/19310802280_87590e0f8d_o.jpg>

Whether stuffed gets stacked or not is a no-brainer. As things get
smaller and less hot, we WILL start bringing other elements into
closer proximity. So sure, we will see local arrays being used.

But dang, how they gonna hook all that shtuff up!

 

[Robert Baer]

skybuck2000@hotmail.com wrote:

One more posting though about the "RAM" integration attempt of intel and others onto CPUs/chips.

It seems Intel is trying to be "nice" about it and trying to create an "eco" system for other RAM manufacturers to deliver "RAM" chips for integration on top of the Intel's CPUs.

* What are you talking about boy?
Never heard of L1,L2 cache?
That is RAM, kid.

This tactic/strategy is probably flawed and weak. Bussiness is war, in war help nobody, everybody has to fight for themselfes, effectively.

Nobody will probably join Intel into this effort until it's proven that it will work and even then it is doubtfull. This tactic/strategy is taking too long apperently.

RAM chips may be necessary for other devices or laptop or what not. This may be an unforseen complication with this idea.

Thus I must concluse that this RAM integration onto CHIPS is an ALL-or-NOTHING strategy.

That means Intel will have to pull this off WITHOUT help from RAM manufacturers and they must do it in such a fashion that it involves ALL of their products.

Laptops/PC chips, server chips maybe even mobile phones or surface device and so forth.

Intel MUST be willing to "DESTROY" the RAM companies. It is either DESTROY or be DESTROYED potentially.

Intel stands for "integrated electronics" this is what they do, this is at the hart of their company. In the past Intel integrated CACHE chips into their CPUs.

They could very well do the same with RAM chips. But they must produce these themselfes and integrate them well.

Perhaps RAM companies will then come to intel to strike a deal before they go out of bussiness.

For now basically my conclusion is that CEO and maybe head of intel is too nice and to weak to bite through and make this happens.

Investors may have to call for FIREING of CEO if CEO is not willing to destroy RAM companies.

Intel may be very well in trouble and their future is at stake. It's other Intel destroy RAM companies or they have no good product to survive against the uncoming unslaught of AMD.

And these many-core processors will start to trickle down to laptops as well.

One temporarely solution would be to "clone" and "copy paste" threadripper design/chiplet design and go with that for now, it's proven to work somewhat, it gets hot but is doable.

Until ram on chip is decently integrated and if it's coolable.

In a way AMD seems to have beaten intel to this thanks to chiplet design and HUGE 288 MB cache in total on Threadripper 3 3990x.

I write this message mainly to try and save INTEL from destruction, Intel is needed to keep prices competitive and don't play under one HOOD lol ! =D

Bye for now,
Skybuck.

P.S.: Thoughen up ! =D

 

[Robert Baer]

upsidedown@downunder.com wrote:

On Sun, 9 Feb 2020 17:29:40 -0800 (PST), skybuck2000@hotmail.com
wrote:

One more posting though about the "RAM" integration attempt of intel and others onto CPUs/chips.

It seems Intel is trying to be "nice" about it and trying to create an "eco" system for other RAM manufacturers to deliver "RAM" chips for integration on top of the Intel's CPUs.

Just stacking RAM and CPU on separate chips in the horizontal
direction or vertical direction is very boring.

I am interested if someone integrates a one gigabit of RAM with a SIMD
(vector processor). A 32Krows x 32 Kcolumn RAM with 1024 parallel 32
bit ALUs would be an interesting parallel architecture.


Now THAT is more like it!

 

On Mon, 10 Feb 2020 14:24:36 -0800 (PST), Whoey Louie
<trader4@optonline.net> wrote:

Just stacking RAM and CPU on separate chips in the horizontal
direction or vertical direction is very boring.

But the title of the post is integrating it onto the CPU chip.
And of course Intel CPUs have had cache RAM since the 386.
So, again, IDK what he's talking about.


I am interested if someone integrates a one gigabit of RAM

Gigabit?


with a SIMD
(vector processor). A 32Krows x 32 Kcolumn RAM with 1024 parallel 32
bit ALUs would be an interesting parallel architecture.

It should be noted how a dynamic RAM works.

On a 1 Gbit RAM the 15 bit row address selects one of the 32 K
columns. The contents of all 32 K cells in that row are read out and
forwarded into 32 K sense amplifiers and all the nits in that column
are written back to 32 K cells in parallel.

On a read cycle the output of only 1-8 sense amplifiers are selected
by the column address and forwarded to 1-8 I/O pins. On a write cycle.
most of the column bits are written back as in a read cycle _except_
for 1-8 bits, in which the sense amplifier output is replaced by the
I/O pin values. The column address defines, which bits of the column
are taken from the I/O pins.

On a typical DRAM chip, the severe bottle neck is the memory
_interface_ to the external world being only 1-8 bits wide, while
internally 32 K bits would be available. It would be impractical to
have 32 K external I/O pins

If the ALUs are integrated on the same chip, all 32 K column bits
could be accessed in parallel. Architecturally this would be simple to
make a vector processor (SIMD) with say 1024 ALUs connected to the
sense amplifier outputs A 32 bit column could support 2048 of 16 bit
ALUs, 1024 of 32 bit ALUs or 512 of 64 bit ALUs (e.g. double precision
floats each).

 

[legg]

On Mon, 10 Feb 2020 04:03:34 +0000 (UTC),
DecadentLinuxUserNumeroUno@decadence.org wrote:

skybuck2000@hotmail.com wrote in news:d27e3361-d297-4bbe-ade9-
81150b04155a@googlegroups.com:

One more posting

SNIP!

You are such an idiot.

I am pretty certain that Intel knows a lot more about things than you
ever will, child.

Skybuck's been the same age for the last twenty years.

RL

 

On Tuesday, 11 February 2020 08:14:47 UTC, upsid...@downunder.com wrote:

On a typical DRAM chip, the severe bottle neck is the memory
_interface_ to the external world being only 1-8 bits wide, while
internally 32 K bits would be available. It would be impractical to
have 32 K external I/O pins

The Russkis tried something like that long ago, but I can't find the pic anywhere :/


NT

 

[mpm]

On Monday, February 10, 2020 at 4:29:29 AM UTC-5, tabb...@gmail.com wrote:

On Monday, 10 February 2020 01:29:45 UTC, skybu...@hotmail.com wrote:
One more posting though about the "RAM" integration attempt of intel and others onto CPUs/chips.

Please don't, or we'll have to killfile you.

For a couple of years now, I have been trying to figure out exactly what is wrong with Skybuck.

So far, the top-3 contenders are:

1) He's off his meds (again)
2) A TV fell on his head as a child (I'm thinking a Kloss Nova Beam Model-1, three-lens projection TV, from an appreciable height!), or
3) He hasn't had sex yet; potentially even including himself. (Or if he has, it just wasn't as enjoyable as posting his drivel here.)

Or, maybe he's just crazy.

 

legg <legg@nospam.magma.ca> wrote in
news:rgv54fpu8ig5jtvi2njqvlh9k576nvs5q0@4ax.com:

On Mon, 10 Feb 2020 04:03:34 +0000 (UTC),
DecadentLinuxUserNumeroUno@decadence.org wrote:

skybuck2000@hotmail.com wrote in news:d27e3361-d297-4bbe-ade9-
81150b04155a@googlegroups.com:

One more posting

SNIP!

You are such an idiot.

I am pretty certain that Intel knows a lot more about things
than you
ever will, child.

Skybuck's been the same age for the last twenty years.

RL

He has spent way too much of the last five of it making inane posts
into this group.

Did you see how cool that IBM 7 nm die looked? Wow. 30Bn elements
on less space using way less power running faster. You could put 4
of them into a cellphone and have a quad quad. Or the cellphone PCB
will be 900 sq mm and the rest will be a battery that makes it run
for a month.

I hope they (IBM) come out with a new, super powerful, already
scalar Power PC version of the CELL CPU. Then folks WILL be building
supercomputers under their desks. Redux the CELL. That lil bastard
would run circle around everything had they not clamped the clocks on
it. Bring it back... Badder then ever. Emulate all that x86 and
other intel multi-pipe crap easily and faster. Just add a primo
graphics engine and set it up for AI too. Winner winner chicken
dinner.

 

tabbypurr@gmail.com wrote in
news:6db03166-27dc-47c1-bd56-f19d9706c9f8@googlegroups.com:

On Tuesday, 11 February 2020 08:14:47 UTC, upsid...@downunder.com
wrote:

On a typical DRAM chip, the severe bottle neck is the memory
_interface_ to the external world being only 1-8 bits wide,
while internally 32 K bits would be available. It would be
impractical to have 32 K external I/O pins

The Russkis tried something like that long ago, but I can't find
the pic anywhere :/


NT

Ever seen our hand wired core rope memory?

Impractical? Yeah... path lengths alone.

Even today's architectures on the MOBOs make for timing issues and
some traces have to have wiggles in them to slow down the arrival of
their pulses with respect to their neighbors.

Kind of like how engine headers need equal length pipes to be in
tune.

The F-35 stimulator racks I fitted with a few thousand high freq
SMA cables all had to be equal length. You would not believe how
cheap they get when you contract cable houses and look for bids on
builds that big. And we did more than a few stimulators for the DoD.
That is systems of 15 racks of a gazillion dollars worth of High Ghz
gear). When they bought our gear, most of the bid goes into the
gear. No cheating the gov boys when you are at 10 to 30GHz.

Instead of a few bucks a foot, they become a few bucks each (the
cables). No way we could have matched that in house. Would have
cost us millions, even if we produced higher quality product.

 

[Whoey Louie]

On Wednesday, February 12, 2020 at 9:13:39 AM UTC-5, DecadentLinux...@decadence.org wrote:

legg <legg@nospam.magma.ca> wrote in
news:rgv54fpu8ig5jtvi2njqvlh9k576nvs5q0@4ax.com:

On Mon, 10 Feb 2020 04:03:34 +0000 (UTC),
DecadentLinuxUserNumeroUno@decadence.org wrote:

skybuck2000@hotmail.com wrote in news:d27e3361-d297-4bbe-ade9-
81150b04155a@googlegroups.com:

One more posting

SNIP!

You are such an idiot.

I am pretty certain that Intel knows a lot more about things
than you
ever will, child.

Skybuck's been the same age for the last twenty years.

RL


He has spent way too much of the last five of it making inane posts
into this group.

Did you see how cool that IBM 7 nm die looked? Wow.

Did everyone see that TSMC is now leading Intel in process technology?
They are shipping a lot of product on 7nm, including AMD cpus for all
markets, while Intel only has it's mobile products on 10nm. TSMC will
be rolling out 5nm later this year.

IDK what all has gone wrong at Intel, but I know that the bean counters,
not tech or manufacturing is running the company now. The board is chock
full of similar. The transition to bean counters started with Otellini,
now they have as CEO a guy who was CFO at Ebay. Quite stunning. Wonder
what Gordon Moore thinks? Andy and Bob Noyce must be spinning in their
graves.

 

Whoey Louie <trader4@optonline.net> wrote in
news:7bfb4c1d-998a-4bfb-a8ba-f2816c3e79a5@googlegroups.com:

news:rgv54fpu8ig5jtvi2njqvlh9k576nvs5q0@4ax.com:

On Mon, 10 Feb 2020 04:03:34 +0000 (UTC),
DecadentLinuxUserNumeroUno@decadence.org wrote:

skybuck2000@hotmail.com wrote in news:d27e3361-d297-4bbe-ade9-
81150b04155a@googlegroups.com:

One more posting

SNIP!

You are such an idiot.

I am pretty certain that Intel knows a lot more about things
than you
ever will, child.

Skybuck's been the same age for the last twenty years.

RL


He has spent way too much of the last five of it making inane
posts into this group.

Did you see how cool that IBM 7 nm die looked? Wow.

Did everyone see that TSMC is now leading Intel in process
technology?

Did you stop to think that Intel is going to bypass the 7nm node
entirely?

The reference I made was to IBM. TSMC and Samsung and IBM are
making 7nm node chips together that look better than the process AMD
went with. Mostly the same but slightly newer.

They look way cool. Like old sepia photos, only 'crisper'. hehe.
Way 'crisper'.

 

Whoey Louie <trader4@optonline.net> wrote in news:7bfb4c1d-998a-4bfb-
a8ba-f2816c3e79a5@googlegroups.com:

TSMC will
be rolling out 5nm later this year.

With 7nm just entering the market, it will take a few years to
amortize the fab hardware costs.

Got a citation?

 

On Wednesday, 12 February 2020 14:28:55 UTC, DecadentLinux...@decadence.org wrote:

tabbypurr wrote in
news:6db03166-27dc-47c1-bd56-f19d9706c9f8@googlegroups.com:
On Tuesday, 11 February 2020 08:14:47 UTC, upsid...@downunder.com
wrote:

On a typical DRAM chip, the severe bottle neck is the memory
_interface_ to the external world being only 1-8 bits wide,
while internally 32 K bits would be available. It would be
impractical to have 32 K external I/O pins

The Russkis tried something like that long ago, but I can't find
the pic anywhere :/


NT


Ever seen our hand wired core rope memory?

yeees. Ever seen a valve?

Impractical? Yeah... path lengths alone.

Even today's architectures on the MOBOs make for timing issues and
some traces have to have wiggles in them to slow down the arrival of
their pulses with respect to their neighbors.

Kind of like how engine headers need equal length pipes to be in
tune.

Yeah. There are better ways to handle that of course, but it does require a bit more complexity.


NT

 

[Whoey Louie]

On Wednesday, February 12, 2020 at 10:49:04 AM UTC-5, DecadentLinux...@decadence.org wrote:

Whoey Louie <trader4@optonline.net> wrote in news:7bfb4c1d-998a-4bfb-
a8ba-f2816c3e79a5@googlegroups.com:

TSMC will
be rolling out 5nm later this year.

With 7nm just entering the market, it will take a few years to
amortize the fab hardware costs.

Got a citation?

Google broken? TSMC demonstrated it last year, they will be shipping
iPhone chips on 5 nm in Q2. They've been doing 7nm since 2018.

Like I said, TSMC is now ahead of Intel on process technology. A very
bad sign for America. And it validates AMD's decision to get out of
the fab business. At the time, the common wisdom was that without fabs,
they would fall further behind Intel, by not having the latest process
tech. Instead, it's worked the other way around. Now AMD has 7nm for
much of it's product line and Intel only has 10nm for it;s mobile chips.
That is simply stunning. But it shows what happens when bean counters
take over a tech giant.

 

[Whoey Louie]

On Wednesday, February 12, 2020 at 10:47:11 AM UTC-5, DecadentLinux...@decadence.org wrote:

Whoey Louie <trader4@optonline.net> wrote in
news:7bfb4c1d-998a-4bfb-a8ba-f2816c3e79a5@googlegroups.com:

news:rgv54fpu8ig5jtvi2njqvlh9k576nvs5q0@4ax.com:

On Mon, 10 Feb 2020 04:03:34 +0000 (UTC),
DecadentLinuxUserNumeroUno@decadence.org wrote:

skybuck2000@hotmail.com wrote in news:d27e3361-d297-4bbe-ade9-
81150b04155a@googlegroups.com:

One more posting

SNIP!

You are such an idiot.

I am pretty certain that Intel knows a lot more about things
than you
ever will, child.

Skybuck's been the same age for the last twenty years.

RL


He has spent way too much of the last five of it making inane
posts into this group.

Did you see how cool that IBM 7 nm die looked? Wow.

Did everyone see that TSMC is now leading Intel in process
technology?

Did you stop to think that Intel is going to bypass the 7nm node
entirely?

Did you stop to google Intel's roadmap before you made a fool of
yourself, again? They are on 10 now, 7 next, stupid.

Wrong, always wrong.