Achronix Semiconductor in Talks for Merger...

  • Thread starter gnuarm.del...@gmail.com
  • Start date
On 08/01/2021 18:46, gnuarm.del...@gmail.com wrote:
On Friday, January 8, 2021 at 7:37:33 AM UTC-5, HT-Lab wrote:
On 07/01/2021 22:24, Kevin Neilson wrote:
On Wednesday, January 6, 2021 at 11:35:39 AM UTC-7, gnuarm.del...@gmail.com wrote:
An IPO of sorts really. They would merge with ACE Convergence Acquisition Corp NASDAQ: ACEV and this company would be seeking investors.

Achronix has been profitable, so this should be a good deal. I\'m looking to buy in.

--

Rick C.

- Get 1,000 miles of free Supercharging
- Tesla referral code - https://ts.la/richard11209

These IPOs done through SPACs are trying to take advantage of market exuberance which will surely pass at some point. It might be easy to get burned when everything turns. I\'m suspicious of new fads in the dark financial arts.

I don\'t know much about Achronix, except that I believe they no longer use any of the asynchronous architecture on which they were originally based. Maybe they should change their name to Chronix? But that sounds like Dr. Dre album or a persistent disease. I\'m not sure how they survive in a market ruled by the duopoly,
They moved to a different market, their main product is an embedded FPGA
IP core (and associated expensive to develop backend tools). Given the
cost of making an ASIC/SoC and time to market pressures it makes sense
to add some reconfigurable bits so you can fix some \"oopses\" and add
features after tape-out.

I don\'t think it is the \"oopsies\" problem they are addressing. If you have an \"oopsie\" it is unlikely to be fixable with a separate piece of logic.
Click to expand...

No that is exactly what it is used for. By adding bypass logic to an
\"eFPGA\" there is a good change you can fix bugs after tape-out. And yes
designers do know which blocks are most likely to have issues.

This is obviously not new, microprocessor manufacturers have been doing
this for decades. I am always amazed at the issues AMD and Intel can fix
after tape-out, I am sure the patched microcode is not just some simple
ROM code that changes the instruction sequencer.

Hans
www.ht-lab.com


Allowing an ASIC user to add a bit of logic to the device or even a
custom coprocessor can be very useful. I seem to recall someone
offering such a chip once, but I don\'t recall any details. It never
made it to a general market that I know of. I suspect it was mostly
sold to OEMs with high volumes. Often FPGAs are used as prototyping
devices and that may have been how this was used.
>
 
On 08/01/2021 18:46, gnuarm.del...@gmail.com wrote:
On Friday, January 8, 2021 at 7:37:33 AM UTC-5, HT-Lab wrote:
On 07/01/2021 22:24, Kevin Neilson wrote:
On Wednesday, January 6, 2021 at 11:35:39 AM UTC-7, gnuarm.del...@gmail.com wrote:
An IPO of sorts really. They would merge with ACE Convergence Acquisition Corp NASDAQ: ACEV and this company would be seeking investors.

Achronix has been profitable, so this should be a good deal. I\'m looking to buy in.

--

Rick C.

- Get 1,000 miles of free Supercharging
- Tesla referral code - https://ts.la/richard11209

These IPOs done through SPACs are trying to take advantage of market exuberance which will surely pass at some point. It might be easy to get burned when everything turns. I\'m suspicious of new fads in the dark financial arts.

I don\'t know much about Achronix, except that I believe they no longer use any of the asynchronous architecture on which they were originally based. Maybe they should change their name to Chronix? But that sounds like Dr. Dre album or a persistent disease. I\'m not sure how they survive in a market ruled by the duopoly,
They moved to a different market, their main product is an embedded FPGA
IP core (and associated expensive to develop backend tools). Given the
cost of making an ASIC/SoC and time to market pressures it makes sense
to add some reconfigurable bits so you can fix some \"oopses\" and add
features after tape-out.

I don\'t think it is the \"oopsies\" problem they are addressing. If you have an \"oopsie\" it is unlikely to be fixable with a separate piece of logic.
Click to expand...

No that is exactly what it is used for. By adding bypass logic to an
\"eFPGA\" there is a good change you can fix bugs after tape-out. And yes
designers do know which blocks are most likely to have issues.

This is obviously not new, microprocessor manufacturers have been doing
this for decades. I am always amazed at the issues AMD and Intel can fix
after tape-out, I am sure the patched microcode is not just some simple
ROM code that changes the instruction sequencer.

Hans
www.ht-lab.com


Allowing an ASIC user to add a bit of logic to the device or even a
custom coprocessor can be very useful. I seem to recall someone
offering such a chip once, but I don\'t recall any details. It never
made it to a general market that I know of. I suspect it was mostly
sold to OEMs with high volumes. Often FPGAs are used as prototyping
devices and that may have been how this was used.
>
 
On 08/01/2021 18:46, gnuarm.del...@gmail.com wrote:
On Friday, January 8, 2021 at 7:37:33 AM UTC-5, HT-Lab wrote:
On 07/01/2021 22:24, Kevin Neilson wrote:
On Wednesday, January 6, 2021 at 11:35:39 AM UTC-7, gnuarm.del...@gmail.com wrote:
An IPO of sorts really. They would merge with ACE Convergence Acquisition Corp NASDAQ: ACEV and this company would be seeking investors.

Achronix has been profitable, so this should be a good deal. I\'m looking to buy in.

--

Rick C.

- Get 1,000 miles of free Supercharging
- Tesla referral code - https://ts.la/richard11209

These IPOs done through SPACs are trying to take advantage of market exuberance which will surely pass at some point. It might be easy to get burned when everything turns. I\'m suspicious of new fads in the dark financial arts.

I don\'t know much about Achronix, except that I believe they no longer use any of the asynchronous architecture on which they were originally based. Maybe they should change their name to Chronix? But that sounds like Dr. Dre album or a persistent disease. I\'m not sure how they survive in a market ruled by the duopoly,
They moved to a different market, their main product is an embedded FPGA
IP core (and associated expensive to develop backend tools). Given the
cost of making an ASIC/SoC and time to market pressures it makes sense
to add some reconfigurable bits so you can fix some \"oopses\" and add
features after tape-out.

I don\'t think it is the \"oopsies\" problem they are addressing. If you have an \"oopsie\" it is unlikely to be fixable with a separate piece of logic.
Click to expand...

No that is exactly what it is used for. By adding bypass logic to an
\"eFPGA\" there is a good change you can fix bugs after tape-out. And yes
designers do know which blocks are most likely to have issues.

This is obviously not new, microprocessor manufacturers have been doing
this for decades. I am always amazed at the issues AMD and Intel can fix
after tape-out, I am sure the patched microcode is not just some simple
ROM code that changes the instruction sequencer.

Hans
www.ht-lab.com


Allowing an ASIC user to add a bit of logic to the device or even a
custom coprocessor can be very useful. I seem to recall someone
offering such a chip once, but I don\'t recall any details. It never
made it to a general market that I know of. I suspect it was mostly
sold to OEMs with high volumes. Often FPGAs are used as prototyping
devices and that may have been how this was used.
>
 
On 08/01/2021 18:46, gnuarm.del...@gmail.com wrote:
On Friday, January 8, 2021 at 7:37:33 AM UTC-5, HT-Lab wrote:
On 07/01/2021 22:24, Kevin Neilson wrote:
On Wednesday, January 6, 2021 at 11:35:39 AM UTC-7, gnuarm.del...@gmail.com wrote:
An IPO of sorts really. They would merge with ACE Convergence Acquisition Corp NASDAQ: ACEV and this company would be seeking investors.

Achronix has been profitable, so this should be a good deal. I\'m looking to buy in.

--

Rick C.

- Get 1,000 miles of free Supercharging
- Tesla referral code - https://ts.la/richard11209

These IPOs done through SPACs are trying to take advantage of market exuberance which will surely pass at some point. It might be easy to get burned when everything turns. I\'m suspicious of new fads in the dark financial arts.

I don\'t know much about Achronix, except that I believe they no longer use any of the asynchronous architecture on which they were originally based. Maybe they should change their name to Chronix? But that sounds like Dr. Dre album or a persistent disease. I\'m not sure how they survive in a market ruled by the duopoly,
They moved to a different market, their main product is an embedded FPGA
IP core (and associated expensive to develop backend tools). Given the
cost of making an ASIC/SoC and time to market pressures it makes sense
to add some reconfigurable bits so you can fix some \"oopses\" and add
features after tape-out.

I don\'t think it is the \"oopsies\" problem they are addressing. If you have an \"oopsie\" it is unlikely to be fixable with a separate piece of logic.
Click to expand...

No that is exactly what it is used for. By adding bypass logic to an
\"eFPGA\" there is a good change you can fix bugs after tape-out. And yes
designers do know which blocks are most likely to have issues.

This is obviously not new, microprocessor manufacturers have been doing
this for decades. I am always amazed at the issues AMD and Intel can fix
after tape-out, I am sure the patched microcode is not just some simple
ROM code that changes the instruction sequencer.

Hans
www.ht-lab.com


Allowing an ASIC user to add a bit of logic to the device or even a
custom coprocessor can be very useful. I seem to recall someone
offering such a chip once, but I don\'t recall any details. It never
made it to a general market that I know of. I suspect it was mostly
sold to OEMs with high volumes. Often FPGAs are used as prototyping
devices and that may have been how this was used.
>
 
On 08/01/2021 18:46, gnuarm.del...@gmail.com wrote:
On Friday, January 8, 2021 at 7:37:33 AM UTC-5, HT-Lab wrote:
On 07/01/2021 22:24, Kevin Neilson wrote:
On Wednesday, January 6, 2021 at 11:35:39 AM UTC-7, gnuarm.del...@gmail.com wrote:
An IPO of sorts really. They would merge with ACE Convergence Acquisition Corp NASDAQ: ACEV and this company would be seeking investors.

Achronix has been profitable, so this should be a good deal. I\'m looking to buy in.

--

Rick C.

- Get 1,000 miles of free Supercharging
- Tesla referral code - https://ts.la/richard11209

These IPOs done through SPACs are trying to take advantage of market exuberance which will surely pass at some point. It might be easy to get burned when everything turns. I\'m suspicious of new fads in the dark financial arts.

I don\'t know much about Achronix, except that I believe they no longer use any of the asynchronous architecture on which they were originally based. Maybe they should change their name to Chronix? But that sounds like Dr. Dre album or a persistent disease. I\'m not sure how they survive in a market ruled by the duopoly,
They moved to a different market, their main product is an embedded FPGA
IP core (and associated expensive to develop backend tools). Given the
cost of making an ASIC/SoC and time to market pressures it makes sense
to add some reconfigurable bits so you can fix some \"oopses\" and add
features after tape-out.

I don\'t think it is the \"oopsies\" problem they are addressing. If you have an \"oopsie\" it is unlikely to be fixable with a separate piece of logic.
Click to expand...

No that is exactly what it is used for. By adding bypass logic to an
\"eFPGA\" there is a good change you can fix bugs after tape-out. And yes
designers do know which blocks are most likely to have issues.

This is obviously not new, microprocessor manufacturers have been doing
this for decades. I am always amazed at the issues AMD and Intel can fix
after tape-out, I am sure the patched microcode is not just some simple
ROM code that changes the instruction sequencer.

Hans
www.ht-lab.com


Allowing an ASIC user to add a bit of logic to the device or even a
custom coprocessor can be very useful. I seem to recall someone
offering such a chip once, but I don\'t recall any details. It never
made it to a general market that I know of. I suspect it was mostly
sold to OEMs with high volumes. Often FPGAs are used as prototyping
devices and that may have been how this was used.
>
 
On Saturday, January 9, 2021 at 4:31:18 AM UTC-5, HT-Lab wrote:
On 08/01/2021 18:46, gnuarm.del...@gmail.com wrote:
On Friday, January 8, 2021 at 7:37:33 AM UTC-5, HT-Lab wrote:
On 07/01/2021 22:24, Kevin Neilson wrote:
On Wednesday, January 6, 2021 at 11:35:39 AM UTC-7, gnuarm.del...@gmail.com wrote:
An IPO of sorts really. They would merge with ACE Convergence Acquisition Corp NASDAQ: ACEV and this company would be seeking investors.

Achronix has been profitable, so this should be a good deal. I\'m looking to buy in.

--

Rick C.

- Get 1,000 miles of free Supercharging
- Tesla referral code - https://ts.la/richard11209

These IPOs done through SPACs are trying to take advantage of market exuberance which will surely pass at some point. It might be easy to get burned when everything turns. I\'m suspicious of new fads in the dark financial arts.

I don\'t know much about Achronix, except that I believe they no longer use any of the asynchronous architecture on which they were originally based. Maybe they should change their name to Chronix? But that sounds like Dr. Dre album or a persistent disease. I\'m not sure how they survive in a market ruled by the duopoly,
They moved to a different market, their main product is an embedded FPGA
IP core (and associated expensive to develop backend tools). Given the
cost of making an ASIC/SoC and time to market pressures it makes sense
to add some reconfigurable bits so you can fix some \"oopses\" and add
features after tape-out.

I don\'t think it is the \"oopsies\" problem they are addressing. If you have an \"oopsie\" it is unlikely to be fixable with a separate piece of logic..
No that is exactly what it is used for. By adding bypass logic to an
\"eFPGA\" there is a good change you can fix bugs after tape-out. And yes
designers do know which blocks are most likely to have issues.

This is obviously not new, microprocessor manufacturers have been doing
this for decades. I am always amazed at the issues AMD and Intel can fix
after tape-out, I am sure the patched microcode is not just some simple
ROM code that changes the instruction sequencer.

Hans
www.ht-lab.com
Allowing an ASIC user to add a bit of logic to the device or even a
custom coprocessor can be very useful. I seem to recall someone
offering such a chip once, but I don\'t recall any details. It never
made it to a general market that I know of. I suspect it was mostly
sold to OEMs with high volumes. Often FPGAs are used as prototyping
devices and that may have been how this was used.
Click to expand...

Do you have any info from Achronix regarding this? While the technique is not uncommon in various devices, I don\'t think they are very large pieces of logic. If they aren\'t large, is it really important to have the fastest technology in them (which is the Achronix advantage)?

There was a device made by a European chip company that had embedded FPGA. I never saw anything about it being to \"fix\" the chip.

If the chip is being used for prototyping, that is entirely different and not an ASIC at all. Why design a chip to debug the chip you are going to design? What they do talk about at the Achronix web site is lots and lots of \"networking\" and some very high speed interfaces. Rather than fixings oppsies, I expect they are supporting leaving portions of the your ASIC to be implemented in gate software rather than hard wiring. That would seem to make a lot more sense.

--

Rick C.

-+ Get 1,000 miles of free Supercharging
-+ Tesla referral code - https://ts.la/richard11209
 
On Saturday, January 9, 2021 at 4:31:18 AM UTC-5, HT-Lab wrote:
On 08/01/2021 18:46, gnuarm.del...@gmail.com wrote:
On Friday, January 8, 2021 at 7:37:33 AM UTC-5, HT-Lab wrote:
On 07/01/2021 22:24, Kevin Neilson wrote:
On Wednesday, January 6, 2021 at 11:35:39 AM UTC-7, gnuarm.del...@gmail.com wrote:
An IPO of sorts really. They would merge with ACE Convergence Acquisition Corp NASDAQ: ACEV and this company would be seeking investors.

Achronix has been profitable, so this should be a good deal. I\'m looking to buy in.

--

Rick C.

- Get 1,000 miles of free Supercharging
- Tesla referral code - https://ts.la/richard11209

These IPOs done through SPACs are trying to take advantage of market exuberance which will surely pass at some point. It might be easy to get burned when everything turns. I\'m suspicious of new fads in the dark financial arts.

I don\'t know much about Achronix, except that I believe they no longer use any of the asynchronous architecture on which they were originally based. Maybe they should change their name to Chronix? But that sounds like Dr. Dre album or a persistent disease. I\'m not sure how they survive in a market ruled by the duopoly,
They moved to a different market, their main product is an embedded FPGA
IP core (and associated expensive to develop backend tools). Given the
cost of making an ASIC/SoC and time to market pressures it makes sense
to add some reconfigurable bits so you can fix some \"oopses\" and add
features after tape-out.

I don\'t think it is the \"oopsies\" problem they are addressing. If you have an \"oopsie\" it is unlikely to be fixable with a separate piece of logic..
No that is exactly what it is used for. By adding bypass logic to an
\"eFPGA\" there is a good change you can fix bugs after tape-out. And yes
designers do know which blocks are most likely to have issues.

This is obviously not new, microprocessor manufacturers have been doing
this for decades. I am always amazed at the issues AMD and Intel can fix
after tape-out, I am sure the patched microcode is not just some simple
ROM code that changes the instruction sequencer.

Hans
www.ht-lab.com
Allowing an ASIC user to add a bit of logic to the device or even a
custom coprocessor can be very useful. I seem to recall someone
offering such a chip once, but I don\'t recall any details. It never
made it to a general market that I know of. I suspect it was mostly
sold to OEMs with high volumes. Often FPGAs are used as prototyping
devices and that may have been how this was used.
Click to expand...

Do you have any info from Achronix regarding this? While the technique is not uncommon in various devices, I don\'t think they are very large pieces of logic. If they aren\'t large, is it really important to have the fastest technology in them (which is the Achronix advantage)?

There was a device made by a European chip company that had embedded FPGA. I never saw anything about it being to \"fix\" the chip.

If the chip is being used for prototyping, that is entirely different and not an ASIC at all. Why design a chip to debug the chip you are going to design? What they do talk about at the Achronix web site is lots and lots of \"networking\" and some very high speed interfaces. Rather than fixings oppsies, I expect they are supporting leaving portions of the your ASIC to be implemented in gate software rather than hard wiring. That would seem to make a lot more sense.

--

Rick C.

-+ Get 1,000 miles of free Supercharging
-+ Tesla referral code - https://ts.la/richard11209
 
On Saturday, January 9, 2021 at 4:31:18 AM UTC-5, HT-Lab wrote:
On 08/01/2021 18:46, gnuarm.del...@gmail.com wrote:
On Friday, January 8, 2021 at 7:37:33 AM UTC-5, HT-Lab wrote:
On 07/01/2021 22:24, Kevin Neilson wrote:
On Wednesday, January 6, 2021 at 11:35:39 AM UTC-7, gnuarm.del...@gmail.com wrote:
An IPO of sorts really. They would merge with ACE Convergence Acquisition Corp NASDAQ: ACEV and this company would be seeking investors.

Achronix has been profitable, so this should be a good deal. I\'m looking to buy in.

--

Rick C.

- Get 1,000 miles of free Supercharging
- Tesla referral code - https://ts.la/richard11209

These IPOs done through SPACs are trying to take advantage of market exuberance which will surely pass at some point. It might be easy to get burned when everything turns. I\'m suspicious of new fads in the dark financial arts.

I don\'t know much about Achronix, except that I believe they no longer use any of the asynchronous architecture on which they were originally based. Maybe they should change their name to Chronix? But that sounds like Dr. Dre album or a persistent disease. I\'m not sure how they survive in a market ruled by the duopoly,
They moved to a different market, their main product is an embedded FPGA
IP core (and associated expensive to develop backend tools). Given the
cost of making an ASIC/SoC and time to market pressures it makes sense
to add some reconfigurable bits so you can fix some \"oopses\" and add
features after tape-out.

I don\'t think it is the \"oopsies\" problem they are addressing. If you have an \"oopsie\" it is unlikely to be fixable with a separate piece of logic..
No that is exactly what it is used for. By adding bypass logic to an
\"eFPGA\" there is a good change you can fix bugs after tape-out. And yes
designers do know which blocks are most likely to have issues.

This is obviously not new, microprocessor manufacturers have been doing
this for decades. I am always amazed at the issues AMD and Intel can fix
after tape-out, I am sure the patched microcode is not just some simple
ROM code that changes the instruction sequencer.

Hans
www.ht-lab.com
Allowing an ASIC user to add a bit of logic to the device or even a
custom coprocessor can be very useful. I seem to recall someone
offering such a chip once, but I don\'t recall any details. It never
made it to a general market that I know of. I suspect it was mostly
sold to OEMs with high volumes. Often FPGAs are used as prototyping
devices and that may have been how this was used.
Click to expand...

Do you have any info from Achronix regarding this? While the technique is not uncommon in various devices, I don\'t think they are very large pieces of logic. If they aren\'t large, is it really important to have the fastest technology in them (which is the Achronix advantage)?

There was a device made by a European chip company that had embedded FPGA. I never saw anything about it being to \"fix\" the chip.

If the chip is being used for prototyping, that is entirely different and not an ASIC at all. Why design a chip to debug the chip you are going to design? What they do talk about at the Achronix web site is lots and lots of \"networking\" and some very high speed interfaces. Rather than fixings oppsies, I expect they are supporting leaving portions of the your ASIC to be implemented in gate software rather than hard wiring. That would seem to make a lot more sense.

--

Rick C.

-+ Get 1,000 miles of free Supercharging
-+ Tesla referral code - https://ts.la/richard11209
 
On Saturday, January 9, 2021 at 4:31:18 AM UTC-5, HT-Lab wrote:
On 08/01/2021 18:46, gnuarm.del...@gmail.com wrote:
On Friday, January 8, 2021 at 7:37:33 AM UTC-5, HT-Lab wrote:
On 07/01/2021 22:24, Kevin Neilson wrote:
On Wednesday, January 6, 2021 at 11:35:39 AM UTC-7, gnuarm.del...@gmail.com wrote:
An IPO of sorts really. They would merge with ACE Convergence Acquisition Corp NASDAQ: ACEV and this company would be seeking investors.

Achronix has been profitable, so this should be a good deal. I\'m looking to buy in.

--

Rick C.

- Get 1,000 miles of free Supercharging
- Tesla referral code - https://ts.la/richard11209

These IPOs done through SPACs are trying to take advantage of market exuberance which will surely pass at some point. It might be easy to get burned when everything turns. I\'m suspicious of new fads in the dark financial arts.

I don\'t know much about Achronix, except that I believe they no longer use any of the asynchronous architecture on which they were originally based. Maybe they should change their name to Chronix? But that sounds like Dr. Dre album or a persistent disease. I\'m not sure how they survive in a market ruled by the duopoly,
They moved to a different market, their main product is an embedded FPGA
IP core (and associated expensive to develop backend tools). Given the
cost of making an ASIC/SoC and time to market pressures it makes sense
to add some reconfigurable bits so you can fix some \"oopses\" and add
features after tape-out.

I don\'t think it is the \"oopsies\" problem they are addressing. If you have an \"oopsie\" it is unlikely to be fixable with a separate piece of logic..
No that is exactly what it is used for. By adding bypass logic to an
\"eFPGA\" there is a good change you can fix bugs after tape-out. And yes
designers do know which blocks are most likely to have issues.

This is obviously not new, microprocessor manufacturers have been doing
this for decades. I am always amazed at the issues AMD and Intel can fix
after tape-out, I am sure the patched microcode is not just some simple
ROM code that changes the instruction sequencer.

Hans
www.ht-lab.com
Allowing an ASIC user to add a bit of logic to the device or even a
custom coprocessor can be very useful. I seem to recall someone
offering such a chip once, but I don\'t recall any details. It never
made it to a general market that I know of. I suspect it was mostly
sold to OEMs with high volumes. Often FPGAs are used as prototyping
devices and that may have been how this was used.
Click to expand...

Do you have any info from Achronix regarding this? While the technique is not uncommon in various devices, I don\'t think they are very large pieces of logic. If they aren\'t large, is it really important to have the fastest technology in them (which is the Achronix advantage)?

There was a device made by a European chip company that had embedded FPGA. I never saw anything about it being to \"fix\" the chip.

If the chip is being used for prototyping, that is entirely different and not an ASIC at all. Why design a chip to debug the chip you are going to design? What they do talk about at the Achronix web site is lots and lots of \"networking\" and some very high speed interfaces. Rather than fixings oppsies, I expect they are supporting leaving portions of the your ASIC to be implemented in gate software rather than hard wiring. That would seem to make a lot more sense.

--

Rick C.

-+ Get 1,000 miles of free Supercharging
-+ Tesla referral code - https://ts.la/richard11209
 
On Saturday, January 9, 2021 at 4:31:18 AM UTC-5, HT-Lab wrote:
On 08/01/2021 18:46, gnuarm.del...@gmail.com wrote:
On Friday, January 8, 2021 at 7:37:33 AM UTC-5, HT-Lab wrote:
On 07/01/2021 22:24, Kevin Neilson wrote:
On Wednesday, January 6, 2021 at 11:35:39 AM UTC-7, gnuarm.del...@gmail.com wrote:
An IPO of sorts really. They would merge with ACE Convergence Acquisition Corp NASDAQ: ACEV and this company would be seeking investors.

Achronix has been profitable, so this should be a good deal. I\'m looking to buy in.

--

Rick C.

- Get 1,000 miles of free Supercharging
- Tesla referral code - https://ts.la/richard11209

These IPOs done through SPACs are trying to take advantage of market exuberance which will surely pass at some point. It might be easy to get burned when everything turns. I\'m suspicious of new fads in the dark financial arts.

I don\'t know much about Achronix, except that I believe they no longer use any of the asynchronous architecture on which they were originally based. Maybe they should change their name to Chronix? But that sounds like Dr. Dre album or a persistent disease. I\'m not sure how they survive in a market ruled by the duopoly,
They moved to a different market, their main product is an embedded FPGA
IP core (and associated expensive to develop backend tools). Given the
cost of making an ASIC/SoC and time to market pressures it makes sense
to add some reconfigurable bits so you can fix some \"oopses\" and add
features after tape-out.

I don\'t think it is the \"oopsies\" problem they are addressing. If you have an \"oopsie\" it is unlikely to be fixable with a separate piece of logic..
No that is exactly what it is used for. By adding bypass logic to an
\"eFPGA\" there is a good change you can fix bugs after tape-out. And yes
designers do know which blocks are most likely to have issues.

This is obviously not new, microprocessor manufacturers have been doing
this for decades. I am always amazed at the issues AMD and Intel can fix
after tape-out, I am sure the patched microcode is not just some simple
ROM code that changes the instruction sequencer.

Hans
www.ht-lab.com
Allowing an ASIC user to add a bit of logic to the device or even a
custom coprocessor can be very useful. I seem to recall someone
offering such a chip once, but I don\'t recall any details. It never
made it to a general market that I know of. I suspect it was mostly
sold to OEMs with high volumes. Often FPGAs are used as prototyping
devices and that may have been how this was used.
Click to expand...

Do you have any info from Achronix regarding this? While the technique is not uncommon in various devices, I don\'t think they are very large pieces of logic. If they aren\'t large, is it really important to have the fastest technology in them (which is the Achronix advantage)?

There was a device made by a European chip company that had embedded FPGA. I never saw anything about it being to \"fix\" the chip.

If the chip is being used for prototyping, that is entirely different and not an ASIC at all. Why design a chip to debug the chip you are going to design? What they do talk about at the Achronix web site is lots and lots of \"networking\" and some very high speed interfaces. Rather than fixings oppsies, I expect they are supporting leaving portions of the your ASIC to be implemented in gate software rather than hard wiring. That would seem to make a lot more sense.

--

Rick C.

-+ Get 1,000 miles of free Supercharging
-+ Tesla referral code - https://ts.la/richard11209
 
HT-Lab <hans64@htminuslab.com> wrote:
They moved to a different market, their main product is an embedded FPGA
IP core (and associated expensive to develop backend tools). Given the
cost of making an ASIC/SoC and time to market pressures it makes sense
to add some reconfigurable bits so you can fix some \"oopses\" and add
features after tape-out.
Click to expand...

Is an FPGA a good fit for that?

It\'s not unusual to add \'chicken bits\' that allow particular parts to be
disabled or bypassed. But ISTM there\'s a bit of a disconnect between that
and a full-scale FPGA. Unless you implement your entire block in FPGA
logic, it\'s always going to be faster to implement your risky logic in
several hard-logic ways and use routing controlled by chicken bits to
select. You pay an area cost for that, but retain ASIC performance - I\'d
imagine even the best FPGA logic is going to be much slower.

I could see some FPGA use cases where you want to do, say, hardware video
decode (for power reasons perhaps) but need to periodically update to the
latest codec. Similarly when doing packet processing and you need something
to handle the customer\'s special flavour of packets at line rate.

But going embedded FPGA means you pay a performance cost over hard ASIC
cells, and you\'ll pay that performance cost even if everything works first
time. I can\'t quite see going FPGA making sense for speculative bug fixes
alone.

Theo
 
HT-Lab <hans64@htminuslab.com> wrote:
They moved to a different market, their main product is an embedded FPGA
IP core (and associated expensive to develop backend tools). Given the
cost of making an ASIC/SoC and time to market pressures it makes sense
to add some reconfigurable bits so you can fix some \"oopses\" and add
features after tape-out.
Click to expand...

Is an FPGA a good fit for that?

It\'s not unusual to add \'chicken bits\' that allow particular parts to be
disabled or bypassed. But ISTM there\'s a bit of a disconnect between that
and a full-scale FPGA. Unless you implement your entire block in FPGA
logic, it\'s always going to be faster to implement your risky logic in
several hard-logic ways and use routing controlled by chicken bits to
select. You pay an area cost for that, but retain ASIC performance - I\'d
imagine even the best FPGA logic is going to be much slower.

I could see some FPGA use cases where you want to do, say, hardware video
decode (for power reasons perhaps) but need to periodically update to the
latest codec. Similarly when doing packet processing and you need something
to handle the customer\'s special flavour of packets at line rate.

But going embedded FPGA means you pay a performance cost over hard ASIC
cells, and you\'ll pay that performance cost even if everything works first
time. I can\'t quite see going FPGA making sense for speculative bug fixes
alone.

Theo
 
HT-Lab <hans64@htminuslab.com> wrote:
They moved to a different market, their main product is an embedded FPGA
IP core (and associated expensive to develop backend tools). Given the
cost of making an ASIC/SoC and time to market pressures it makes sense
to add some reconfigurable bits so you can fix some \"oopses\" and add
features after tape-out.
Click to expand...

Is an FPGA a good fit for that?

It\'s not unusual to add \'chicken bits\' that allow particular parts to be
disabled or bypassed. But ISTM there\'s a bit of a disconnect between that
and a full-scale FPGA. Unless you implement your entire block in FPGA
logic, it\'s always going to be faster to implement your risky logic in
several hard-logic ways and use routing controlled by chicken bits to
select. You pay an area cost for that, but retain ASIC performance - I\'d
imagine even the best FPGA logic is going to be much slower.

I could see some FPGA use cases where you want to do, say, hardware video
decode (for power reasons perhaps) but need to periodically update to the
latest codec. Similarly when doing packet processing and you need something
to handle the customer\'s special flavour of packets at line rate.

But going embedded FPGA means you pay a performance cost over hard ASIC
cells, and you\'ll pay that performance cost even if everything works first
time. I can\'t quite see going FPGA making sense for speculative bug fixes
alone.

Theo
 
HT-Lab <hans64@htminuslab.com> wrote:
They moved to a different market, their main product is an embedded FPGA
IP core (and associated expensive to develop backend tools). Given the
cost of making an ASIC/SoC and time to market pressures it makes sense
to add some reconfigurable bits so you can fix some \"oopses\" and add
features after tape-out.
Click to expand...

Is an FPGA a good fit for that?

It\'s not unusual to add \'chicken bits\' that allow particular parts to be
disabled or bypassed. But ISTM there\'s a bit of a disconnect between that
and a full-scale FPGA. Unless you implement your entire block in FPGA
logic, it\'s always going to be faster to implement your risky logic in
several hard-logic ways and use routing controlled by chicken bits to
select. You pay an area cost for that, but retain ASIC performance - I\'d
imagine even the best FPGA logic is going to be much slower.

I could see some FPGA use cases where you want to do, say, hardware video
decode (for power reasons perhaps) but need to periodically update to the
latest codec. Similarly when doing packet processing and you need something
to handle the customer\'s special flavour of packets at line rate.

But going embedded FPGA means you pay a performance cost over hard ASIC
cells, and you\'ll pay that performance cost even if everything works first
time. I can\'t quite see going FPGA making sense for speculative bug fixes
alone.

Theo
 
HT-Lab <hans64@htminuslab.com> wrote:
They moved to a different market, their main product is an embedded FPGA
IP core (and associated expensive to develop backend tools). Given the
cost of making an ASIC/SoC and time to market pressures it makes sense
to add some reconfigurable bits so you can fix some \"oopses\" and add
features after tape-out.
Click to expand...

Is an FPGA a good fit for that?

It\'s not unusual to add \'chicken bits\' that allow particular parts to be
disabled or bypassed. But ISTM there\'s a bit of a disconnect between that
and a full-scale FPGA. Unless you implement your entire block in FPGA
logic, it\'s always going to be faster to implement your risky logic in
several hard-logic ways and use routing controlled by chicken bits to
select. You pay an area cost for that, but retain ASIC performance - I\'d
imagine even the best FPGA logic is going to be much slower.

I could see some FPGA use cases where you want to do, say, hardware video
decode (for power reasons perhaps) but need to periodically update to the
latest codec. Similarly when doing packet processing and you need something
to handle the customer\'s special flavour of packets at line rate.

But going embedded FPGA means you pay a performance cost over hard ASIC
cells, and you\'ll pay that performance cost even if everything works first
time. I can\'t quite see going FPGA making sense for speculative bug fixes
alone.

Theo
 
Theo <theom+news@chiark.greenend.org.uk> writes:

HT-Lab <hans64@htminuslab.com> wrote:
They moved to a different market, their main product is an embedded FPGA
IP core (and associated expensive to develop backend tools). Given the
cost of making an ASIC/SoC and time to market pressures it makes sense
to add some reconfigurable bits so you can fix some \"oopses\" and add
features after tape-out.

Is an FPGA a good fit for that?
Click to expand...

I\'d like to know too. Or actually I\'d like to know the size of the eFPGA
market, the customers and who has what market share and what it\'s
actually used for but all that seems secret. But there are new(ish)
companies exclusively in that market, at least Flex Logix (although
they\'ve come out with some kind of ML FPGA chip now) and some old ones
have joined up too. Even FPGA old timer QuickLogic came out of what I
think of near death to play in that business.
 
Theo <theom+news@chiark.greenend.org.uk> writes:

HT-Lab <hans64@htminuslab.com> wrote:
They moved to a different market, their main product is an embedded FPGA
IP core (and associated expensive to develop backend tools). Given the
cost of making an ASIC/SoC and time to market pressures it makes sense
to add some reconfigurable bits so you can fix some \"oopses\" and add
features after tape-out.

Is an FPGA a good fit for that?
Click to expand...

I\'d like to know too. Or actually I\'d like to know the size of the eFPGA
market, the customers and who has what market share and what it\'s
actually used for but all that seems secret. But there are new(ish)
companies exclusively in that market, at least Flex Logix (although
they\'ve come out with some kind of ML FPGA chip now) and some old ones
have joined up too. Even FPGA old timer QuickLogic came out of what I
think of near death to play in that business.
 
Theo <theom+news@chiark.greenend.org.uk> writes:

HT-Lab <hans64@htminuslab.com> wrote:
They moved to a different market, their main product is an embedded FPGA
IP core (and associated expensive to develop backend tools). Given the
cost of making an ASIC/SoC and time to market pressures it makes sense
to add some reconfigurable bits so you can fix some \"oopses\" and add
features after tape-out.

Is an FPGA a good fit for that?
Click to expand...

I\'d like to know too. Or actually I\'d like to know the size of the eFPGA
market, the customers and who has what market share and what it\'s
actually used for but all that seems secret. But there are new(ish)
companies exclusively in that market, at least Flex Logix (although
they\'ve come out with some kind of ML FPGA chip now) and some old ones
have joined up too. Even FPGA old timer QuickLogic came out of what I
think of near death to play in that business.
 
Theo <theom+news@chiark.greenend.org.uk> writes:

HT-Lab <hans64@htminuslab.com> wrote:
They moved to a different market, their main product is an embedded FPGA
IP core (and associated expensive to develop backend tools). Given the
cost of making an ASIC/SoC and time to market pressures it makes sense
to add some reconfigurable bits so you can fix some \"oopses\" and add
features after tape-out.

Is an FPGA a good fit for that?
Click to expand...

I\'d like to know too. Or actually I\'d like to know the size of the eFPGA
market, the customers and who has what market share and what it\'s
actually used for but all that seems secret. But there are new(ish)
companies exclusively in that market, at least Flex Logix (although
they\'ve come out with some kind of ML FPGA chip now) and some old ones
have joined up too. Even FPGA old timer QuickLogic came out of what I
think of near death to play in that business.
 
On Sunday, January 10, 2021 at 1:47:08 PM UTC-5, Anssi Saari wrote:
Theo <theom...@chiark.greenend.org.uk> writes:

HT-Lab <han...@htminuslab.com> wrote:
They moved to a different market, their main product is an embedded FPGA
IP core (and associated expensive to develop backend tools). Given the
cost of making an ASIC/SoC and time to market pressures it makes sense
to add some reconfigurable bits so you can fix some \"oopses\" and add
features after tape-out.

Is an FPGA a good fit for that?
I\'d like to know too. Or actually I\'d like to know the size of the eFPGA
market, the customers and who has what market share and what it\'s
actually used for but all that seems secret. But there are new(ish)
companies exclusively in that market, at least Flex Logix (although
they\'ve come out with some kind of ML FPGA chip now) and some old ones
have joined up too. Even FPGA old timer QuickLogic came out of what I
think of near death to play in that business.
Click to expand...

What I\'ve found interesting is there are very limited options for MCU/FPGA combinations. The available choices are rather large and expensive. Like there are <$5 FPGAs and very cheap MCUs, you\'d think there would be <$5 MCU/FPGA combos. Actually, Gowin has a line of small FPGAs with an ARM CM3. I need to look into these a bit harder. I don\'t know if you can trust the pricing on the Edge web site, but they show a 9 kLUT part with the ARM for under $4. That\'s pretty interesting. The version without extra RAM is available in an 88 pin package. The version with the RAM is not available in anything larger than 48 pins at the moment without going to a BGA type package.

--

Rick C.

+- Get 1,000 miles of free Supercharging
+- Tesla referral code - https://ts.la/richard11209
 
On Sunday, January 10, 2021 at 1:47:08 PM UTC-5, Anssi Saari wrote:
Theo <theom...@chiark.greenend.org.uk> writes:

HT-Lab <han...@htminuslab.com> wrote:
They moved to a different market, their main product is an embedded FPGA
IP core (and associated expensive to develop backend tools). Given the
cost of making an ASIC/SoC and time to market pressures it makes sense
to add some reconfigurable bits so you can fix some \"oopses\" and add
features after tape-out.

Is an FPGA a good fit for that?
I\'d like to know too. Or actually I\'d like to know the size of the eFPGA
market, the customers and who has what market share and what it\'s
actually used for but all that seems secret. But there are new(ish)
companies exclusively in that market, at least Flex Logix (although
they\'ve come out with some kind of ML FPGA chip now) and some old ones
have joined up too. Even FPGA old timer QuickLogic came out of what I
think of near death to play in that business.
Click to expand...

What I\'ve found interesting is there are very limited options for MCU/FPGA combinations. The available choices are rather large and expensive. Like there are <$5 FPGAs and very cheap MCUs, you\'d think there would be <$5 MCU/FPGA combos. Actually, Gowin has a line of small FPGAs with an ARM CM3. I need to look into these a bit harder. I don\'t know if you can trust the pricing on the Edge web site, but they show a 9 kLUT part with the ARM for under $4. That\'s pretty interesting. The version without extra RAM is available in an 88 pin package. The version with the RAM is not available in anything larger than 48 pins at the moment without going to a BGA type package.

--

Rick C.

+- Get 1,000 miles of free Supercharging
+- Tesla referral code - https://ts.la/richard11209
 
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