about the always block in verilog

[GaborSzakacs]

jonesandy@comcast.net wrote:

Gabor,

Per the reference manual, you use three processes: one for each (rise/fall)register, and one for a mux controlled by the clock level. You have to either use opposite edges of the same clock signal, or use two clocks from the same DCM that are 180 degrees apart in phase. As with most things in the reference manual, they often support additional means (e.g. a single process with two clocks or both edges of one clock, mutually exclusive, as specified in 1076.6). I know they support dual-edged processes in which the same signal/variable is not assigned on both edges, so I suppose you could do it in at most two, if not a single process (using variables for the registers and a mux assignment to the output signal after the last "end if":

process (rst, clk) is
variable qr, qf: std_logic;
begin
if rst then
qr := '0';
qf := '0';
elsif rising_edge(clk) then
qr := d;
elsif falling_edge(clk) then
qf := d;
end if;
output <= (qr and clk) or (qf and not clk);
end process;

It's been a long time since I used synplify for a xilinx platform, so I don't know if the 1076.6 method works or not (including a double-edge process with assignments on both edges to the same output signal). Note that synplify does not support inferrence for all target architectures that have DDR output registers.

Andy

I'm sure there's many ways to describe this in a single process in VHDL,
I was sondering what the Verilog template looked like (since the thread
started off on that vein).

For VHDL I could see a single process without variables like:

process (rst, clk1, clk2) is
begin
if rst then
ouput <= '0';
else
if rising_edge(clk1) then
output <= d1;
end if;
if rising_edge(clk2) then
output <= d2;
end if;
end if;
end process;

Where this version more nearly models the Xilinx style dual clock,
dual D DDR flops. You could also use a synchronous reset (in the
primitive this is a parameter or generic). But in any case I
don't see how you'll model this in a single Verilog always block,
and if not, then there is an unusual exception for synthesis needed
to infer this without multi-source errors, or else it would need
two processes with two separate signals and an external mux, all
of which the synthesis tool would understand how to pack into
one DDR flop.

-- Gabor