A Simple Integrated Circuit Design with Factorial Calculatio

[serkany]

Hi,
I have been studying VHDL for a couple of months through the book
named as "Circuit Design with VHDL" by Volnei A. Pedroni. It is a
useful book for beginners. But I may ask you a few questions to make
my mind confident.

1- I learnt basic structures of VHDL. And I want to make a simple
design to calculate 5! factorial in a design. I want to design a chip
for this work. I wanna add memory, RAM and such units to this
project... Which book you advise me to learn those things? Where can I
start to use my theoretical knowledge?

2- What steps should I take to be a good VHDL programmer?

3- I am in the last year of university in electrical-electronics
engineering. I want to assign myself to PLC, Scada, Automatic Control,
VHDL and FGPA design. Do I have a Master of Science chance in an
American university? Which of them may work for me to apply for
master?

Thanks in Advance,

 

[HT-Lab]

"serkany" <seryuz@gmail.com> wrote in message
news:5b5bc3f0-f0f4-493f-a69b-26eb4d1a94c9@c36g2000yqn.googlegroups.com...

Hi,
I have been studying VHDL for a couple of months through the book
named as "Circuit Design with VHDL" by Volnei A. Pedroni. It is a
useful book for beginners. But I may ask you a few questions to make
my mind confident.

1- I learnt basic structures of VHDL. And I want to make a simple
design to calculate 5! factorial in a design. I want to design a chip
for this work. I wanna add memory, RAM and such units to this
^^^^^^

I would personally refrain from using contractions like wanna instead of
want to. Although English is not my native language I do know that if you
use constructs like this on your CV or in an email to a prospective employer
they might not appreciate it and in the current climate you really have to
dot your i's and cross your t's.

project... Which book you advise me to learn those things? Where can I
start to use my theoretical knowledge?

Get yourself a low-cost prototype board like drigmorn1 and some free tools
are start working on your factorial design. Make sure you spend enough time
on properly simulating and testing your design and don't just burn and try
or eyeball the waveform as a means of verification. Your future employer
might ask you about this.

2- What steps should I take to be a good VHDL programmer?

Practise, practise and practise and ignore any advice that SystemVerilog is
the way forward

3- I am in the last year of university in electrical-electronics
engineering. I want to assign myself to PLC, Scada, Automatic Control,
VHDL and FGPA design. Do I have a Master of Science chance in an
American university? Which of them may work for me to apply for
master?

Contact the University and ask what their entry requirements are.

Hans
www.ht-lab.com

Thanks in Advance,

 

[Mike Treseler]

serkany wrote:

1- I learnt basic structures of VHDL. And I want to make a simple
design to calculate 5! factorial in a design.

That's more of a compile time constant than a design:
test_output <= std_logic_vector(to_unsigned(factorial(5),8));

2- What steps should I take to be a good VHDL programmer?

I would
1. Learn synchronous digital design techniques.
2. Learn vhdl simulation.
3. Not call myself a programmer.

-- Mike Treseler

 

[serkany]

@Mike Treseler

That's more of a compile time constant than a design:
test_output <= std_logic_vector(to_unsigned(factorial(5),8));

Actually, my purpose is to find 5! in each trigger CLK. I want to make
4 triggers with RUN button, so at the end we will obtain 5!.
first Run trigger : 5
second one : 5*4
third one : 5*4*3
fourth one : 5*4*3*2

Where is my mistake here? Can you have a look at it, everyone?



---------------------------------------------
-----------5! factorial calculation-----------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;

-------------------------------------------
entity factorial is
port (clk : IN BIT;
result : OUT INTEGER);
end factorial;
-------------------------------------------
architecture calculation of factorial is
signal n: integer :=5;
signal temp: integer :=1;

begin
PROCESS (clk)
begin
if (clk'EVENT AND clk='1') then
temp <= temp * n;
n <= n-1;
result <= temp;
end if;
end PROCESS;
end calculation;
------------------------------------------
------------------------------------------

 

[Tricky]

On 15 Apr, 13:52, serkany <ser...@gmail.com> wrote:

@Mike Treseler

That's more of a compile time constant than a design:
test_output <= std_logic_vector(to_unsigned(factorial(5),8));

Actually, my purpose is to find 5! in each trigger CLK. I want to make
4 triggers with RUN button, so at the end we will obtain 5!.
first Run trigger    : 5
second one           : 5*4
third one            : 5*4*3
fourth one           : 5*4*3*2

Where is my mistake here? Can you have a look at it, everyone?

---------------------------------------------
-----------5! factorial calculation-----------
library ieee;
    use ieee.std_logic_1164.all;
    use ieee.std_logic_arith.all;
    use ieee.std_logic_signed.all;

-------------------------------------------
entity factorial is
    port (clk : IN BIT;
          result : OUT INTEGER);
    end factorial;
-------------------------------------------
architecture calculation of factorial is
    signal n: integer :=5;
    signal temp: integer :=1;

    begin
    PROCESS (clk)
        begin
            if (clk'EVENT AND clk='1') then
              temp <= temp * n;
              n <= n-1;
              result <= temp;
            end if;
    end PROCESS;
    end calculation;
------------------------------------------
------------------------------------------

after 5 clocks you're going to end up with 0, and it will just stay
there.

for what you are proprosing, why not do this?

type int_array_t is array(natural range<&gt of integer;
constant VALUES : int_array(0 to 3) := (5, 5*4, 5*4*3, 5*4*3*2);

signal idx : integer range 0 to 3;
begin

process(clk)
begin
if reset = '1' then
idx <= 0;
elsif rising_edge(clk) then
if idx = 3 then
idx <= 0;
else
idx <= idx + 1;
end if;
end if;
end process;

result <= VALUES(idx);

 

On Apr 15, 8:52 am, serkany <ser...@gmail.com> wrote:

@Mike Treseler

That's more of a compile time constant than a design:
test_output <= std_logic_vector(to_unsigned(factorial(5),8));

Actually, my purpose is to find 5! in each trigger CLK. I want to make
4 triggers with RUN button, so at the end we will obtain 5!.
first Run trigger    : 5
second one           : 5*4
third one            : 5*4*3
fourth one           : 5*4*3*2

Where is my mistake here? Can you have a look at it, everyone?

---------------------------------------------
-----------5! factorial calculation-----------
library ieee;
    use ieee.std_logic_1164.all;
    use ieee.std_logic_arith.all;
    use ieee.std_logic_signed.all;

-------------------------------------------
entity factorial is
    port (clk : IN BIT;
          result : OUT INTEGER);
    end factorial;
-------------------------------------------
architecture calculation of factorial is
    signal n: integer :=5;
    signal temp: integer :=1;

    begin
    PROCESS (clk)
        begin
            if (clk'EVENT AND clk='1') then
              temp <= temp * n;
              n <= n-1;
              result <= temp;
            end if;
    end PROCESS;
    end calculation;
------------------------------------------
------------------------------------------

As Tricky mentioned, your loop doesn't have a proper termination
condition (test for n=1) - this means that your result will only be
cofrrect for one clock cycle, and whether that's the first or second
or fifth clock cycle will depend on what value of n you started with.
This kind of structure (where you "toss a value into the wind" and
hope you can catch it when the corresponding answer comes back ) is
usually a dangerous way to design a system - too many ways to mess up.
I added a "done" bit you can observe in the code below.

Also, while this is "neat" for a learning project, most real hardware
should do something more than once (unless you're computing the number
42), so you want a "start on new input" or a "reset" input as well as
an input that isn't constant - I'll leave this to you.

You also have to be careful of two other more things: Your calculation
outputs an INTEGER as opposed to a std_logic_vector which means that,
even though your design might simulate OK on the computer, an FPGA
synthesizer is not guaranteed to create the "normal" twos complement
bus on the FPGA pins the way you probably want.

The other thing to watch out for is that (you mention a RUN button) -
on an FPGA eval board, you need to make sure that your RUN button is
cleanly debounced - mechanical switches can jiggle enough to make
dozens of clock events happen in a matter of milliseconds on the first
button press.

One way to test if your "framework" (RUN button and output pins) is
correct is to change your calculation logic (the factorial) into the
simplest logic you can think of: for example, a counter, or just
shifting by one bit per clock, or a toggling value every clock and see
if your board toggles the outputs. Using a dead-simple computation
lets you check that your "other stuff" (like clocking, and initial
conditions) are correct before you worry about the math.


Also, use "numeric_std" instead of "std_logic_arith" - just because
some tutorial written in 1992 says to do it, don't. It's 2008 now.
There have been lost of flame wars about this - Google this group to
learn more.

If I were to take a stab, I'd write it like this (caveat: I'm just
typing this on the fly, not testing or compiling):

Good luck,

- Kenn

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

-------------------------------------------
entity factorial is
port (clk : IN BIT;
result : OUT std_logic_vector(7 downto 0);
done : out std_logic);
end factorial;
-------------------------------------------
architecture calculation of factorial is
signal n: integer :=5;
signal temp: integer :=1;

begin
PROCESS (clk)
begin
if (clk'EVENT AND clk='1') then
temp <= temp * n;
done <= '1'; -- provisionally
if (n > 1) then
n <= n-1;
done <= '0'; -- Oh, wasn't really done
end if;
result <= std_logic_vector(to_unsigned
(result,result'length));
end if;
end PROCESS;
end calculation;
------------------------------------------