A couple of simple questions about a simple op amp circuit

Jamie · Apr 2, 2012

Jasen Betts wrote:

On 2012-04-01, Jamie <jamie_ka1lpa_not_valid_after_ka1lpa_@charter.net> wrote:

Well, at least it gives people something to talk about. But I still
can't see how he expects the circuit to be a constant current source for
the test load if you don't bother to account for the sharp knee on the
gate turn on voltage point and the load varying due to a battery
discharging while under test.

???
the circuit compares the volage across in r13 + r14 with the preset
voltage in the non-inverting input and turns the mosfet up or down to
match the voltages. the mosfet response doesn't need to be linear, only
monotonic,

And, if you stop chopping up the messages, you'll know that the whole

statement was about removing R5 from the circuit completely.

My how things can run a muck around here. Nothing but chop monkeys
around here.

Jamie

Jamie · Apr 2, 2012

Tim Wescott wrote:

On Sun, 01 Apr 2012 22:00:46 -0400, Jamie wrote:

Tim Wescott wrote:

On Sun, 01 Apr 2012 17:52:50 -0400, Jamie wrote:

Tim Wescott wrote:

On Sun, 01 Apr 2012 14:25:26 -0400, Michael Black wrote:

On Sun, 1 Apr 2012, Jamie wrote:

Bob Engelhardt wrote:

I'm a new poster here. I've posted a couple of times to SED, but
always felt that the general level of SED was _way_ above me.
SE_Basics_ is more my level.

My questions are about this battery tester (an "electronic load"):
http://home.comcast.net/~bobengelhardt/eLoad.jpg

1. What is the purpose of R5? My guess is that the ckt would work
without it, but it's in some way better with it.

No, you need R5 there. It is the feed back sense required to keep U1
operating as a voltage comparator. The + input of U1 is the
reference voltage required and the (-)input would be the comparing
point, in this case, it is comparing the SOURCE (S) side of the
mosfet transistor and will make what ever needed adjustment output
on U1 to bias Q1 to get there. If the voltage exceeds at (S) of Q1,
compared to what is sitting at (+) input of U1, U1 output will then
drop in bias voltage on the gate (G) of Q1. This of course, will
cause the Q1 to not conduct as much and lower the voltage at (S) of
Q1 to satisfy the voltage comparator circuit of U1.

But technically, if not for the capacitor from the output of the
opamp to the inverting input of the op-amp, the resistor is not
needed.

But quite practically, if not for C1 and its associated resistors then
the circuit will oscillate strongly. That circuit is a classic for
driving a MOSFET gate without oscillations.

It's no different from a voltage follower (or indeed, the other half
of the op-amp that lies unused at the lower left, the output
connected to the inverting input), though in this case, the FET is in
that feedback loop.

It's considerably different from a voltage follower into a resistive
load, though, because the MOSFET gate is very capacitive, and the
LM358 (like lots of op-amps) Really Doesn't like driving capacitive
loads, and will oscillate like mad if you try.

But the opamp wants to see voltage, which it's already seeing on the
non-inverting input. Since no voltage amplification is done in that
stage, there's no absolute reason for the resistor, the voltage at
the FET is the same voltage as at the inverting input of the op-amp.

Unless, of course, you want the circuit to actually work correctly.

Well, at least it gives people something to talk about. But I still
can't see how he expects the circuit to be a constant current source
for the test load if you don't bother to account for the sharp knee on
the gate turn on voltage point and the load varying due to a battery
discharging while under test.

I almost get the impression that maybe he thinks that is a jfet or
non-enhanced, when in fact, it's not. Maybe using the correct foot
print may have removed the mystery behind that.

The op-amp accounts for that. If you put your thumb over C1, R4, and
Q1, then what's left is a voltage follower that drives the voltage at
the top of R13 to be equal to the voltage at pin 5 of U1. Since (at DC
at least) the MOSFET takes no gate current, that voltage is
proportional to the battery current, and hence it is the battery (or
power supply) current that is being servoed.

The circuit should do a pretty darned good job of holding the load
current steady, in fact.

I fully understand how the circuit works, but my comment to the original
statement is, that R5 is needed when it was thought it could've been
removed because it looked like it wasn't needed. That is far from the
truth. That is all I was trying to convey, R5 is absolutely needed here.

Ah -- I thought you were commenting on the OP's post, not Mr. Black's
post. My error.

This is a 101 constant current circuit using a differential circuit
to
maintain it's current at R13 and R14.

Yes, and I was kind of surprised that you didn't realize it. But I've
seen some pretty astute analog circuit designers who've seen this circuit
(or similar ones) and not realized what was up.

Oh well, maybe I should pick a different brand beer. This Coors Light
is getting to me, then again, it could be the fact that I just got done
with my Taxes. And I hope all the free loaders enjoy getting my money
that I have to additionally pay on this year.

Coors Light. Ick. Surely in this day and age you can get some decent
craft beer with real taste and color!

Well, I do enjoy Sam Adams however, I can not drink that any more. It
seems to dry out my throat and gives me breathing problems when trying
to sleep at night. You notice how I said at night, other times I just
sleep at the desk!

Jamie

Bob Engelhardt · Apr 3, 2012

Bob Engelhardt wrote:

...

My questions are about this battery tester (an "electronic load"):
http://home.comcast.net/~bobengelhardt/eLoad.jpg

1. What is the purpose of R5? My guess is that the ckt would work
without it, but it's in some way better with it.

I had actually built a ckt very similar to this a while ago, without R4,
R5, & C1. It "worked" very well, as far as keeping a load current
fixed, as shown on a DVM. If I had thought to 'scope it I suppose that
I would have seen oscillation. Next time I'll know.

Follow up question: if my ckt was oscillating, how would that affect the
battery under test?

2. The 2nd op amp: "The voltage reference, U2, provides a stable
2.5-volt reference voltage ...". ...

Well, that was embarrassing! When he said "U2", I thought that he was
talking about the 2nd half of the op amp pkg. But the zener was clearly
marked as "U2". I guess that I expected a "U" to be an IC & a zener to
be a "D", never thinking ...

Thanks to all the reply-ers.

Bob

Tim Wescott · Apr 3, 2012

On Mon, 02 Apr 2012 21:53:19 -0400, Bob Engelhardt wrote:

Bob Engelhardt wrote:
...

My questions are about this battery tester (an "electronic load"):
http://home.comcast.net/~bobengelhardt/eLoad.jpg

1. What is the purpose of R5? My guess is that the ckt would work
without it, but it's in some way better with it.

I had actually built a ckt very similar to this a while ago, without R4,
R5, & C1. It "worked" very well, as far as keeping a load current
fixed, as shown on a DVM. If I had thought to 'scope it I suppose that
I would have seen oscillation. Next time I'll know.

Follow up question: if my ckt was oscillating, how would that affect the
battery under test?

You may have lucked out and not gotten oscillation. Depending on the op-
amp and the FET, such a circuit may oscillate, it may be dead stable (not
likely without a special op-amp), or it may just be laying in wait to
surprise you.

Depending on how strong the oscillation is, the battery current may just
have some ripple (not likely), it may be pulsed but retain the correct
average current (this is kinda likely), or you may not be able to set the
average current at all (most likely, but apparently not what you saw).

2. The 2nd op amp: "The voltage reference, U2, provides a stable
2.5-volt reference voltage ...". ...

Well, that was embarrassing! When he said "U2", I thought that he was
talking about the 2nd half of the op amp pkg. But the zener was clearly
marked as "U2". I guess that I expected a "U" to be an IC & a zener to
be a "D", never thinking ...

Thanks to all the reply-ers.

Bob

--
Tim Wescott
Control system and signal processing consulting
www.wescottdesign.com

Jasen Betts · Apr 3, 2012

On 2012-04-02, Jamie <jamie_ka1lpa_not_valid_after_ka1lpa_@charter.net> wrote:

Jasen Betts wrote:

On 2012-04-01, Jamie <jamie_ka1lpa_not_valid_after_ka1lpa_@charter.net> wrote:

Well, at least it gives people something to talk about. But I still
can't see how he expects the circuit to be a constant current source for
the test load if you don't bother to account for the sharp knee on the
gate turn on voltage point and the load varying due to a battery
discharging while under test.

???
the circuit compares the volage across in r13 + r14 with the preset
voltage in the non-inverting input and turns the mosfet up or down to
match the voltages. the mosfet response doesn't need to be linear, only
monotonic,

And, if you stop chopping up the messages, you'll know that the whole
statement was about removing R5 from the circuit completely.

I suspect he intended to replace the resistor with a conductor,

--
ââ 100% natural

--- Posted via news://freenews.netfront.net/ - Complaints to news@netfront.net ---

Jasen Betts · Apr 3, 2012

On 2012-04-02, Jim Thompson <To-Email-Use-The-Envelope-Icon@On-My-Web-Site.com> wrote:

On 2 Apr 2012 07:13:33 GMT, Jasen Betts <jasen@xnet.co.nz> wrote:

On 2012-04-01, Tim Wescott <tim@seemywebsite.please> wrote:

The reason for R5 is because you need R4 and C1 in there for stability:
the MOSFET gate is highly capacitive, which slows the response of U1 down
considerably. If you just connected U1 straight to Q1, then there would
be enough added lag in the loop formed by U1 and Q1 that the circuit
would oscillate. R4 isolates U1's output from the MOSFET gate (but
leaves in the lag).

C1 lets U1's output 'talk' directly to U1's input
(which introduces lead, which counteracts the lag).

nah, a capacitor from output to the inverting input reduces the AC gain
producing even more lag, this stops the op-amp from overshooting and
also ensure that it won't oscillate.

Jason, Could you elaborate on that? Like write us an equation that
shows how it reduces the AC gain?

An equation,,, you mean like numbers?

My initial thought was that the capacitor in the negative feedback path
is going to kill all the AC gain (because caps pass AC, and negative
feedback reduces gain)

Looking closer I see that the op-amp is organised as an integrator
integrating the difference between the voltage at the mosfet source
and the voltage from the pot.

So, a step change at the source will result in a ramp at the op-amp output
the slope is determined by (V_source-V_pot) R5 C1, this will result in
a change that will turn the mosfet on or off the compensate for the
error. As the source voltage approaches the set point the current in
R5 reduces and the ramp levels out.

As I understand MOSFETs (which isn't all that well) that one is
configured as a source follower, so it's going to have approxiately
unity voltage gain.

So closing the loop the step response is going to be a logarythmic
curve with the limit at the set point.

R5 is 1k and C1 is 10nF so the time constant is 10us whick looks to
be between 10 and 100 times more than the time the op-amp takes to
respond to its inputs, so it's going to mostly behave like an integrator
and will quickly

The capacitances of the mostfet (which as I said I don't really
understand) are all much smaller than C1, so I'm guessing that the
mosfet will respond about 10 times faster than the integrator does.

--
ââ 100% natural

--- Posted via news://freenews.netfront.net/ - Complaints to news@netfront.net ---

Jim Thompson · Apr 3, 2012

On 3 Apr 2012 09:51:45 GMT, Jasen Betts <jasen@xnet.co.nz> wrote:

On 2012-04-02, Jim Thompson <To-Email-Use-The-Envelope-Icon@On-My-Web-Site.com> wrote:
On 2 Apr 2012 07:13:33 GMT, Jasen Betts <jasen@xnet.co.nz> wrote:

On 2012-04-01, Tim Wescott <tim@seemywebsite.please> wrote:

The reason for R5 is because you need R4 and C1 in there for stability:
the MOSFET gate is highly capacitive, which slows the response of U1 down
considerably. If you just connected U1 straight to Q1, then there would
be enough added lag in the loop formed by U1 and Q1 that the circuit
would oscillate. R4 isolates U1's output from the MOSFET gate (but
leaves in the lag).

C1 lets U1's output 'talk' directly to U1's input
(which introduces lead, which counteracts the lag).

nah, a capacitor from output to the inverting input reduces the AC gain
producing even more lag, this stops the op-amp from overshooting and
also ensure that it won't oscillate.

Jason, Could you elaborate on that? Like write us an equation that
shows how it reduces the AC gain?

An equation,,, you mean like numbers?

No. An _equation_ describing the feedback loop from OpAmp output back
to inverting input.

My initial thought was that the capacitor in the negative feedback path
is going to kill all the AC gain (because caps pass AC, and negative
feedback reduces gain)

Looking closer I see that the op-amp is organised as an integrator
integrating the difference between the voltage at the mosfet source
and the voltage from the pot.

No.

So, a step change at the source will result in a ramp at the op-amp output
the slope is determined by (V_source-V_pot) R5 C1, this will result in
a change that will turn the mosfet on or off the compensate for the
error. As the source voltage approaches the set point the current in
R5 reduces and the ramp levels out.

As I understand MOSFETs (which isn't all that well) that one is
configured as a source follower, so it's going to have approxiately
unity voltage gain.

So closing the loop the step response is going to be a logarythmic
curve with the limit at the set point.

R5 is 1k and C1 is 10nF so the time constant is 10us whick looks to
be between 10 and 100 times more than the time the op-amp takes to
respond to its inputs, so it's going to mostly behave like an integrator
and will quickly

The capacitances of the mostfet (which as I said I don't really
understand) are all much smaller than C1, so I'm guessing that the
mosfet will respond about 10 times faster than the integrator does.

Bob Penoyer · Apr 4, 2012

On Sun, 01 Apr 2012 14:12:40 -0700, Jim Thompson
<To-Email-Use-The-Envelope-Icon@On-My-Web-Site.com> wrote:

On Sun, 01 Apr 2012 11:34:26 -0400, Bob Engelhardt
bobengelhardt@comcast.net> wrote:

I'm a new poster here. I've posted a couple of times to SED, but always
felt that the general level of SED was _way_ above me. SE_Basics_ is
more my level.

My questions are about this battery tester (an "electronic load"):
http://home.comcast.net/~bobengelhardt/eLoad.jpg

1. What is the purpose of R5? My guess is that the ckt would work
without it, but it's in some way better with it.

Both R5 _and_ R4 are to isolate the OpAmp from a capacitive load, to
prevent instability.

R5, C1, and U1 form an integrator making the circuit a Type 1 system.

Jim Thompson · Apr 4, 2012

On Tue, 03 Apr 2012 21:28:03 -0700, Bob Penoyer
<bob@NOSPAMbobpenoyer.com> wrote:

On Sun, 01 Apr 2012 14:12:40 -0700, Jim Thompson
To-Email-Use-The-Envelope-Icon@On-My-Web-Site.com> wrote:

On Sun, 01 Apr 2012 11:34:26 -0400, Bob Engelhardt
bobengelhardt@comcast.net> wrote:

I'm a new poster here. I've posted a couple of times to SED, but always
felt that the general level of SED was _way_ above me. SE_Basics_ is
more my level.

My questions are about this battery tester (an "electronic load"):
http://home.comcast.net/~bobengelhardt/eLoad.jpg

1. What is the purpose of R5? My guess is that the ckt would work
without it, but it's in some way better with it.

Both R5 _and_ R4 are to isolate the OpAmp from a capacitive load, to
prevent instability.

R5, C1, and U1 form an integrator making the circuit a Type 1 system.

Bob Penoyer · Apr 4, 2012

On Wed, 04 Apr 2012 09:12:27 -0700, Jim Thompson
<To-Email-Use-The-Envelope-Icon@On-My-Web-Site.com> wrote:

1. What is the purpose of R5? My guess is that the ckt would work
without it, but it's in some way better with it.

Both R5 _and_ R4 are to isolate the OpAmp from a capacitive load, to
prevent instability.

R5, C1, and U1 form an integrator making the circuit a Type 1 system.

Perhaps. But that's not the whole story. How does the gm and Cgs of
the FET affect the loop?

Well, as a quick look, I'd say gm isn't significant since Q1 is
connected as a source follower.

Taking Ciss as Cgs, the IRF350's is about 2600pF. That and R4 form a
time constant of 2.6us. R5 and C1 form a time constant (I know this is
an odd way to consider an integrator) of 10us so the integrator is the
dominantly slow function.

Going a step further, consider the entire loop: The integrator puts a
pole at the origin; R4 and Cgs form a low-pass RC network that puts a
pole on the negative real axis. So the root locus contains two poles,
one at the origin and another to the left of the origin. Together,
they describe a locus that is always in the left-half plane.

At least from this back-of-the-envelope approach, the circuit appears
to be inherently stable.

Jim Thompson · Apr 4, 2012

On Wed, 04 Apr 2012 15:45:40 -0700, Bob Penoyer
<bob@NOSPAMbobpenoyer.com> wrote:

On Wed, 04 Apr 2012 09:12:27 -0700, Jim Thompson
To-Email-Use-The-Envelope-Icon@On-My-Web-Site.com> wrote:

1. What is the purpose of R5? My guess is that the ckt would work
without it, but it's in some way better with it.

Both R5 _and_ R4 are to isolate the OpAmp from a capacitive load, to
prevent instability.

R5, C1, and U1 form an integrator making the circuit a Type 1 system.

Perhaps. But that's not the whole story. How does the gm and Cgs of
the FET affect the loop?

Well, as a quick look, I'd say gm isn't significant since Q1 is
connected as a source follower.

Taking Ciss as Cgs, the IRF350's is about 2600pF. That and R4 form a
time constant of 2.6us. R5 and C1 form a time constant (I know this is
an odd way to consider an integrator) of 10us so the integrator is the
dominantly slow function.

Going a step further, consider the entire loop: The integrator puts a
pole at the origin; R4 and Cgs form a low-pass RC network that puts a
pole on the negative real axis. So the root locus contains two poles,
one at the origin and another to the left of the origin. Together,
they describe a locus that is always in the left-half plane.

At least from this back-of-the-envelope approach, the circuit appears
to be inherently stable.

The whole arrangement is to keep a direct capacitive load (to ground)
away from the OpAmp, so it's a classic feed-around "lead" network.

But you're right, it appears to be stable without it... but I
personally wouldn't try it that way

A couple of simple questions about a simple op amp circuit

Jamie

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A couple of simple questions about a simple op amp circuit

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Jim Thompson

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