8 switches

[Rich Grise]

On Sun, 07 Aug 2005 17:45:52 -0700, BobG wrote:

can someone advise on a better design ?
====================================
separate has 'a rat' in it

I certainly can!

You can do this in one part. That other post, where Tom Biasi said
to make a truth table, jogged my neuron. Get a PROM that's at least
256 bits deep and at least one bit wide. Like, a 28C16, 2K x 8.

Your 8 switches go directly, with pullups, to a0 - a7. a8-10 go
to ground. Program these 8 bytes:

addresses data (hex)
binary hex
00000000001 001 0xFE
00000000010 002 0xFE
00000000100 004 0xFE
00000001000 008 0xFE
00000010000 010 0xFE
00000100000 020 0xFE
00001000000 040 0xFE
00010000000 080 0xFE

and leave all of the rest of it 0xFF. Output bit 0 will
go "low" when one and only one switch is pressed.

Have Fun!
Rich

 

[Si Ballenger]

On Thu, 11 Aug 2005 01:51:37 GMT, Rich Grise
<eatmyshorts@doubleclick.net> wrote:

On Sun, 07 Aug 2005 14:12:45 +0000, Si Ballenger wrote:

On 6 Aug 2005 23:12:49 -0700, mattk@froggy.com.au wrote:

i'm creating a basic device,

i have 8 basic open switches.

if i close one switch, i want the main circuit to be complete, however
if more than one are closed, i want the circuit to remain open.

i'm new to electronics and i was considering 8 seperate relays but i'm
assuming this would require 8 seperate switch circuits with 8 seperate
batteries, however each relay would close the same main circuit.

can someone advise on a better design ?


Well, you probably could use 9 relays, one being the master
normally closed relay for the master circuit, and the other eight
normally open operated by the switches. Connect the eight NO
relay conatacts to a power supply and a resistor, and parallel
the outputs to coil of the master relay. Size the resistors such
that current thorugh only one isn't enough to operate the master
relay, but current through two or more in parallel is sufficient
to operate the master coil, opening the master circuit.

You've just designed a Rube Goldberg doorbell. ;-P

But how do I answer TWO doors at the same time????

 

[Rich Grise]

On Thu, 11 Aug 2005 04:32:40 +0000, Si Ballenger wrote:

On Thu, 11 Aug 2005 01:51:37 GMT, Rich Grise
eatmyshorts@doubleclick.net> wrote:

On Sun, 07 Aug 2005 14:12:45 +0000, Si Ballenger wrote:

On 6 Aug 2005 23:12:49 -0700, mattk@froggy.com.au wrote:

i'm creating a basic device,

i have 8 basic open switches.

if i close one switch, i want the main circuit to be complete, however
if more than one are closed, i want the circuit to remain open.

i'm new to electronics and i was considering 8 seperate relays but i'm
assuming this would require 8 seperate switch circuits with 8 seperate
batteries, however each relay would close the same main circuit.

can someone advise on a better design ?


Well, you probably could use 9 relays, one being the master
normally closed relay for the master circuit, and the other eight
normally open operated by the switches. Connect the eight NO
relay conatacts to a power supply and a resistor, and parallel
the outputs to coil of the master relay. Size the resistors such
that current thorugh only one isn't enough to operate the master
relay, but current through two or more in parallel is sufficient
to operate the master coil, opening the master circuit.

You've just designed a Rube Goldberg doorbell. ;-P

But how do I answer TWO doors at the same time????

see alt.sci.clone ;-)

 

[Rich Grise]

On Thu, 11 Aug 2005 02:02:31 +0000, Rich Grise wrote:

On Sun, 07 Aug 2005 17:45:52 -0700, BobG wrote:

can someone advise on a better design ?
====================================
separate has 'a rat' in it

I certainly can!

You can do this in one part. That other post, where Tom Biasi said
to make a truth table, jogged my neuron. Get a PROM that's at least
256 bits deep and at least one bit wide. Like, a 28C16, 2K x 8.

Your 8 switches go directly, with pullups, to a0 - a7. a8-10 go
to ground. Program these 8 bytes:

addresses data (hex)
binary hex
00000000001 001 0xFE
00000000010 002 0xFE
00000000100 004 0xFE
00000001000 008 0xFE
00000010000 010 0xFE
00000100000 020 0xFE
00001000000 040 0xFE
00010000000 080 0xFE

and leave all of the rest of it 0xFF. Output bit 0 will
go "low" when one and only one switch is pressed.

OOpps! I've got the wrong logic in my truth table there: for NO
switches with pullups, you'd need this:

addresses data (hex)
binary hex
11111111110 3FE 0xFE
11111111101 3FD 0xFE
11111111011 3FB 0xFE
11111110111 3F7 0xFE
11111101111 3EF 0xFE
11111011111 3DF 0xFE
11110111111 3BF 0xFE
11101111111 37F 0xFE

Cheers!
Rich

 

[John Fields]

On Fri, 12 Aug 2005 18:15:35 GMT, Rich Grise <richgrise@example.net>
wrote:

On Thu, 11 Aug 2005 02:02:31 +0000, Rich Grise wrote:

On Sun, 07 Aug 2005 17:45:52 -0700, BobG wrote:

can someone advise on a better design ?
====================================
separate has 'a rat' in it

I certainly can!

You can do this in one part. That other post, where Tom Biasi said
to make a truth table, jogged my neuron. Get a PROM that's at least
256 bits deep and at least one bit wide. Like, a 28C16, 2K x 8.

Your 8 switches go directly, with pullups, to a0 - a7. a8-10 go
to ground. Program these 8 bytes:

addresses data (hex)
binary hex
00000000001 001 0xFE
00000000010 002 0xFE
00000000100 004 0xFE
00000001000 008 0xFE
00000010000 010 0xFE
00000100000 020 0xFE
00001000000 040 0xFE
00010000000 080 0xFE

and leave all of the rest of it 0xFF. Output bit 0 will
go "low" when one and only one switch is pressed.

OOpps! I've got the wrong logic in my truth table there: for NO
switches with pullups, you'd need this:

addresses data (hex)
binary hex
11111111110 3FE 0xFE
11111111101 3FD 0xFE
11111111011 3FB 0xFE
11111110111 3F7 0xFE
11111101111 3EF 0xFE
11111011111 3DF 0xFE
11110111111 3BF 0xFE
11101111111 37F 0xFE

---
For an 8 pin solution which is ratiometric, which doesn't require a
programmer, and which works down to 3V using John Popelish's maximum
voltage difference divider:


Vcc--+--------+---//---+
| | |
| [10k] [10k]
| | |
| O| O|
| O| O|
| |S1 |S8
[16k] +---//---+
| |
| | Vcc V+
| | | |
| | | [R]
| +--|-\ |
| | | >--+
+--------|--|+/ |
| | |
[3k9] | LM393 |
| | |
+--------|--|-\ |
| | | >--+-->OUT
| +--|+/
| | |
[10k] [6k8] |
| | |
| | |
GND>-+--------+---+------->GND


--
John Fields
Professional Circuit Designer

 

[John Popelish]

John Fields wrote:

For an 8 pin solution which is ratiometric, which doesn't require a
programmer, and which works down to 3V using John Popelish's maximum
voltage difference divider:

I have a refinement for your schematic: The reference divider has to
distinguish between 0 and 40% of supply (to tell 1 switch from zero)
so I think the lower reference level should be about 20% of supply.
The second decision distinguishes between 40% and 58% of supply (one
switch versus two switches), so the reference should be about half way
between those, or 49% of supply. This case has less noise margin than
the first one (+- about 10% versus about +- 20%), so the threshold has
to be pretty well centered to maximize noise margin and resistor
tolerance.

So here is your schematic repeated with the reference divider altered
to make approximately those choices:

Vcc--+--------+---//---+
| | |
| [10k] [10k]
| | |
| O| O|
| O| O|
| |S1 |S8
[51k] +---//---+
| |
| | Vcc V+
| | | |
| | | [R]
| +--|-\ |
| | | >--+
+--------|--|+/ |
| | |
[30k] | LM393 |
| | |
+--------|--|-\ |
| | | >--+-->OUT
| +--|+/
| | |
[20k] [6k8] |
| | |
| | |
GND>-+--------+---+------->GND

I think this provides enough margin for 5% resistors to work well
enough, if the switch lines are not subject to much noise pickup. The
O.P. might need to add a little filter capacitance across the 6.8k to
reduce hum.

 

[John Fields]

On Fri, 12 Aug 2005 17:17:34 -0400, John Popelish
<jpopelish@rica.net> wrote:

John Fields wrote:

For an 8 pin solution which is ratiometric, which doesn't require a
programmer, and which works down to 3V using John Popelish's maximum
voltage difference divider:

I have a refinement for your schematic: The reference divider has to
distinguish between 0 and 40% of supply (to tell 1 switch from zero)
so I think the lower reference level should be about 20% of supply.

---
Perhaps you're right, but if there's noise on ground, getting as far
away from it as possible is a good thing.
---

The second decision distinguishes between 40% and 58% of supply (one
switch versus two switches), so the reference should be about half way
between those, or 49% of supply.

---
The problem with that is that 49% of of a 3V supply is so close to
the common mode limit of the comparator that using 5% resistors to
define that point will result in unacceptable performance.
---

This case has less noise margin than
the first one (+- about 10% versus about +- 20%), so the threshold has
to be pretty well centered to maximize noise margin and resistor
tolerance.

---
Yes. Because of the limitations imposed by a 3v supply and your
divider, I opted for a window centered on 1.2V for a single switch
closure.
---

So here is your schematic repeated with the reference divider altered
to make approximately those choices:

Vcc--+--------+---//---+
| | |
| [10k] [10k]
| | |
| O| O|
| O| O|
| |S1 |S8
[51k] +---//---+
| |
| | Vcc V+
| | | |
| | | [R]
| +--|-\ |
| | | >--+
+--------|--|+/ |
| | |
[30k] | LM393 |
| | |
+--------|--|-\ |
| | | >--+-->OUT
| +--|+/
| | |
[20k] [6k8] |
| | |
| | |
GND>-+--------+---+------->GND

I think this provides enough margin for 5% resistors to work well
enough, if the switch lines are not subject to much noise pickup. The
O.P. might need to add a little filter capacitance across the 6.8k to
reduce hum.

---
I'll post my math to abse in a little while so you can see what I'm
talking about.

--
John Fields
Professional Circuit Designer

 

[John Fields]

On Fri, 12 Aug 2005 17:44:21 -0500, John Fields
<jfields@austininstruments.com> wrote:

I'll post my math to abse in a little while so you can see what I'm
talking about.

---
Tomorrow.

--
John Fields
Professional Circuit Designer

 

[John Fields]

On 8 Aug 2005 12:35:11 -0700, jpopelish@rica.net wrote:

John Fields wrote:
(snip)
+5V
|R1
[1000]
|
+-------+---->Eo
|R2 |R3
[1000] [1000]
| |
+-------+
|
GND
(snip)

I think you will get the largest possible voltage difference between 1
switch closed and 2 switches closed if R1=1/(sqrt(2))*R2.

That is why
I recommended 10k at each switch and 6.8K as the common series
resistor. I chose higher values than you did, because I was imagining
(for no particular reason) the whole thing running from a 9 volt
battery.

---
OK.

From one of your previous posts, I like your idea of referencing the
switch divider to ground instead of to Vcc, and your choice of
resistors, which _does_ give the largest difference in voltage
between one and two resistors switched in. Although, with a 3V
supply, the difference is only about 15mV more than with equal-value
resistors!

With the switching divider looking like this:

E1
|
+------+
| |
[R2] [R3]
| |
O| O|
O| O|
| |
+------+------E2
|
[R1]
|
0V

and, with a 3V supply and your resistors, we have, for a single
resistor switched in:

EIR1 3V * 6800R
E2 = ------- = -------------- = 1.214V
R1+R2 10kR + 6800R

and for two resistors switched in:

E1R1
E2 = ----------------- = 1.729v
R1 + (R2 || R3)


Now, since the upper limit of the common mode voltage range for the
LM393 is Vcc -1.5V, that's 1.5V for a 3V supply. Since the output
voltage of the switch divider will rise to 1.729V when two switches
are closed (and higher than that if more than two switches are
closed) we have to make sure that the higher output voltage from the
reference divider stays below 1.5V in order for the comparator to
work properly.

If we make a chart of where the system voltages lie in relation to
each other, amplitude-wise, we'll get something like this:

Vcc----------------3V

V2sw-------------1.73V

Vcm--------------1.5V

Vhi--------------??

V1sw-------------1.21V

Vlo--------------??

GND---------------0V

If we make Vhi equal to 1.4V, that'll give us 100mV of headroom to
the common mode limit, Vcm, which ought to be plenty, and it'll also
be higher than the one-switch output voltage, V1sw, which is what we
want. Then if we make the difference between Vhi and V1sw the same
as the voltage difference between V1sw and Vlo and round everything
off, the chart will look like this:


Vcc----------------3V

V2sw-------------1.7V

Vcm--------------1.5V

Vhi--------------1.4V

V1sw-------------1.2V

Vlo--------------1.0V

GND---------------0V


and with 100ľA in the reference string, the circuit will look like
this.


Vcc--+--------+---//---+
| | |
| [10k] [10k]
| | |
| O| O|
| O| O|
| |S1 |S8
[16k] +---//---+
| |
| | V+
| | |
| | [R]
| +--|-\ |
| | | >--+
+--------|--|+/ |
| | |
[3k9] | |
| | |
+--------|--|-\ |
| | | >--+
| +--|+/
| |
[10k] [6k8]
| |
| |
GND>-+--------+

Now, since we're using 5% resistors, the worst thing that could
happen is if their tolerances let the comparator input voltages step
on each other.

I've worked it all out, but rather than do a lot of extra typing,
I've posted my handwritten worksheets to abse.

--
John Fields
Professional Circuit Designer

 

[John Popelish]

John Fields wrote:

On 8 Aug 2005 12:35:11 -0700, jpopelish@rica.net wrote:


John Fields wrote:
(snip)

+5V
|R1
[1000]
|
+-------+---->Eo
|R2 |R3
[1000] [1000]
| |
+-------+
|
GND

(snip)

I think you will get the largest possible voltage difference between 1
switch closed and 2 switches closed if R1=1/(sqrt(2))*R2.

That is why
I recommended 10k at each switch and 6.8K as the common series
resistor. I chose higher values than you did, because I was imagining
(for no particular reason) the whole thing running from a 9 volt
battery.


---
OK.

From one of your previous posts, I like your idea of referencing the
switch divider to ground instead of to Vcc, and your choice of
resistors, which _does_ give the largest difference in voltage
between one and two resistors switched in. Although, with a 3V
supply, the difference is only about 15mV more than with equal-value
resistors!

With the switching divider looking like this:

E1
|
+------+
| |
[R2] [R3]
| |
O| O|
O| O|
| |
+------+------E2
|
[R1]
|
0V

and, with a 3V supply and your resistors, we have, for a single
resistor switched in:

EIR1 3V * 6800R
E2 = ------- = -------------- = 1.214V
R1+R2 10kR + 6800R

and for two resistors switched in:

E1R1
E2 = ----------------- = 1.729v
R1 + (R2 || R3)


Now, since the upper limit of the common mode voltage range for the
LM393 is Vcc -1.5V, that's 1.5V for a 3V supply. Since the output
voltage of the switch divider will rise to 1.729V when two switches
are closed (and higher than that if more than two switches are
closed) we have to make sure that the higher output voltage from the
reference divider stays below 1.5V in order for the comparator to
work properly.

If we make a chart of where the system voltages lie in relation to
each other, amplitude-wise, we'll get something like this:

Vcc----------------3V

V2sw-------------1.73V

Vcm--------------1.5V

Vhi--------------??

V1sw-------------1.21V

Vlo--------------??

GND---------------0V

If we make Vhi equal to 1.4V, that'll give us 100mV of headroom to
the common mode limit, Vcm, which ought to be plenty, and it'll also
be higher than the one-switch output voltage, V1sw, which is what we
want. Then if we make the difference between Vhi and V1sw the same
as the voltage difference between V1sw and Vlo and round everything
off, the chart will look like this:


Vcc----------------3V

V2sw-------------1.7V

Vcm--------------1.5V

Vhi--------------1.4V

V1sw-------------1.2V

Vlo--------------1.0V

GND---------------0V

Nice analysis with practical considerations (though, if I were really
going to go with a 3 volt battery supply, I think I would go with the
low voltage version of the dual comparator). I understand why you are
pushing the noise margin of Vhi to stay under the common mode voltage
limit, but why do you not center Vlo between GND and V1sw? It seems
to me that this reduces the tolerance limit for the lower resistor in
the reference string. Is there some advantage of raising this voltage
that I missed?

Perhaps a better solution to the common mode limit would be to reduce
the common switch resistor a bit more. Something like 4.7k helps
quite a bit. It lowers V1sw (=.959 vs. 1.2 or down 20%) more than it
does V2sw-V1sw (=.495 vs. .50 or down 1%). The 1% drop in V2sw-V1sw
is more than compensated for by making the whole swing usable.

The list changes to:

Vcc---------------3.000V

V2sw--------------1.454V

Vcm---------------1.5V

Vhi---------------1.206V

V1sw--------------0.959V

Vlo---------------0.480V

GND---------------0V

This provides .248 volts margin on both sides Vhi, while operating
below Vcm for V2sw. Vlo still has .480 volts margin on each side.

Vcm won't interfer till the battery falls to 2.41, assuming the
comparator still works at all.

Of course, if the circuit will run from a 9 volt battery, then I would
go back to the 6.8k common resistor and have huge noise margin and
maximum resistor tolerance.

Are we having too much fun with this simple circuit, yet?

 

John Popelish wrote:
Oops. I need to fix the picture to put Vcm above V2sw.

Nice analysis with practical considerations (though, if I were really
going to go with a 3 volt battery supply, I think I would go with the
low voltage version of the dual comparator). I understand why you are
pushing the noise margin of Vhi to stay under the common mode voltage
limit, but why do you not center Vlo between GND and V1sw? It seems
to me that this reduces the tolerance limit for the lower resistor in
the reference string. Is there some advantage of raising this voltage
that I missed?

Perhaps a better solution to the common mode limit would be to reduce
the common switch resistor a bit more. Something like 4.7k helps
quite a bit. It lowers V1sw (=.959 vs. 1.2 or down 20%) more than it
does V2sw-V1sw (=.495 vs. .50 or down 1%). The 1% drop in V2sw-V1sw
is more than compensated for by making the whole swing usable.

The list changes to:

Vcc---------------3.000V

Vcm---------------1.5V

V2sw--------------1.454V

Vhi---------------1.206V

V1sw--------------0.959V

Vlo---------------0.480V

GND---------------0V

This provides .248 volts margin on both sides Vhi, while operating
below Vcm for V2sw. Vlo still has .480 volts margin on each side.

Vcm won't interfer till the battery falls to 2.41, assuming the
comparator still works at all.

Of course, if the circuit will run from a 9 volt battery, then I would
go back to the 6.8k common resistor and have huge noise margin and
maximum resistor tolerance.

Are we having too much fun with this simple circuit, yet?

 

[John Fields]

On 13 Aug 2005 19:11:56 -0700, jpopelish@rica.net wrote:

John Popelish wrote:
Oops. I need to fix the picture to put Vcm above V2sw.

Nice analysis with practical considerations (though, if I were really
going to go with a 3 volt battery supply, I think I would go with the
low voltage version of the dual comparator). I understand why you are
pushing the noise margin of Vhi to stay under the common mode voltage
limit, but why do you not center Vlo between GND and V1sw? It seems
to me that this reduces the tolerance limit for the lower resistor in
the reference string. Is there some advantage of raising this voltage
that I missed?

---
No. That's a good choice.
---

Perhaps a better solution to the common mode limit would be to reduce
the common switch resistor a bit more.

---
Ah, but that would be cheating! This whole exercise (on my part)
was to come up with an adequate reference divider made from 5%
resistors to be used with your 1.414:1 switching divider, (also made
from 5% resistors) a 3V supply, and an LM393.
---

Something like 4.7k helps
quite a bit. It lowers V1sw (=.959 vs. 1.2 or down 20%) more than it
does V2sw-V1sw (=.495 vs. .50 or down 1%). The 1% drop in V2sw-V1sw
is more than compensated for by making the whole swing usable.

The list changes to:

Vcc---------------3.000V

Vcm---------------1.5V

V2sw--------------1.454V

Vhi---------------1.206V

V1sw--------------0.959V

Vlo---------------0.480V

GND---------------0V

This provides .248 volts margin on both sides Vhi, while operating
below Vcm for V2sw. Vlo still has .480 volts margin on each side.

---
It doesn't matter whether V2sw exceeds the common mode limit as long
as Vhi doesn't, so changing the ratio of the switching divider only
decreases the noise margins.
---

Vcm won't interfer till the battery falls to 2.41, assuming the
comparator still works at all.

Of course, if the circuit will run from a 9 volt battery, then I would
go back to the 6.8k common resistor and have huge noise margin and
maximum resistor tolerance.

---
But you vouldn't be able to have the circuit keep working as the
battery voltage fell to 3V.
---

Are we having too much fun with this simple circuit, yet?

---
I'm done if you are!

--
John Fields
Professional Circuit Designer

 

John Fields wrote:

jpopelish@rica.net wrote:

Nice analysis with practical considerations (though, if I were really
going to go with a 3 volt battery supply, I think I would go with the
low voltage version of the dual comparator). I understand why you are
pushing the noise margin of Vhi to stay under the common mode voltage
limit, but why do you not center Vlo between GND and V1sw? It seems
to me that this reduces the tolerance limit for the lower resistor in
the reference string. Is there some advantage of raising this voltage
that I missed?

---
No. That's a good choice.
---

Perhaps a better solution to the common mode limit would be to reduce
the common switch resistor a bit more.


---
Ah, but that would be cheating! This whole exercise (on my part)
was to come up with an adequate reference divider made from 5%
resistors to be used with your 1.414:1 switching divider, (also made
from 5% resistors) a 3V supply, and an LM393.
---

Something like 4.7k helps
quite a bit. It lowers V1sw (=.959 vs. 1.2 or down 20%) more than it
does V2sw-V1sw (=.495 vs. .50 or down 1%). The 1% drop in V2sw-V1sw
is more than compensated for by making the whole swing usable.

The list changes to:

Vcc---------------3.000V

Vcm---------------1.5V

V2sw--------------1.454V

Vhi---------------1.206V

V1sw--------------0.959V

Vlo---------------0.480V

GND---------------0V

This provides .248 volts margin on both sides Vhi, while operating
below Vcm for V2sw. Vlo still has .480 volts margin on each side.

---
It doesn't matter whether V2sw exceeds the common mode limit as long
as Vhi doesn't, so changing the ratio of the switching divider only
decreases the noise margins.
---


Vcm won't interfer till the battery falls to 2.41, assuming the
comparator still works at all.

Of course, if the circuit will run from a 9 volt battery, then I would
go back to the 6.8k common resistor and have huge noise margin and
maximum resistor tolerance.

---
But you vouldn't be able to have the circuit keep working as the
battery voltage fell to 3V.
---

Are we having too much fun with this simple circuit, yet?

---
I'm done if you are!

This has been an excellent exercise demonstrating how a concept (even
one as simple as a couple voltage dividers) can evolve just by
considering various constraints. But until the O.P. comes back with
some guidence as to what constraints actually apply to his problem, I
guess I am done. I have enjoyed the process.

 

[John Fields]

On 14 Aug 2005 11:20:54 -0700, jpopelish@rica.net wrote:

John Fields wrote:
jpopelish@rica.net wrote:

Are we having too much fun with this simple circuit, yet?

---
I'm done if you are!

This has been an excellent exercise demonstrating how a concept (even
one as simple as a couple voltage dividers) can evolve just by
considering various constraints. But until the O.P. comes back with
some guidence as to what constraints actually apply to his problem, I
guess I am done. I have enjoyed the process.

---
Me too. Thanks!


--
John Fields
Professional Circuit Designer