74HC74 oscillator simulation

[John Larkin]

On Sat, 3 Aug 2019 21:28:55 +0300, Tauno Voipio
<tauno.voipio@notused.fi.invalid> wrote:

On 3.8.19 19:08, bitrex wrote:
On 8/3/19 12:06 PM, bitrex wrote:
IRL I don't think there's anything this configuration of the 'HC74
could do but oscillate; with an RC network from not-Q to not-CLR and
D, CLK, and not-PRE grounded.

But with these models from the Yahoo LTSpice users group the LTSPice
time domain looks like it manages to find some other metastable state
and sits there spinning its wheels.

Can anyone suggest some ICs that could bust it out and get it to
square-wave in the sim? Thanks

https://imgur.com/a/Idv4LSs

plz use this link instead

https://imgur.com/a/ochGSav

Your circuit is simply wrong: there is a stable state
with both Q- and CLR- high.

But \preset is grounded.

The classic oscillator (though bad) is to use a Schmitt
with integrating feedback.

It's an off-label use, but most flops will act as a net inverter in
that circuit. Spice may well not model that mode correctly. But the
voltage gain is typically low so the whole thing might stabilize near
Vcc/2.

More phase shift around the loop can make it oscillate. A gated,
edge-triggered one-shot is sometimes handy, so I've used a similar
circuit to make a flop clear itself, but with a higher-order delay
than the single RC. An RLC works, or a PCB trace delay line. A dual
delay, RCRC, might work too.


--

John Larkin Highland Technology, Inc

lunatic fringe electronics

 

[Rick C]

On Saturday, August 3, 2019 at 3:17:11 PM UTC-4, bitrex wrote:

On 8/3/19 2:40 PM, Rick C wrote:
On Saturday, August 3, 2019 at 2:28:58 PM UTC-4, Tauno Voipio wrote:
On 3.8.19 19:08, bitrex wrote:
On 8/3/19 12:06 PM, bitrex wrote:
IRL I don't think there's anything this configuration of the 'HC74
could do but oscillate; with an RC network from not-Q to not-CLR and
D, CLK, and not-PRE grounded.

But with these models from the Yahoo LTSpice users group the LTSPice
time domain looks like it manages to find some other metastable state
and sits there spinning its wheels.

Can anyone suggest some ICs that could bust it out and get it to
square-wave in the sim? Thanks

https://imgur.com/a/Idv4LSs

plz use this link instead

https://imgur.com/a/ochGSav

Your circuit is simply wrong: there is a stable state
with both Q- and CLR- high.

I think not. The PRE- pin is grounded. If CLR- is high the Q is 1 and Q- is 0. The circuit should work in simulation. If the waveform shown in the picture is anything relative to the Q- output, there is something logically wrong with the simulation... which is very possible if the FF doesn't initialize properly.


I think the oscillator relies on the 0/0 state at the not-PRE/not-CLR
inputs being metastable to start up, but the model's state is not
actually metastable.

Metastability is not needed. Gates in the FF drive the corresponding output high when each input is low. So both Q and Q- will be high when the CLR- input is low. There may be something going on internally if you were clocking it, but clock is grounded.

This circuit is just an inverter between the CLR- and Q- signals.

When RC went low, the Q- output should have gone high. Not sure what is still wrong, but again, I suggest you connect a square wave to the CLR- pin to test the operation of the FF. Q should stay high while Q- is the square wave inverted.

What is going on with the initialization statement? I don't see a "res" signal.

--

Rick C.

-- Get 1,000 miles of free Supercharging
-- Tesla referral code - https://ts.la/richard11209

 

[bitrex]

On 8/3/19 3:47 PM, Rick C wrote:

On Saturday, August 3, 2019 at 3:17:11 PM UTC-4, bitrex wrote:
On 8/3/19 2:40 PM, Rick C wrote:
On Saturday, August 3, 2019 at 2:28:58 PM UTC-4, Tauno Voipio wrote:
On 3.8.19 19:08, bitrex wrote:
On 8/3/19 12:06 PM, bitrex wrote:
IRL I don't think there's anything this configuration of the 'HC74
could do but oscillate; with an RC network from not-Q to not-CLR and
D, CLK, and not-PRE grounded.

But with these models from the Yahoo LTSpice users group the LTSPice
time domain looks like it manages to find some other metastable state
and sits there spinning its wheels.

Can anyone suggest some ICs that could bust it out and get it to
square-wave in the sim? Thanks

https://imgur.com/a/Idv4LSs

plz use this link instead

https://imgur.com/a/ochGSav

Your circuit is simply wrong: there is a stable state
with both Q- and CLR- high.

I think not. The PRE- pin is grounded. If CLR- is high the Q is 1 and Q- is 0. The circuit should work in simulation. If the waveform shown in the picture is anything relative to the Q- output, there is something logically wrong with the simulation... which is very possible if the FF doesn't initialize properly.


I think the oscillator relies on the 0/0 state at the not-PRE/not-CLR
inputs being metastable to start up, but the model's state is not
actually metastable.

Metastability is not needed. Gates in the FF drive the corresponding output high when each input is low. So both Q and Q- will be high when the CLR- input is low. There may be something going on internally if you were clocking it, but clock is grounded.

This circuit is just an inverter between the CLR- and Q- signals.

When RC went low, the Q- output should have gone high. Not sure what is still wrong, but again, I suggest you connect a square wave to the CLR- pin to test the operation of the FF. Q should stay high while Q- is the square wave inverted.

Doesn't pass any signal at all when I do that.

What is going on with the initialization statement? I don't see a "res" signal.

I removed some other stuff before posting but forgot that, sorry

I found a thread on the Yahoo LTSpice users group that might be relevant,

<https://groups.yahoo.com/neo/groups/LTspice/conversations/topics/101425>

"Hello!

I think I found an error in the model 74HC74 in 74HC_v.lib.

When I ground D, CLK, PRE und CLR
then Q is 0V and /Q is VCC but both Q and /Q should be VCC

see function table page 4

http://assets.nexperia.com/documents/data-sheet/74HC_HCT74.pdf

Please can someone verify this error and maybe someone can correct the LIB.

I'm not qualified to correct it.

Thanks for your help!!!!!

Best Regards

Harald"


Looks like a corrected model may have been posted in the thread but it
doesn't look like the model file I downloaded has been updated, nothing
in there about the 'HC74 being revised after the date of the above
thread (2017)

"* 74hc.lib
*
* 74HCxxx Model libraray for LTSPICE from www.linear.com/software
*
*
* Revision 0.55 08/20/2003
* Revision 0.56 08/21/2003
* Revision 0.57 02/04/2005
* Revision 0.58 03/28/2005
* Revision 0.59 03/29/2005
* Revision 0.60 07/09/2006 74HC191 added
* Revision 0.61 10/16/2006 74HC4538 added
* Revision 0.62 10/23/2009 74HC373 typo corrected
* Revision 0.63 11/13/2009 74HC533 added
* Revision 0.64 05/02/2010 74HC40103 added
* Revision 0.65 30/05/2010 74HC244 added
* Revision 0.66 01/30/2012 enabled B(VCC) in input/output driver models
* Revision 0.67 10/04/2013 74HC_IN_0: V=LIMIT(0,V(in) ->
V=LIMIT(0,V(in,VGND)
* Revision 0.68 09/30/2014 corrected a typo HCT to HC in 74HC244
* Revision 0.69 02/01/2019 74HC05 added
*

 

[bitrex]

On 8/3/19 4:32 PM, Rick C wrote:

On Saturday, August 3, 2019 at 4:14:51 PM UTC-4, bitrex wrote:
On 8/3/19 4:00 PM, John Larkin wrote:
On Sat, 3 Aug 2019 15:12:01 -0400, bitrex <user@example.net> wrote:

With the error that I made wrt setting parameters corrected and the sim
tested such that the flip flop divides down and otherwise operates
correctly here is the output in the former configuration, with more
clear labeling of voltages. also no oscillation.

https://imgur.com/a/tHr6Qij

You might try a real flop. The model may not properly handle this
case.



Yeah I don't know if it's a model problem at this point or if this
circuit is just a bust I'm curious now.

It would be amusing/sad if that referenced patent just didn't work at
all. Maybe the crystal makes the "magic" happen

It's not magic. Just that most people aren't familiar with the issues of designing an oscillator. I assume this is not a circuit which is important to operate in a real circuit. Oscillators like this can have intermittent startup problems. I just use oscillators these days. Easier. Even when the oscillator is in an MCU they do a crappy job of specifying the crystal parameters. You have to beg for things like ESR of the crystal. Pick the wrong part and it will work fine on the bench, them may not start reliably with changes in temperature, etc.

You could try working that thread again. I can't find the model you indicate at ADI (bought LT). Try copying the text in Harald's post and make helmut's modification. Harald said that was what worked for him.

I'm just gonna feed a faster Schmitt trigger-oscillator clock into a a
long counter I think so I can divide it down to a few Hz and use the
faster clock for some other purpose. The single gate or two-gate NAND
schmitt oscillator is not sexy but it's pretty reliable.

You're right it might be possible to get this to work with fiddling in
simulation but I need something that will work consistently IRL, not any
point in spending much more effort on it.

I thought it would be cool if there were a way to make say a quad D flop
self-oscillate and divide itself down but sounds like a challenge for
another day

 

[bitrex]

On 8/3/19 4:48 PM, John Larkin wrote:

On Sat, 3 Aug 2019 16:31:23 -0400, bitrex <user@example.net> wrote:

On 8/3/19 1:34 PM, bitrex wrote:
On 8/3/19 12:59 PM, John Larkin wrote:
On Sat, 03 Aug 2019 09:24:40 -0700, John Larkin
jjlarkin@highlandtechnology.com> wrote:

On Sat, 3 Aug 2019 12:06:05 -0400, bitrex <user@example.net> wrote:

IRL I don't think there's anything this configuration of the 'HC74
could
do but oscillate; with an RC network from not-Q to not-CLR and D, CLK,
and not-PRE grounded.

But with these models from the Yahoo LTSpice users group the LTSPice
time domain looks like it manages to find some other metastable state
and sits there spinning its wheels.

Can anyone suggest some ICs that could bust it out and get it to
square-wave in the sim? Thanks

https://imgur.com/a/Idv4LSs

The voltage gain from \Q to \CLR is low,

Actually meant \CLR to \Q, the gain inside the IC.



The easy thing to do to get a square wave is the schmitt inverter, I'd
like a low frequency (10s of Hz) with the Q and not Q outputs but I
don't wanna use a large R, large cap, wanna use a small R and cap that's
relatively cheap to get tight tolerance/tempco on the components.

The easy thing to then do is run a higher frequency from the standard
schmitt inverter with smaller Rc, C into a divider chain.

But it would be cool if there were some self-oscillating structure of
flops that did it all without needing the Schmitt inverter at all, so
far my attempts to find it have been unproductive though

If you have Q and not Q whether from a flip-flop or just from a set of
appropriately-connected inverters it might be possible to bootstrap the
RC constant capacitor somehow instead of grounding it.

I think a ripple counter would work fine to divide down a clock from a
faster Schmitt oscillator, also. Then I could use the fast clock for
some other purpose. That'd be cool.

Packaged XOs are so cheap now it's barely worth making your own
oscillator. Well, maybe a schmitt if the frequency accuracy doesn't
matter much.

Small uPs usually have a pretty good internal oscillator.

uP's are so cheap and easy that there's little reason for me to not
recommend one for most simple projects right off the bat

This is a great tool, it lets you drag and drop little functional blocks
like "voltage controlled" oscillators, logic gates, functional blocks of
various types and bang it up to an 8 pin AVR in about 5 minutes:

<https://xod.io/>


But I don't turn down money because a client asks me to design something
they'd like to build themselves without a uP and wants to pay me some
cash for my nice-dinner-with-the-girlfriend fund for doing it

 

[John Larkin]

On Sat, 3 Aug 2019 16:31:23 -0400, bitrex <user@example.net> wrote:

On 8/3/19 1:34 PM, bitrex wrote:
On 8/3/19 12:59 PM, John Larkin wrote:
On Sat, 03 Aug 2019 09:24:40 -0700, John Larkin
jjlarkin@highlandtechnology.com> wrote:

On Sat, 3 Aug 2019 12:06:05 -0400, bitrex <user@example.net> wrote:

IRL I don't think there's anything this configuration of the 'HC74
could
do but oscillate; with an RC network from not-Q to not-CLR and D, CLK,
and not-PRE grounded.

But with these models from the Yahoo LTSpice users group the LTSPice
time domain looks like it manages to find some other metastable state
and sits there spinning its wheels.

Can anyone suggest some ICs that could bust it out and get it to
square-wave in the sim? Thanks

https://imgur.com/a/Idv4LSs

The voltage gain from \Q to \CLR is low,

Actually meant \CLR to \Q, the gain inside the IC.



The easy thing to do to get a square wave is the schmitt inverter, I'd
like a low frequency (10s of Hz) with the Q and not Q outputs but I
don't wanna use a large R, large cap, wanna use a small R and cap that's
relatively cheap to get tight tolerance/tempco on the components.

The easy thing to then do is run a higher frequency from the standard
schmitt inverter with smaller Rc, C into a divider chain.

But it would be cool if there were some self-oscillating structure of
flops that did it all without needing the Schmitt inverter at all, so
far my attempts to find it have been unproductive though

If you have Q and not Q whether from a flip-flop or just from a set of
appropriately-connected inverters it might be possible to bootstrap the
RC constant capacitor somehow instead of grounding it.

I think a ripple counter would work fine to divide down a clock from a
faster Schmitt oscillator, also. Then I could use the fast clock for
some other purpose. That'd be cool.

Packaged XOs are so cheap now it's barely worth making your own
oscillator. Well, maybe a schmitt if the frequency accuracy doesn't
matter much.

Small uPs usually have a pretty good internal oscillator.


--

John Larkin Highland Technology, Inc

lunatic fringe electronics

 

[Rick C]

On Saturday, August 3, 2019 at 4:43:16 PM UTC-4, bitrex wrote:

On 8/3/19 4:32 PM, Rick C wrote:
On Saturday, August 3, 2019 at 4:14:51 PM UTC-4, bitrex wrote:
On 8/3/19 4:00 PM, John Larkin wrote:
On Sat, 3 Aug 2019 15:12:01 -0400, bitrex <user@example.net> wrote:

With the error that I made wrt setting parameters corrected and the sim
tested such that the flip flop divides down and otherwise operates
correctly here is the output in the former configuration, with more
clear labeling of voltages. also no oscillation.

https://imgur.com/a/tHr6Qij

You might try a real flop. The model may not properly handle this
case.



Yeah I don't know if it's a model problem at this point or if this
circuit is just a bust I'm curious now.

It would be amusing/sad if that referenced patent just didn't work at
all. Maybe the crystal makes the "magic" happen

It's not magic. Just that most people aren't familiar with the issues of designing an oscillator. I assume this is not a circuit which is important to operate in a real circuit. Oscillators like this can have intermittent startup problems. I just use oscillators these days. Easier. Even when the oscillator is in an MCU they do a crappy job of specifying the crystal parameters. You have to beg for things like ESR of the crystal. Pick the wrong part and it will work fine on the bench, them may not start reliably with changes in temperature, etc.

You could try working that thread again. I can't find the model you indicate at ADI (bought LT). Try copying the text in Harald's post and make helmut's modification. Harald said that was what worked for him.


I'm just gonna feed a faster Schmitt trigger-oscillator clock into a a
long counter I think so I can divide it down to a few Hz and use the
faster clock for some other purpose. The single gate or two-gate NAND
schmitt oscillator is not sexy but it's pretty reliable.

You're right it might be possible to get this to work with fiddling in
simulation but I need something that will work consistently IRL, not any
point in spending much more effort on it.

I thought it would be cool if there were a way to make say a quad D flop
self-oscillate and divide itself down but sounds like a challenge for
another day

The circuit is the same as an inverter, just no Schmitt trigger.

The quad FF doesn't have the preset and clear controls that turn one stage into an inverter. You could wire one stage to be a divide by two, use a differentiator to produce glitches with a diode to clamp the low going pulses so they become positive pulses. That would be a tricky circuit.

--

Rick C.

+- Get 1,000 miles of free Supercharging
+- Tesla referral code - https://ts.la/richard11209

 

[bitrex]

On 8/3/19 5:10 PM, bitrex wrote:

Small uPs usually have a pretty good internal oscillator.



uP's are so cheap and easy that there's little reason for me to not
recommend one for most simple projects right off the bat

This is a great tool, it lets you drag and drop little functional blocks
like "voltage controlled" oscillators, logic gates, functional blocks of
various types and bang it up to an 8 pin AVR in about 5 minutes:

https://xod.io/

There's a niche for low-speed hairball logic-like circuitry, that being
able to "program" a microprocessor visually and end up with a "circuit"
but expressed in auto-generated code, but that is provably glitch-free
and that runs on a general-purpose uP that this tool fills very nicely

 

[Rick C]

On Saturday, August 3, 2019 at 11:12:45 PM UTC-4, whit3rd wrote:

On Saturday, August 3, 2019 at 9:06:10 AM UTC-7, bitrex wrote:
IRL I don't think there's anything this configuration of the 'HC74 could
do but oscillate

The innards of a master/slave D flipflop are huge;

By grounding the clock, data input and PRE- input, the "huge" innards are all disabled other than a NAND gate and an output buffer. CLR- to Q- looks like a single inverter.

a simpler
oscillator (ring oscillator) just takes an odd number of inverters,
so in CMOS it starts at six transistors, maybe even two, no external
capacitors/resistors required.

One generally uses other things, to minimize side-effects
(power supply current spikes) , and timing components accurate
over temperature, aging, device variation.

Crystals are good, oscillators are better.

--

Rick C.

++ Get 1,000 miles of free Supercharging
++ Tesla referral code - https://ts.la/richard11209

 

[whit3rd]

On Saturday, August 3, 2019 at 9:06:10 AM UTC-7, bitrex wrote:

IRL I don't think there's anything this configuration of the 'HC74 could
do but oscillate

The innards of a master/slave D flipflop are huge; a simpler
oscillator (ring oscillator) just takes an odd number of inverters,
so in CMOS it starts at six transistors, maybe even two, no external
capacitors/resistors required.

One generally uses other things, to minimize side-effects
(power supply current spikes) , and timing components accurate
over temperature, aging, device variation.

 

[Bill Sloman]

On Sunday, August 4, 2019 at 5:12:06 AM UTC+10, John Larkin wrote:

On Sat, 3 Aug 2019 21:31:15 +0300, Tauno Voipio
tauno.voipio@notused.fi.invalid> wrote:

On 3.8.19 19:58, bitrex wrote:
On 8/3/19 12:24 PM, John Larkin wrote:
On Sat, 3 Aug 2019 12:06:05 -0400, bitrex <user@example.net> wrote:

IRL I don't think there's anything this configuration of the 'HC74 could
do but oscillate; with an RC network from not-Q to not-CLR and D, CLK,
and not-PRE grounded.

But with these models from the Yahoo LTSpice users group the LTSPice
time domain looks like it manages to find some other metastable state
and sits there spinning its wheels.

Can anyone suggest some ICs that could bust it out and get it to
square-wave in the sim? Thanks

https://imgur.com/a/Idv4LSs

The voltage gain from \Q to \CLR is low, and there's no schmitt
action, so you can get a stable negative feedback loop. It would
likely oscillate at a higher frequency, where the logic prop delay
becomes important.

Why not use a schmitt inverter? This circuit could be rescued, but it
would take more parts.

Maybe "ground" C1 to Q?

But I wouldn't trust the Spice models for what is basically analog
behavior.



Check this out someone actually got a patent for this back in 1990 (the
crystal probably helps a lot):

https://imgur.com/a/YryI2p6

An idea can be patented even if it does not work.

For some people, getting patents is a kind of addiction.

Places like IBM, Bell Labs and EMI Central Research had teams of patent lawyers, and a culture where the staff were encourage to put in patent queries..

One of my colleagues at EMI held the record for patent queries filed in any one year. None of them went through. One of the two I got resulted from what had struck me as a perfectly obvious point, but after I'd had to explain it to some half-dozen people I decided that it probably wasn't obvious to those skilled in the art. The patent examiners agreed.

--
Bill Sloman, Sydney

 

[Tom Gardner]

On 04/08/19 04:05, Bill Sloman wrote:

On Sunday, August 4, 2019 at 5:12:06 AM UTC+10, John Larkin wrote:
On Sat, 3 Aug 2019 21:31:15 +0300, Tauno Voipio
tauno.voipio@notused.fi.invalid> wrote:

On 3.8.19 19:58, bitrex wrote:
On 8/3/19 12:24 PM, John Larkin wrote:
On Sat, 3 Aug 2019 12:06:05 -0400, bitrex <user@example.net> wrote:

IRL I don't think there's anything this configuration of the 'HC74
could do but oscillate; with an RC network from not-Q to not-CLR
and D, CLK, and not-PRE grounded.

But with these models from the Yahoo LTSpice users group the
LTSPice time domain looks like it manages to find some other
metastable state and sits there spinning its wheels.

Can anyone suggest some ICs that could bust it out and get it to
square-wave in the sim? Thanks

https://imgur.com/a/Idv4LSs

The voltage gain from \Q to \CLR is low, and there's no schmitt
action, so you can get a stable negative feedback loop. It would
likely oscillate at a higher frequency, where the logic prop delay
becomes important.

Why not use a schmitt inverter? This circuit could be rescued, but
it would take more parts.

Maybe "ground" C1 to Q?

But I wouldn't trust the Spice models for what is basically analog
behavior.



Check this out someone actually got a patent for this back in 1990
(the crystal probably helps a lot):

https://imgur.com/a/YryI2p6

An idea can be patented even if it does not work.

For some people, getting patents is a kind of addiction.

Places like IBM, Bell Labs and EMI Central Research had teams of patent
lawyers, and a culture where the staff were encourage to put in patent
queries.

Rule of thumb: if a company decides to put a /new/
emphasis on getting patents, then someone has
/started/ thinking of selling the company.

One of my colleagues at EMI held the record for patent queries filed in any
one year. None of them went through. One of the two I got resulted from what
had struck me as a perfectly obvious point, but after I'd had to explain it
to some half-dozen people I decided that it probably wasn't obvious to those
skilled in the art. The patent examiners agreed.

Yup; that was my experience too.

 

[bitrex]

On 8/4/19 2:25 AM, Tom Gardner wrote:

On 04/08/19 04:05, Bill Sloman wrote:
On Sunday, August 4, 2019 at 5:12:06 AM UTC+10, John Larkin wrote:
On Sat, 3 Aug 2019 21:31:15 +0300, Tauno Voipio
tauno.voipio@notused.fi.invalid> wrote:

On 3.8.19 19:58, bitrex wrote:
On 8/3/19 12:24 PM, John Larkin wrote:
On Sat, 3 Aug 2019 12:06:05 -0400, bitrex <user@example.net> wrote:

IRL I don't think there's anything this configuration of the 'HC74
could do but oscillate; with an RC network from not-Q to not-CLR
and D, CLK, and not-PRE grounded.

But with these models from the Yahoo LTSpice users group the
LTSPice time domain looks like it manages to find some other
metastable state and sits there spinning its wheels.

Can anyone suggest some ICs that could bust it out and get it to
square-wave in the sim? Thanks

https://imgur.com/a/Idv4LSs

The voltage gain from \Q to \CLR is low, and there's no schmitt
action, so you can get a stable negative feedback loop. It would
likely oscillate at a higher frequency, where the logic prop delay
becomes important.

Why not use a schmitt inverter? This circuit could be rescued, but
it would take more parts.

Maybe "ground" C1 to Q?

But I wouldn't trust the Spice models for what is basically analog
behavior.



Check this out someone actually got a patent for this back in 1990
(the crystal probably helps a lot):

https://imgur.com/a/YryI2p6

An idea can be patented even if it does not work.

For some people, getting patents is a kind of addiction.

Places like IBM, Bell Labs and EMI Central Research had teams of patent
lawyers, and a culture where the staff were encourage to put in patent
queries.

Rule of thumb: if a company decides to put a /new/
emphasis on getting patents, then someone has
/started/ thinking of selling the company.


One of my colleagues at EMI held the record for patent queries filed
in any
one year. None of them went through. One of the two I got resulted
from what
had struck me as a perfectly obvious point, but after I'd had to
explain it
to some half-dozen people I decided that it probably wasn't obvious to
those
skilled in the art. The patent examiners agreed.

Yup; that was my experience too.

Yeah like the double-decker couch!

<https://www.youtube.com/watch?v=G9UZv-egULY>

 

[Robert Baer]

bitrex wrote:

IRL I don't think there's anything this configuration of the 'HC74 could
do but oscillate; with an RC network from not-Q to not-CLR and D, CLK,
and not-PRE grounded.

But with these models from the Yahoo LTSpice users group the LTSPice
time domain looks like it manages to find some other metastable state
and sits there spinning its wheels.

Can anyone suggest some ICs that could bust it out and get it to
square-wave in the sim? Thanks

https://imgur.com/a/Idv4LSs

Zoinks! You've taken a wrong turn.

Let's split up, gang. If you're looking for an image, it's probably been
deleted or may not have existed at all.

If you are looking for groovy images, visit our gallery!

 

[legg]

On Sat, 3 Aug 2019 12:06:05 -0400, bitrex <user@example.net> wrote:

IRL I don't think there's anything this configuration of the 'HC74 could
do but oscillate; with an RC network from not-Q to not-CLR and D, CLK,
and not-PRE grounded.

But with these models from the Yahoo LTSpice users group the LTSPice
time domain looks like it manages to find some other metastable state
and sits there spinning its wheels.

Can anyone suggest some ICs that could bust it out and get it to
square-wave in the sim? Thanks

https://imgur.com/a/Idv4LSs

This recently posted to the Previously-mentioned group:

"In the course of writing my 74LVC1G library I discovered that my
first attempt at the '74 D flip-flop wasn't quite right: the truth
table was correct except for when Set and Reset were both low. The
datasheet states that Q and Qbar should both be high, but Q was in
fact low.

I checked just the A device Dflop and found that the behaviour of
Preset and Clear is complex and incompatible with *74 devices.
Therefore, any 74xx series D flip-flop model that just relies
internally on the A device Dflop will likely be incorrect. I checked
Helmut's 74HC and 74HCT libraries and the '74 devices were incorrect.

I'm surprised that after all these years, nobody has spotted this
subtle error with these libraries!

I haven't checked whether there are other device models in various
libraries with asynchronous Set and Reset that also have this problem
feature.

The truth table of the A device Dflop depends on the order that Preset
and Clear are set. If Preset is set first and remains high and Clear
is set later, Preset overrides Clear and Q remains high and Qbar
remains low. If Clear is set first, then Q remains low and Qbar
remains high. If both are set simultaneously, then Q and Qbar are
latched in the states they were before before Preset and Clear were
set.

If both Preset and Clear are set from t=0 (initialised), Q always
remains low and Qbar remains high.

I have since found that
http://ltwiki.org/index.php?title=Undocumented_LTspice#A-Devices
states that with the Dflop and SRflop, Clear has precedence over
Preset, but that's not the whole story, as that only seems to apply at
initialisation. It is not known whether the observed behaviour is
wholly intended. I would guess that these A devices are extensively
used within the distributed LTspice libraries...

To correct the 74HC74 and 74HCT74 library model static truth tables
requires that the A device Dflop Preset and Q are OR'd and Clear and
Qbar are OR'd for the respective outputs, and the timing adjusted.

Regards,
Tony Casey"

RL

 

[Rick C]

On Sunday, August 4, 2019 at 8:20:09 PM UTC-4, legg wrote:

On Sat, 3 Aug 2019 12:06:05 -0400, bitrex <user@example.net> wrote:

IRL I don't think there's anything this configuration of the 'HC74 could
do but oscillate; with an RC network from not-Q to not-CLR and D, CLK,
and not-PRE grounded.

But with these models from the Yahoo LTSpice users group the LTSPice
time domain looks like it manages to find some other metastable state
and sits there spinning its wheels.

Can anyone suggest some ICs that could bust it out and get it to
square-wave in the sim? Thanks

https://imgur.com/a/Idv4LSs

This recently posted to the Previously-mentioned group:

"In the course of writing my 74LVC1G library I discovered that my
first attempt at the '74 D flip-flop wasn't quite right: the truth
table was correct except for when Set and Reset were both low. The
datasheet states that Q and Qbar should both be high, but Q was in
fact low.

I checked just the A device Dflop and found that the behaviour of
Preset and Clear is complex and incompatible with *74 devices.
Therefore, any 74xx series D flip-flop model that just relies
internally on the A device Dflop will likely be incorrect. I checked
Helmut's 74HC and 74HCT libraries and the '74 devices were incorrect.

I'm surprised that after all these years, nobody has spotted this
subtle error with these libraries!

I haven't checked whether there are other device models in various
libraries with asynchronous Set and Reset that also have this problem
feature.

The truth table of the A device Dflop depends on the order that Preset
and Clear are set. If Preset is set first and remains high and Clear
is set later, Preset overrides Clear and Q remains high and Qbar
remains low. If Clear is set first, then Q remains low and Qbar
remains high. If both are set simultaneously, then Q and Qbar are
latched in the states they were before before Preset and Clear were
set.

If both Preset and Clear are set from t=0 (initialised), Q always
remains low and Qbar remains high.

I have since found that
http://ltwiki.org/index.php?title=Undocumented_LTspice#A-Devices
states that with the Dflop and SRflop, Clear has precedence over
Preset, but that's not the whole story, as that only seems to apply at
initialisation. It is not known whether the observed behaviour is
wholly intended. I would guess that these A devices are extensively
used within the distributed LTspice libraries...

To correct the 74HC74 and 74HCT74 library model static truth tables
requires that the A device Dflop Preset and Q are OR'd and Clear and
Qbar are OR'd for the respective outputs, and the timing adjusted.

Clearly this is not an easy issue to fully grasp. The last bit of this explanation is not correct I think. Rather than ORing the signals listed, they should be NORed or low true ANDed (same thing, different ways of saying it). From the earlier description of how the models currently work, I'm not sure this would properly account for the internal state of the FF however.

--

Rick C.

--- Get 1,000 miles of free Supercharging
--- Tesla referral code - https://ts.la/richard11209

 

[Jasen Betts]

On 2019-08-03, John Larkin <jjlarkin@highlandtechnology.com> wrote:

On Sat, 3 Aug 2019 21:28:55 +0300, Tauno Voipio
tauno.voipio@notused.fi.invalid> wrote:

On 3.8.19 19:08, bitrex wrote:
On 8/3/19 12:06 PM, bitrex wrote:
IRL I don't think there's anything this configuration of the 'HC74
could do but oscillate; with an RC network from not-Q to not-CLR and
D, CLK, and not-PRE grounded.

But with these models from the Yahoo LTSpice users group the LTSPice
time domain looks like it manages to find some other metastable state
and sits there spinning its wheels.

Can anyone suggest some ICs that could bust it out and get it to
square-wave in the sim? Thanks

https://imgur.com/a/Idv4LSs

plz use this link instead

https://imgur.com/a/ochGSav

Your circuit is simply wrong: there is a stable state
with both Q- and CLR- high.


But \preset is grounded.



The classic oscillator (though bad) is to use a Schmitt
with integrating feedback.

It's an off-label use, but most flops will act as a net inverter in
that circuit. Spice may well not model that mode correctly. But the
voltage gain is typically low so the whole thing might stabilize near
Vcc/2.

going by fig 4
https://assets.nexperia.com/documents/data-sheet/74HC_HCT74.pdf

it should work as an inverter.

--
When I tried casting out nines I made a hash of it.