S
salman sheikh
Guest
Hello,
I need a vhdl entity that allows me to write four x-bit values on a
periodic write signal and then read them out sequentially (in 4 clock
cycles) base on a read signal.
So you would have a diagram like something like this:
_ _ _ _
write _| |______| |______| |______| |________
value a b c d
_
read _____________________________________| |_______
value a b c d
Is this best implemented in a single small 4 word fifo or is there
another better approache?
Salman
I need a vhdl entity that allows me to write four x-bit values on a
periodic write signal and then read them out sequentially (in 4 clock
cycles) base on a read signal.
So you would have a diagram like something like this:
_ _ _ _
write _| |______| |______| |______| |________
value a b c d
_
read _____________________________________| |_______
value a b c d
Is this best implemented in a single small 4 word fifo or is there
another better approache?
Salman